1/* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35#include <linux/etherdevice.h> 36#include <linux/mlx4/cmd.h> 37#include <linux/module.h> 38#include <linux/cache.h> 39 40#include "fw.h" 41#include "icm.h" 42 43enum { 44 MLX4_COMMAND_INTERFACE_MIN_REV = 2, 45 MLX4_COMMAND_INTERFACE_MAX_REV = 3, 46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3, 47}; 48 49extern void __buggy_use_of_MLX4_GET(void); 50extern void __buggy_use_of_MLX4_PUT(void); 51 52static bool enable_qos = true; 53module_param(enable_qos, bool, 0444); 54MODULE_PARM_DESC(enable_qos, "Enable Enhanced QoS support (default: on)"); 55 56#define MLX4_GET(dest, source, offset) \ 57 do { \ 58 void *__p = (char *) (source) + (offset); \ 59 u64 val; \ 60 switch (sizeof (dest)) { \ 61 case 1: (dest) = *(u8 *) __p; break; \ 62 case 2: (dest) = be16_to_cpup(__p); break; \ 63 case 4: (dest) = be32_to_cpup(__p); break; \ 64 case 8: val = get_unaligned((u64 *)__p); \ 65 (dest) = be64_to_cpu(val); break; \ 66 default: __buggy_use_of_MLX4_GET(); \ 67 } \ 68 } while (0) 69 70#define MLX4_PUT(dest, source, offset) \ 71 do { \ 72 void *__d = ((char *) (dest) + (offset)); \ 73 switch (sizeof(source)) { \ 74 case 1: *(u8 *) __d = (source); break; \ 75 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \ 76 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \ 77 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \ 78 default: __buggy_use_of_MLX4_PUT(); \ 79 } \ 80 } while (0) 81 82static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags) 83{ 84 static const char *fname[] = { 85 [ 0] = "RC transport", 86 [ 1] = "UC transport", 87 [ 2] = "UD transport", 88 [ 3] = "XRC transport", 89 [ 6] = "SRQ support", 90 [ 7] = "IPoIB checksum offload", 91 [ 8] = "P_Key violation counter", 92 [ 9] = "Q_Key violation counter", 93 [12] = "Dual Port Different Protocol (DPDP) support", 94 [15] = "Big LSO headers", 95 [16] = "MW support", 96 [17] = "APM support", 97 [18] = "Atomic ops support", 98 [19] = "Raw multicast support", 99 [20] = "Address vector port checking support", 100 [21] = "UD multicast support", 101 [30] = "IBoE support", 102 [32] = "Unicast loopback support", 103 [34] = "FCS header control", 104 [37] = "Wake On LAN (port1) support", 105 [38] = "Wake On LAN (port2) support", 106 [40] = "UDP RSS support", 107 [41] = "Unicast VEP steering support", 108 [42] = "Multicast VEP steering support", 109 [48] = "Counters support", 110 [52] = "RSS IP fragments support", 111 [53] = "Port ETS Scheduler support", 112 [55] = "Port link type sensing support", 113 [59] = "Port management change event support", 114 [61] = "64 byte EQE support", 115 [62] = "64 byte CQE support", 116 }; 117 int i; 118 119 mlx4_dbg(dev, "DEV_CAP flags:\n"); 120 for (i = 0; i < ARRAY_SIZE(fname); ++i) 121 if (fname[i] && (flags & (1LL << i))) 122 mlx4_dbg(dev, " %s\n", fname[i]); 123} 124 125static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags) 126{ 127 static const char * const fname[] = { 128 [0] = "RSS support", 129 [1] = "RSS Toeplitz Hash Function support", 130 [2] = "RSS XOR Hash Function support", 131 [3] = "Device managed flow steering support", 132 [4] = "Automatic MAC reassignment support", 133 [5] = "Time stamping support", 134 [6] = "VST (control vlan insertion/stripping) support", 135 [7] = "FSM (MAC anti-spoofing) support", 136 [8] = "Dynamic QP updates support", 137 [9] = "Device managed flow steering IPoIB support", 138 [10] = "TCP/IP offloads/flow-steering for VXLAN support", 139 [11] = "MAD DEMUX (Secure-Host) support", 140 [12] = "Large cache line (>64B) CQE stride support", 141 [13] = "Large cache line (>64B) EQE stride support", 142 [14] = "Ethernet protocol control support", 143 [15] = "Ethernet Backplane autoneg support", 144 [16] = "CONFIG DEV support", 145 [17] = "Asymmetric EQs support", 146 [18] = "More than 80 VFs support", 147 [19] = "Performance optimized for limited rule configuration flow steering support", 148 [20] = "Recoverable error events support", 149 [21] = "Port Remap support", 150 [22] = "QCN support", 151 [23] = "QP rate limiting support", 152 [24] = "Ethernet Flow control statistics support", 153 [25] = "Granular QoS per VF support", 154 [26] = "Port ETS Scheduler support", 155 [27] = "Port beacon support", 156 [28] = "RX-ALL support", 157 }; 158 int i; 159 160 for (i = 0; i < ARRAY_SIZE(fname); ++i) 161 if (fname[i] && (flags & (1LL << i))) 162 mlx4_dbg(dev, " %s\n", fname[i]); 163} 164 165int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg) 166{ 167 struct mlx4_cmd_mailbox *mailbox; 168 u32 *inbox; 169 int err = 0; 170 171#define MOD_STAT_CFG_IN_SIZE 0x100 172 173#define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002 174#define MOD_STAT_CFG_PG_SZ_OFFSET 0x003 175 176 mailbox = mlx4_alloc_cmd_mailbox(dev); 177 if (IS_ERR(mailbox)) 178 return PTR_ERR(mailbox); 179 inbox = mailbox->buf; 180 181 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET); 182 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET); 183 184 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG, 185 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 186 187 mlx4_free_cmd_mailbox(dev, mailbox); 188 return err; 189} 190 191int mlx4_QUERY_FUNC(struct mlx4_dev *dev, struct mlx4_func *func, int slave) 192{ 193 struct mlx4_cmd_mailbox *mailbox; 194 u32 *outbox; 195 u8 in_modifier; 196 u8 field; 197 u16 field16; 198 int err; 199 200#define QUERY_FUNC_BUS_OFFSET 0x00 201#define QUERY_FUNC_DEVICE_OFFSET 0x01 202#define QUERY_FUNC_FUNCTION_OFFSET 0x01 203#define QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET 0x03 204#define QUERY_FUNC_RSVD_EQS_OFFSET 0x04 205#define QUERY_FUNC_MAX_EQ_OFFSET 0x06 206#define QUERY_FUNC_RSVD_UARS_OFFSET 0x0b 207 208 mailbox = mlx4_alloc_cmd_mailbox(dev); 209 if (IS_ERR(mailbox)) 210 return PTR_ERR(mailbox); 211 outbox = mailbox->buf; 212 213 in_modifier = slave; 214 215 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, 0, 216 MLX4_CMD_QUERY_FUNC, 217 MLX4_CMD_TIME_CLASS_A, 218 MLX4_CMD_NATIVE); 219 if (err) 220 goto out; 221 222 MLX4_GET(field, outbox, QUERY_FUNC_BUS_OFFSET); 223 func->bus = field & 0xf; 224 MLX4_GET(field, outbox, QUERY_FUNC_DEVICE_OFFSET); 225 func->device = field & 0xf1; 226 MLX4_GET(field, outbox, QUERY_FUNC_FUNCTION_OFFSET); 227 func->function = field & 0x7; 228 MLX4_GET(field, outbox, QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET); 229 func->physical_function = field & 0xf; 230 MLX4_GET(field16, outbox, QUERY_FUNC_RSVD_EQS_OFFSET); 231 func->rsvd_eqs = field16 & 0xffff; 232 MLX4_GET(field16, outbox, QUERY_FUNC_MAX_EQ_OFFSET); 233 func->max_eq = field16 & 0xffff; 234 MLX4_GET(field, outbox, QUERY_FUNC_RSVD_UARS_OFFSET); 235 func->rsvd_uars = field & 0x0f; 236 237 mlx4_dbg(dev, "Bus: %d, Device: %d, Function: %d, Physical function: %d, Max EQs: %d, Reserved EQs: %d, Reserved UARs: %d\n", 238 func->bus, func->device, func->function, func->physical_function, 239 func->max_eq, func->rsvd_eqs, func->rsvd_uars); 240 241out: 242 mlx4_free_cmd_mailbox(dev, mailbox); 243 return err; 244} 245 246int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave, 247 struct mlx4_vhcr *vhcr, 248 struct mlx4_cmd_mailbox *inbox, 249 struct mlx4_cmd_mailbox *outbox, 250 struct mlx4_cmd_info *cmd) 251{ 252 struct mlx4_priv *priv = mlx4_priv(dev); 253 u8 field, port; 254 u32 size, proxy_qp, qkey; 255 int err = 0; 256 struct mlx4_func func; 257 258#define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0 259#define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1 260#define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4 261#define QUERY_FUNC_CAP_FMR_OFFSET 0x8 262#define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10 263#define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14 264#define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18 265#define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20 266#define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24 267#define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28 268#define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c 269#define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30 270#define QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET 0x48 271 272#define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50 273#define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54 274#define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58 275#define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60 276#define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64 277#define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68 278 279#define QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET 0x6c 280 281#define QUERY_FUNC_CAP_FMR_FLAG 0x80 282#define QUERY_FUNC_CAP_FLAG_RDMA 0x40 283#define QUERY_FUNC_CAP_FLAG_ETH 0x80 284#define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10 285#define QUERY_FUNC_CAP_FLAG_RESD_LKEY 0x08 286#define QUERY_FUNC_CAP_FLAG_VALID_MAILBOX 0x04 287 288#define QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG (1UL << 31) 289#define QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG (1UL << 30) 290 291/* when opcode modifier = 1 */ 292#define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3 293#define QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET 0x4 294#define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8 295#define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc 296 297#define QUERY_FUNC_CAP_QP0_TUNNEL 0x10 298#define QUERY_FUNC_CAP_QP0_PROXY 0x14 299#define QUERY_FUNC_CAP_QP1_TUNNEL 0x18 300#define QUERY_FUNC_CAP_QP1_PROXY 0x1c 301#define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28 302 303#define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40 304#define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80 305#define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10 306#define QUERY_FUNC_CAP_VF_ENABLE_QP0 0x08 307 308#define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80 309#define QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS (1 << 31) 310 311 if (vhcr->op_modifier == 1) { 312 struct mlx4_active_ports actv_ports = 313 mlx4_get_active_ports(dev, slave); 314 int converted_port = mlx4_slave_convert_port( 315 dev, slave, vhcr->in_modifier); 316 317 if (converted_port < 0) 318 return -EINVAL; 319 320 vhcr->in_modifier = converted_port; 321 /* phys-port = logical-port */ 322 field = vhcr->in_modifier - 323 find_first_bit(actv_ports.ports, dev->caps.num_ports); 324 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); 325 326 port = vhcr->in_modifier; 327 proxy_qp = dev->phys_caps.base_proxy_sqpn + 8 * slave + port - 1; 328 329 /* Set nic_info bit to mark new fields support */ 330 field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO; 331 332 if (mlx4_vf_smi_enabled(dev, slave, port) && 333 !mlx4_get_parav_qkey(dev, proxy_qp, &qkey)) { 334 field |= QUERY_FUNC_CAP_VF_ENABLE_QP0; 335 MLX4_PUT(outbox->buf, qkey, 336 QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET); 337 } 338 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET); 339 340 /* size is now the QP number */ 341 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + port - 1; 342 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL); 343 344 size += 2; 345 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL); 346 347 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP0_PROXY); 348 proxy_qp += 2; 349 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP1_PROXY); 350 351 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier], 352 QUERY_FUNC_CAP_PHYS_PORT_ID); 353 354 } else if (vhcr->op_modifier == 0) { 355 struct mlx4_active_ports actv_ports = 356 mlx4_get_active_ports(dev, slave); 357 /* enable rdma and ethernet interfaces, new quota locations, 358 * and reserved lkey 359 */ 360 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA | 361 QUERY_FUNC_CAP_FLAG_QUOTAS | QUERY_FUNC_CAP_FLAG_VALID_MAILBOX | 362 QUERY_FUNC_CAP_FLAG_RESD_LKEY); 363 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET); 364 365 field = min( 366 bitmap_weight(actv_ports.ports, dev->caps.num_ports), 367 dev->caps.num_ports); 368 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); 369 370 size = dev->caps.function_caps; /* set PF behaviours */ 371 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET); 372 373 field = 0; /* protected FMR support not available as yet */ 374 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET); 375 376 size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave]; 377 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); 378 size = dev->caps.num_qps; 379 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP); 380 381 size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave]; 382 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); 383 size = dev->caps.num_srqs; 384 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP); 385 386 size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave]; 387 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); 388 size = dev->caps.num_cqs; 389 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP); 390 391 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) || 392 mlx4_QUERY_FUNC(dev, &func, slave)) { 393 size = vhcr->in_modifier & 394 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ? 395 dev->caps.num_eqs : 396 rounddown_pow_of_two(dev->caps.num_eqs); 397 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 398 size = dev->caps.reserved_eqs; 399 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 400 } else { 401 size = vhcr->in_modifier & 402 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ? 403 func.max_eq : 404 rounddown_pow_of_two(func.max_eq); 405 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 406 size = func.rsvd_eqs; 407 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 408 } 409 410 size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave]; 411 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); 412 size = dev->caps.num_mpts; 413 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP); 414 415 size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave]; 416 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); 417 size = dev->caps.num_mtts; 418 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP); 419 420 size = dev->caps.num_mgms + dev->caps.num_amgms; 421 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); 422 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP); 423 424 size = QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG | 425 QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG; 426 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET); 427 428 size = dev->caps.reserved_lkey + ((slave << 8) & 0xFF00); 429 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET); 430 } else 431 err = -EINVAL; 432 433 return err; 434} 435 436int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u8 gen_or_port, 437 struct mlx4_func_cap *func_cap) 438{ 439 struct mlx4_cmd_mailbox *mailbox; 440 u32 *outbox; 441 u8 field, op_modifier; 442 u32 size, qkey; 443 int err = 0, quotas = 0; 444 u32 in_modifier; 445 446 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */ 447 in_modifier = op_modifier ? gen_or_port : 448 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS; 449 450 mailbox = mlx4_alloc_cmd_mailbox(dev); 451 if (IS_ERR(mailbox)) 452 return PTR_ERR(mailbox); 453 454 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, op_modifier, 455 MLX4_CMD_QUERY_FUNC_CAP, 456 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 457 if (err) 458 goto out; 459 460 outbox = mailbox->buf; 461 462 if (!op_modifier) { 463 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET); 464 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) { 465 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n"); 466 err = -EPROTONOSUPPORT; 467 goto out; 468 } 469 func_cap->flags = field; 470 quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS); 471 472 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); 473 func_cap->num_ports = field; 474 475 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET); 476 func_cap->pf_context_behaviour = size; 477 478 if (quotas) { 479 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); 480 func_cap->qp_quota = size & 0xFFFFFF; 481 482 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); 483 func_cap->srq_quota = size & 0xFFFFFF; 484 485 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); 486 func_cap->cq_quota = size & 0xFFFFFF; 487 488 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); 489 func_cap->mpt_quota = size & 0xFFFFFF; 490 491 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); 492 func_cap->mtt_quota = size & 0xFFFFFF; 493 494 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); 495 func_cap->mcg_quota = size & 0xFFFFFF; 496 497 } else { 498 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP); 499 func_cap->qp_quota = size & 0xFFFFFF; 500 501 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP); 502 func_cap->srq_quota = size & 0xFFFFFF; 503 504 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP); 505 func_cap->cq_quota = size & 0xFFFFFF; 506 507 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP); 508 func_cap->mpt_quota = size & 0xFFFFFF; 509 510 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP); 511 func_cap->mtt_quota = size & 0xFFFFFF; 512 513 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP); 514 func_cap->mcg_quota = size & 0xFFFFFF; 515 } 516 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 517 func_cap->max_eq = size & 0xFFFFFF; 518 519 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 520 func_cap->reserved_eq = size & 0xFFFFFF; 521 522 if (func_cap->flags & QUERY_FUNC_CAP_FLAG_RESD_LKEY) { 523 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET); 524 func_cap->reserved_lkey = size; 525 } else { 526 func_cap->reserved_lkey = 0; 527 } 528 529 func_cap->extra_flags = 0; 530 531 /* Mailbox data from 0x6c and onward should only be treated if 532 * QUERY_FUNC_CAP_FLAG_VALID_MAILBOX is set in func_cap->flags 533 */ 534 if (func_cap->flags & QUERY_FUNC_CAP_FLAG_VALID_MAILBOX) { 535 MLX4_GET(size, outbox, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET); 536 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG) 537 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_BF_RES_QP; 538 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG) 539 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_A0_RES_QP; 540 } 541 542 goto out; 543 } 544 545 /* logical port query */ 546 if (gen_or_port > dev->caps.num_ports) { 547 err = -EINVAL; 548 goto out; 549 } 550 551 MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET); 552 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) { 553 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN) { 554 mlx4_err(dev, "VLAN is enforced on this port\n"); 555 err = -EPROTONOSUPPORT; 556 goto out; 557 } 558 559 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) { 560 mlx4_err(dev, "Force mac is enabled on this port\n"); 561 err = -EPROTONOSUPPORT; 562 goto out; 563 } 564 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) { 565 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET); 566 if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) { 567 mlx4_err(dev, "phy_wqe_gid is enforced on this ib port\n"); 568 err = -EPROTONOSUPPORT; 569 goto out; 570 } 571 } 572 573 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); 574 func_cap->physical_port = field; 575 if (func_cap->physical_port != gen_or_port) { 576 err = -ENOSYS; 577 goto out; 578 } 579 580 if (func_cap->flags1 & QUERY_FUNC_CAP_VF_ENABLE_QP0) { 581 MLX4_GET(qkey, outbox, QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET); 582 func_cap->qp0_qkey = qkey; 583 } else { 584 func_cap->qp0_qkey = 0; 585 } 586 587 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL); 588 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF; 589 590 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY); 591 func_cap->qp0_proxy_qpn = size & 0xFFFFFF; 592 593 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL); 594 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF; 595 596 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY); 597 func_cap->qp1_proxy_qpn = size & 0xFFFFFF; 598 599 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_NIC_INFO) 600 MLX4_GET(func_cap->phys_port_id, outbox, 601 QUERY_FUNC_CAP_PHYS_PORT_ID); 602 603 /* All other resources are allocated by the master, but we still report 604 * 'num' and 'reserved' capabilities as follows: 605 * - num remains the maximum resource index 606 * - 'num - reserved' is the total available objects of a resource, but 607 * resource indices may be less than 'reserved' 608 * TODO: set per-resource quotas */ 609 610out: 611 mlx4_free_cmd_mailbox(dev, mailbox); 612 613 return err; 614} 615 616int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 617{ 618 struct mlx4_cmd_mailbox *mailbox; 619 u32 *outbox; 620 u8 field; 621 u32 field32, flags, ext_flags; 622 u16 size; 623 u16 stat_rate; 624 int err; 625 int i; 626 627#define QUERY_DEV_CAP_OUT_SIZE 0x100 628#define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10 629#define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11 630#define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12 631#define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13 632#define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14 633#define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15 634#define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16 635#define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17 636#define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19 637#define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a 638#define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b 639#define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d 640#define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e 641#define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f 642#define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20 643#define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21 644#define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22 645#define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23 646#define QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET 0x26 647#define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27 648#define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29 649#define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b 650#define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d 651#define QUERY_DEV_CAP_RSS_OFFSET 0x2e 652#define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f 653#define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33 654#define QUERY_DEV_CAP_PORT_BEACON_OFFSET 0x34 655#define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35 656#define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36 657#define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37 658#define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38 659#define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b 660#define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c 661#define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e 662#define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f 663#define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40 664#define QUERY_DEV_CAP_FLAGS_OFFSET 0x44 665#define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48 666#define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49 667#define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b 668#define QUERY_DEV_CAP_BF_OFFSET 0x4c 669#define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d 670#define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e 671#define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f 672#define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51 673#define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52 674#define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55 675#define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56 676#define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61 677#define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62 678#define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63 679#define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64 680#define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65 681#define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66 682#define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67 683#define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68 684#define QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET 0x70 685#define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70 686#define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74 687#define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76 688#define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77 689#define QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE 0x7a 690#define QUERY_DEV_CAP_ECN_QCN_VER_OFFSET 0x7b 691#define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80 692#define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82 693#define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84 694#define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86 695#define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88 696#define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a 697#define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c 698#define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e 699#define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90 700#define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92 701#define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94 702#define QUERY_DEV_CAP_CONFIG_DEV_OFFSET 0x94 703#define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98 704#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0 705#define QUERY_DEV_CAP_ETH_BACKPL_OFFSET 0x9c 706#define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d 707#define QUERY_DEV_CAP_VXLAN 0x9e 708#define QUERY_DEV_CAP_MAD_DEMUX_OFFSET 0xb0 709#define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET 0xa8 710#define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET 0xac 711#define QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET 0xcc 712#define QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET 0xd0 713#define QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET 0xd2 714 715 716 dev_cap->flags2 = 0; 717 mailbox = mlx4_alloc_cmd_mailbox(dev); 718 if (IS_ERR(mailbox)) 719 return PTR_ERR(mailbox); 720 outbox = mailbox->buf; 721 722 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 723 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 724 if (err) 725 goto out; 726 727 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET); 728 dev_cap->reserved_qps = 1 << (field & 0xf); 729 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET); 730 dev_cap->max_qps = 1 << (field & 0x1f); 731 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET); 732 dev_cap->reserved_srqs = 1 << (field >> 4); 733 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET); 734 dev_cap->max_srqs = 1 << (field & 0x1f); 735 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET); 736 dev_cap->max_cq_sz = 1 << field; 737 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET); 738 dev_cap->reserved_cqs = 1 << (field & 0xf); 739 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET); 740 dev_cap->max_cqs = 1 << (field & 0x1f); 741 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET); 742 dev_cap->max_mpts = 1 << (field & 0x3f); 743 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET); 744 dev_cap->reserved_eqs = 1 << (field & 0xf); 745 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET); 746 dev_cap->max_eqs = 1 << (field & 0xf); 747 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET); 748 dev_cap->reserved_mtts = 1 << (field >> 4); 749 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET); 750 dev_cap->max_mrw_sz = 1 << field; 751 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET); 752 dev_cap->reserved_mrws = 1 << (field & 0xf); 753 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET); 754 dev_cap->max_mtt_seg = 1 << (field & 0x3f); 755 MLX4_GET(size, outbox, QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET); 756 dev_cap->num_sys_eqs = size & 0xfff; 757 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET); 758 dev_cap->max_requester_per_qp = 1 << (field & 0x3f); 759 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET); 760 dev_cap->max_responder_per_qp = 1 << (field & 0x3f); 761 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET); 762 field &= 0x1f; 763 if (!field) 764 dev_cap->max_gso_sz = 0; 765 else 766 dev_cap->max_gso_sz = 1 << field; 767 768 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET); 769 if (field & 0x20) 770 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR; 771 if (field & 0x10) 772 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP; 773 field &= 0xf; 774 if (field) { 775 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS; 776 dev_cap->max_rss_tbl_sz = 1 << field; 777 } else 778 dev_cap->max_rss_tbl_sz = 0; 779 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET); 780 dev_cap->max_rdma_global = 1 << (field & 0x3f); 781 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET); 782 dev_cap->local_ca_ack_delay = field & 0x1f; 783 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); 784 dev_cap->num_ports = field & 0xf; 785 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET); 786 dev_cap->max_msg_sz = 1 << (field & 0x1f); 787 MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET); 788 if (field & 0x10) 789 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN; 790 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 791 if (field & 0x80) 792 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN; 793 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f; 794 MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_BEACON_OFFSET); 795 if (field & 0x80) 796 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_BEACON; 797 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); 798 if (field & 0x80) 799 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB; 800 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET); 801 dev_cap->fs_max_num_qp_per_entry = field; 802 MLX4_GET(field, outbox, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); 803 if (field & 0x1) 804 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QCN; 805 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET); 806 dev_cap->stat_rate_support = stat_rate; 807 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 808 if (field & 0x80) 809 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS; 810 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 811 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET); 812 dev_cap->flags = flags | (u64)ext_flags << 32; 813 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET); 814 dev_cap->reserved_uars = field >> 4; 815 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET); 816 dev_cap->uar_size = 1 << ((field & 0x3f) + 20); 817 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET); 818 dev_cap->min_page_sz = 1 << field; 819 820 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET); 821 if (field & 0x80) { 822 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET); 823 dev_cap->bf_reg_size = 1 << (field & 0x1f); 824 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET); 825 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size)) 826 field = 3; 827 dev_cap->bf_regs_per_page = 1 << (field & 0x3f); 828 } else { 829 dev_cap->bf_reg_size = 0; 830 } 831 832 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET); 833 dev_cap->max_sq_sg = field; 834 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET); 835 dev_cap->max_sq_desc_sz = size; 836 837 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET); 838 dev_cap->max_qp_per_mcg = 1 << field; 839 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET); 840 dev_cap->reserved_mgms = field & 0xf; 841 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET); 842 dev_cap->max_mcgs = 1 << field; 843 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET); 844 dev_cap->reserved_pds = field >> 4; 845 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET); 846 dev_cap->max_pds = 1 << (field & 0x3f); 847 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET); 848 dev_cap->reserved_xrcds = field >> 4; 849 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET); 850 dev_cap->max_xrcds = 1 << (field & 0x1f); 851 852 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET); 853 dev_cap->rdmarc_entry_sz = size; 854 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET); 855 dev_cap->qpc_entry_sz = size; 856 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET); 857 dev_cap->aux_entry_sz = size; 858 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET); 859 dev_cap->altc_entry_sz = size; 860 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET); 861 dev_cap->eqc_entry_sz = size; 862 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET); 863 dev_cap->cqc_entry_sz = size; 864 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET); 865 dev_cap->srq_entry_sz = size; 866 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET); 867 dev_cap->cmpt_entry_sz = size; 868 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET); 869 dev_cap->mtt_entry_sz = size; 870 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET); 871 dev_cap->dmpt_entry_sz = size; 872 873 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET); 874 dev_cap->max_srq_sz = 1 << field; 875 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET); 876 dev_cap->max_qp_sz = 1 << field; 877 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET); 878 dev_cap->resize_srq = field & 1; 879 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET); 880 dev_cap->max_rq_sg = field; 881 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET); 882 dev_cap->max_rq_desc_sz = size; 883 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); 884 if (field & (1 << 4)) 885 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QOS_VPP; 886 if (field & (1 << 5)) 887 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL; 888 if (field & (1 << 6)) 889 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 890 if (field & (1 << 7)) 891 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 892 MLX4_GET(dev_cap->bmme_flags, outbox, 893 QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 894 if (dev_cap->bmme_flags & MLX4_FLAG_PORT_REMAP) 895 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_REMAP; 896 MLX4_GET(field, outbox, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); 897 if (field & 0x20) 898 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CONFIG_DEV; 899 if (field & (1 << 2)) 900 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_IGNORE_FCS; 901 MLX4_GET(dev_cap->reserved_lkey, outbox, 902 QUERY_DEV_CAP_RSVD_LKEY_OFFSET); 903 MLX4_GET(field32, outbox, QUERY_DEV_CAP_ETH_BACKPL_OFFSET); 904 if (field32 & (1 << 0)) 905 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP; 906 if (field32 & (1 << 7)) 907 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT; 908 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC); 909 if (field & 1<<6) 910 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN; 911 MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN); 912 if (field & 1<<3) 913 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS; 914 if (field & (1 << 5)) 915 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG; 916 MLX4_GET(dev_cap->max_icm_sz, outbox, 917 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET); 918 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS) 919 MLX4_GET(dev_cap->max_counters, outbox, 920 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET); 921 922 MLX4_GET(field32, outbox, 923 QUERY_DEV_CAP_MAD_DEMUX_OFFSET); 924 if (field32 & (1 << 0)) 925 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX; 926 927 MLX4_GET(dev_cap->dmfs_high_rate_qpn_base, outbox, 928 QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET); 929 dev_cap->dmfs_high_rate_qpn_base &= MGM_QPN_MASK; 930 MLX4_GET(dev_cap->dmfs_high_rate_qpn_range, outbox, 931 QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET); 932 dev_cap->dmfs_high_rate_qpn_range &= MGM_QPN_MASK; 933 934 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET); 935 dev_cap->rl_caps.num_rates = size; 936 if (dev_cap->rl_caps.num_rates) { 937 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT; 938 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET); 939 dev_cap->rl_caps.max_val = size & 0xfff; 940 dev_cap->rl_caps.max_unit = size >> 14; 941 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET); 942 dev_cap->rl_caps.min_val = size & 0xfff; 943 dev_cap->rl_caps.min_unit = size >> 14; 944 } 945 946 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 947 if (field32 & (1 << 16)) 948 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP; 949 if (field32 & (1 << 26)) 950 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL; 951 if (field32 & (1 << 20)) 952 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM; 953 if (field32 & (1 << 21)) 954 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_80_VFS; 955 956 for (i = 1; i <= dev_cap->num_ports; i++) { 957 err = mlx4_QUERY_PORT(dev, i, dev_cap->port_cap + i); 958 if (err) 959 goto out; 960 } 961 962 /* 963 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then 964 * we can't use any EQs whose doorbell falls on that page, 965 * even if the EQ itself isn't reserved. 966 */ 967 if (dev_cap->num_sys_eqs == 0) 968 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4, 969 dev_cap->reserved_eqs); 970 else 971 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SYS_EQS; 972 973out: 974 mlx4_free_cmd_mailbox(dev, mailbox); 975 return err; 976} 977 978void mlx4_dev_cap_dump(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 979{ 980 if (dev_cap->bf_reg_size > 0) 981 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n", 982 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page); 983 else 984 mlx4_dbg(dev, "BlueFlame not available\n"); 985 986 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n", 987 dev_cap->bmme_flags, dev_cap->reserved_lkey); 988 mlx4_dbg(dev, "Max ICM size %lld MB\n", 989 (unsigned long long) dev_cap->max_icm_sz >> 20); 990 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n", 991 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz); 992 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n", 993 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz); 994 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n", 995 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz); 996 mlx4_dbg(dev, "Num sys EQs: %d, max EQs: %d, reserved EQs: %d, entry size: %d\n", 997 dev_cap->num_sys_eqs, dev_cap->max_eqs, dev_cap->reserved_eqs, 998 dev_cap->eqc_entry_sz); 999 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n", 1000 dev_cap->reserved_mrws, dev_cap->reserved_mtts); 1001 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n", 1002 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars); 1003 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n", 1004 dev_cap->max_pds, dev_cap->reserved_mgms); 1005 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", 1006 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz); 1007 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n", 1008 dev_cap->local_ca_ack_delay, 128 << dev_cap->port_cap[1].ib_mtu, 1009 dev_cap->port_cap[1].max_port_width); 1010 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n", 1011 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg); 1012 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n", 1013 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg); 1014 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz); 1015 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters); 1016 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz); 1017 mlx4_dbg(dev, "DMFS high rate steer QPn base: %d\n", 1018 dev_cap->dmfs_high_rate_qpn_base); 1019 mlx4_dbg(dev, "DMFS high rate steer QPn range: %d\n", 1020 dev_cap->dmfs_high_rate_qpn_range); 1021 1022 if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT) { 1023 struct mlx4_rate_limit_caps *rl_caps = &dev_cap->rl_caps; 1024 1025 mlx4_dbg(dev, "QP Rate-Limit: #rates %d, unit/val max %d/%d, min %d/%d\n", 1026 rl_caps->num_rates, rl_caps->max_unit, rl_caps->max_val, 1027 rl_caps->min_unit, rl_caps->min_val); 1028 } 1029 1030 dump_dev_cap_flags(dev, dev_cap->flags); 1031 dump_dev_cap_flags2(dev, dev_cap->flags2); 1032} 1033 1034int mlx4_QUERY_PORT(struct mlx4_dev *dev, int port, struct mlx4_port_cap *port_cap) 1035{ 1036 struct mlx4_cmd_mailbox *mailbox; 1037 u32 *outbox; 1038 u8 field; 1039 u32 field32; 1040 int err; 1041 1042 mailbox = mlx4_alloc_cmd_mailbox(dev); 1043 if (IS_ERR(mailbox)) 1044 return PTR_ERR(mailbox); 1045 outbox = mailbox->buf; 1046 1047 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 1048 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 1049 MLX4_CMD_TIME_CLASS_A, 1050 MLX4_CMD_NATIVE); 1051 1052 if (err) 1053 goto out; 1054 1055 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); 1056 port_cap->max_vl = field >> 4; 1057 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET); 1058 port_cap->ib_mtu = field >> 4; 1059 port_cap->max_port_width = field & 0xf; 1060 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET); 1061 port_cap->max_gids = 1 << (field & 0xf); 1062 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET); 1063 port_cap->max_pkeys = 1 << (field & 0xf); 1064 } else { 1065#define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00 1066#define QUERY_PORT_MTU_OFFSET 0x01 1067#define QUERY_PORT_ETH_MTU_OFFSET 0x02 1068#define QUERY_PORT_WIDTH_OFFSET 0x06 1069#define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07 1070#define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a 1071#define QUERY_PORT_MAX_VL_OFFSET 0x0b 1072#define QUERY_PORT_MAC_OFFSET 0x10 1073#define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18 1074#define QUERY_PORT_WAVELENGTH_OFFSET 0x1c 1075#define QUERY_PORT_TRANS_CODE_OFFSET 0x20 1076 1077 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, MLX4_CMD_QUERY_PORT, 1078 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 1079 if (err) 1080 goto out; 1081 1082 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET); 1083 port_cap->supported_port_types = field & 3; 1084 port_cap->suggested_type = (field >> 3) & 1; 1085 port_cap->default_sense = (field >> 4) & 1; 1086 port_cap->dmfs_optimized_state = (field >> 5) & 1; 1087 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET); 1088 port_cap->ib_mtu = field & 0xf; 1089 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET); 1090 port_cap->max_port_width = field & 0xf; 1091 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET); 1092 port_cap->max_gids = 1 << (field >> 4); 1093 port_cap->max_pkeys = 1 << (field & 0xf); 1094 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET); 1095 port_cap->max_vl = field & 0xf; 1096 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET); 1097 port_cap->log_max_macs = field & 0xf; 1098 port_cap->log_max_vlans = field >> 4; 1099 MLX4_GET(port_cap->eth_mtu, outbox, QUERY_PORT_ETH_MTU_OFFSET); 1100 MLX4_GET(port_cap->def_mac, outbox, QUERY_PORT_MAC_OFFSET); 1101 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET); 1102 port_cap->trans_type = field32 >> 24; 1103 port_cap->vendor_oui = field32 & 0xffffff; 1104 MLX4_GET(port_cap->wavelength, outbox, QUERY_PORT_WAVELENGTH_OFFSET); 1105 MLX4_GET(port_cap->trans_code, outbox, QUERY_PORT_TRANS_CODE_OFFSET); 1106 } 1107 1108out: 1109 mlx4_free_cmd_mailbox(dev, mailbox); 1110 return err; 1111} 1112 1113#define DEV_CAP_EXT_2_FLAG_PFC_COUNTERS (1 << 28) 1114#define DEV_CAP_EXT_2_FLAG_VLAN_CONTROL (1 << 26) 1115#define DEV_CAP_EXT_2_FLAG_80_VFS (1 << 21) 1116#define DEV_CAP_EXT_2_FLAG_FSM (1 << 20) 1117 1118int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, 1119 struct mlx4_vhcr *vhcr, 1120 struct mlx4_cmd_mailbox *inbox, 1121 struct mlx4_cmd_mailbox *outbox, 1122 struct mlx4_cmd_info *cmd) 1123{ 1124 u64 flags; 1125 int err = 0; 1126 u8 field; 1127 u16 field16; 1128 u32 bmme_flags, field32; 1129 int real_port; 1130 int slave_port; 1131 int first_port; 1132 struct mlx4_active_ports actv_ports; 1133 1134 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 1135 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1136 if (err) 1137 return err; 1138 1139 /* add port mng change event capability and disable mw type 1 1140 * unconditionally to slaves 1141 */ 1142 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 1143 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV; 1144 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW; 1145 actv_ports = mlx4_get_active_ports(dev, slave); 1146 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports); 1147 for (slave_port = 0, real_port = first_port; 1148 real_port < first_port + 1149 bitmap_weight(actv_ports.ports, dev->caps.num_ports); 1150 ++real_port, ++slave_port) { 1151 if (flags & (MLX4_DEV_CAP_FLAG_WOL_PORT1 << real_port)) 1152 flags |= MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port; 1153 else 1154 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port); 1155 } 1156 for (; slave_port < dev->caps.num_ports; ++slave_port) 1157 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port); 1158 1159 /* Not exposing RSS IP fragments to guests */ 1160 flags &= ~MLX4_DEV_CAP_FLAG_RSS_IP_FRAG; 1161 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 1162 1163 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET); 1164 field &= ~0x0F; 1165 field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F; 1166 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET); 1167 1168 /* For guests, disable timestamp */ 1169 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 1170 field &= 0x7f; 1171 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 1172 1173 /* For guests, disable vxlan tunneling and QoS support */ 1174 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN); 1175 field &= 0xd7; 1176 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN); 1177 1178 /* For guests, disable port BEACON */ 1179 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_PORT_BEACON_OFFSET); 1180 field &= 0x7f; 1181 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_PORT_BEACON_OFFSET); 1182 1183 /* For guests, report Blueflame disabled */ 1184 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET); 1185 field &= 0x7f; 1186 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET); 1187 1188 /* For guests, disable mw type 2 and port remap*/ 1189 MLX4_GET(bmme_flags, outbox->buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 1190 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN; 1191 bmme_flags &= ~MLX4_FLAG_PORT_REMAP; 1192 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 1193 1194 /* turn off device-managed steering capability if not enabled */ 1195 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) { 1196 MLX4_GET(field, outbox->buf, 1197 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 1198 field &= 0x7f; 1199 MLX4_PUT(outbox->buf, field, 1200 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 1201 } 1202 1203 /* turn off ipoib managed steering for guests */ 1204 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); 1205 field &= ~0x80; 1206 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); 1207 1208 /* turn off host side virt features (VST, FSM, etc) for guests */ 1209 MLX4_GET(field32, outbox->buf, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 1210 field32 &= ~(DEV_CAP_EXT_2_FLAG_VLAN_CONTROL | DEV_CAP_EXT_2_FLAG_80_VFS | 1211 DEV_CAP_EXT_2_FLAG_FSM | DEV_CAP_EXT_2_FLAG_PFC_COUNTERS); 1212 MLX4_PUT(outbox->buf, field32, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 1213 1214 /* turn off QCN for guests */ 1215 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); 1216 field &= 0xfe; 1217 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); 1218 1219 /* turn off QP max-rate limiting for guests */ 1220 field16 = 0; 1221 MLX4_PUT(outbox->buf, field16, QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET); 1222 1223 /* turn off QoS per VF support for guests */ 1224 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); 1225 field &= 0xef; 1226 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); 1227 1228 /* turn off ignore FCS feature for guests */ 1229 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); 1230 field &= 0xfb; 1231 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); 1232 1233 return 0; 1234} 1235 1236int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, 1237 struct mlx4_vhcr *vhcr, 1238 struct mlx4_cmd_mailbox *inbox, 1239 struct mlx4_cmd_mailbox *outbox, 1240 struct mlx4_cmd_info *cmd) 1241{ 1242 struct mlx4_priv *priv = mlx4_priv(dev); 1243 u64 def_mac; 1244 u8 port_type; 1245 u16 short_field; 1246 int err; 1247 int admin_link_state; 1248 int port = mlx4_slave_convert_port(dev, slave, 1249 vhcr->in_modifier & 0xFF); 1250 1251#define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0 1252#define MLX4_PORT_LINK_UP_MASK 0x80 1253#define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c 1254#define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e 1255 1256 if (port < 0) 1257 return -EINVAL; 1258 1259 /* Protect against untrusted guests: enforce that this is the 1260 * QUERY_PORT general query. 1261 */ 1262 if (vhcr->op_modifier || vhcr->in_modifier & ~0xFF) 1263 return -EINVAL; 1264 1265 vhcr->in_modifier = port; 1266 1267 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0, 1268 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 1269 MLX4_CMD_NATIVE); 1270 1271 if (!err && dev->caps.function != slave) { 1272 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac; 1273 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET); 1274 1275 /* get port type - currently only eth is enabled */ 1276 MLX4_GET(port_type, outbox->buf, 1277 QUERY_PORT_SUPPORTED_TYPE_OFFSET); 1278 1279 /* No link sensing allowed */ 1280 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK; 1281 /* set port type to currently operating port type */ 1282 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3); 1283 1284 admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state; 1285 if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state) 1286 port_type |= MLX4_PORT_LINK_UP_MASK; 1287 else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state) 1288 port_type &= ~MLX4_PORT_LINK_UP_MASK; 1289 1290 MLX4_PUT(outbox->buf, port_type, 1291 QUERY_PORT_SUPPORTED_TYPE_OFFSET); 1292 1293 if (dev->caps.port_type[vhcr->in_modifier] == MLX4_PORT_TYPE_ETH) 1294 short_field = mlx4_get_slave_num_gids(dev, slave, port); 1295 else 1296 short_field = 1; /* slave max gids */ 1297 MLX4_PUT(outbox->buf, short_field, 1298 QUERY_PORT_CUR_MAX_GID_OFFSET); 1299 1300 short_field = dev->caps.pkey_table_len[vhcr->in_modifier]; 1301 MLX4_PUT(outbox->buf, short_field, 1302 QUERY_PORT_CUR_MAX_PKEY_OFFSET); 1303 } 1304 1305 return err; 1306} 1307 1308int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, 1309 int *gid_tbl_len, int *pkey_tbl_len) 1310{ 1311 struct mlx4_cmd_mailbox *mailbox; 1312 u32 *outbox; 1313 u16 field; 1314 int err; 1315 1316 mailbox = mlx4_alloc_cmd_mailbox(dev); 1317 if (IS_ERR(mailbox)) 1318 return PTR_ERR(mailbox); 1319 1320 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, 1321 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 1322 MLX4_CMD_WRAPPED); 1323 if (err) 1324 goto out; 1325 1326 outbox = mailbox->buf; 1327 1328 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET); 1329 *gid_tbl_len = field; 1330 1331 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET); 1332 *pkey_tbl_len = field; 1333 1334out: 1335 mlx4_free_cmd_mailbox(dev, mailbox); 1336 return err; 1337} 1338EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len); 1339 1340int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt) 1341{ 1342 struct mlx4_cmd_mailbox *mailbox; 1343 struct mlx4_icm_iter iter; 1344 __be64 *pages; 1345 int lg; 1346 int nent = 0; 1347 int i; 1348 int err = 0; 1349 int ts = 0, tc = 0; 1350 1351 mailbox = mlx4_alloc_cmd_mailbox(dev); 1352 if (IS_ERR(mailbox)) 1353 return PTR_ERR(mailbox); 1354 pages = mailbox->buf; 1355 1356 for (mlx4_icm_first(icm, &iter); 1357 !mlx4_icm_last(&iter); 1358 mlx4_icm_next(&iter)) { 1359 /* 1360 * We have to pass pages that are aligned to their 1361 * size, so find the least significant 1 in the 1362 * address or size and use that as our log2 size. 1363 */ 1364 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1; 1365 if (lg < MLX4_ICM_PAGE_SHIFT) { 1366 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx)\n", 1367 MLX4_ICM_PAGE_SIZE, 1368 (unsigned long long) mlx4_icm_addr(&iter), 1369 mlx4_icm_size(&iter)); 1370 err = -EINVAL; 1371 goto out; 1372 } 1373 1374 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) { 1375 if (virt != -1) { 1376 pages[nent * 2] = cpu_to_be64(virt); 1377 virt += 1 << lg; 1378 } 1379 1380 pages[nent * 2 + 1] = 1381 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) | 1382 (lg - MLX4_ICM_PAGE_SHIFT)); 1383 ts += 1 << (lg - 10); 1384 ++tc; 1385 1386 if (++nent == MLX4_MAILBOX_SIZE / 16) { 1387 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, 1388 MLX4_CMD_TIME_CLASS_B, 1389 MLX4_CMD_NATIVE); 1390 if (err) 1391 goto out; 1392 nent = 0; 1393 } 1394 } 1395 } 1396 1397 if (nent) 1398 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, 1399 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 1400 if (err) 1401 goto out; 1402 1403 switch (op) { 1404 case MLX4_CMD_MAP_FA: 1405 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW\n", tc, ts); 1406 break; 1407 case MLX4_CMD_MAP_ICM_AUX: 1408 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux\n", tc, ts); 1409 break; 1410 case MLX4_CMD_MAP_ICM: 1411 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM\n", 1412 tc, ts, (unsigned long long) virt - (ts << 10)); 1413 break; 1414 } 1415 1416out: 1417 mlx4_free_cmd_mailbox(dev, mailbox); 1418 return err; 1419} 1420 1421int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm) 1422{ 1423 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1); 1424} 1425 1426int mlx4_UNMAP_FA(struct mlx4_dev *dev) 1427{ 1428 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, 1429 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 1430} 1431 1432 1433int mlx4_RUN_FW(struct mlx4_dev *dev) 1434{ 1435 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, 1436 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1437} 1438 1439int mlx4_QUERY_FW(struct mlx4_dev *dev) 1440{ 1441 struct mlx4_fw *fw = &mlx4_priv(dev)->fw; 1442 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; 1443 struct mlx4_cmd_mailbox *mailbox; 1444 u32 *outbox; 1445 int err = 0; 1446 u64 fw_ver; 1447 u16 cmd_if_rev; 1448 u8 lg; 1449 1450#define QUERY_FW_OUT_SIZE 0x100 1451#define QUERY_FW_VER_OFFSET 0x00 1452#define QUERY_FW_PPF_ID 0x09 1453#define QUERY_FW_CMD_IF_REV_OFFSET 0x0a 1454#define QUERY_FW_MAX_CMD_OFFSET 0x0f 1455#define QUERY_FW_ERR_START_OFFSET 0x30 1456#define QUERY_FW_ERR_SIZE_OFFSET 0x38 1457#define QUERY_FW_ERR_BAR_OFFSET 0x3c 1458 1459#define QUERY_FW_SIZE_OFFSET 0x00 1460#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20 1461#define QUERY_FW_CLR_INT_BAR_OFFSET 0x28 1462 1463#define QUERY_FW_COMM_BASE_OFFSET 0x40 1464#define QUERY_FW_COMM_BAR_OFFSET 0x48 1465 1466#define QUERY_FW_CLOCK_OFFSET 0x50 1467#define QUERY_FW_CLOCK_BAR 0x58 1468 1469 mailbox = mlx4_alloc_cmd_mailbox(dev); 1470 if (IS_ERR(mailbox)) 1471 return PTR_ERR(mailbox); 1472 outbox = mailbox->buf; 1473 1474 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW, 1475 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1476 if (err) 1477 goto out; 1478 1479 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET); 1480 /* 1481 * FW subminor version is at more significant bits than minor 1482 * version, so swap here. 1483 */ 1484 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) | 1485 ((fw_ver & 0xffff0000ull) >> 16) | 1486 ((fw_ver & 0x0000ffffull) << 16); 1487 1488 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID); 1489 dev->caps.function = lg; 1490 1491 if (mlx4_is_slave(dev)) 1492 goto out; 1493 1494 1495 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET); 1496 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV || 1497 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) { 1498 mlx4_err(dev, "Installed FW has unsupported command interface revision %d\n", 1499 cmd_if_rev); 1500 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n", 1501 (int) (dev->caps.fw_ver >> 32), 1502 (int) (dev->caps.fw_ver >> 16) & 0xffff, 1503 (int) dev->caps.fw_ver & 0xffff); 1504 mlx4_err(dev, "This driver version supports only revisions %d to %d\n", 1505 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV); 1506 err = -ENODEV; 1507 goto out; 1508 } 1509 1510 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS) 1511 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS; 1512 1513 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET); 1514 cmd->max_cmds = 1 << lg; 1515 1516 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n", 1517 (int) (dev->caps.fw_ver >> 32), 1518 (int) (dev->caps.fw_ver >> 16) & 0xffff, 1519 (int) dev->caps.fw_ver & 0xffff, 1520 cmd_if_rev, cmd->max_cmds); 1521 1522 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET); 1523 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET); 1524 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET); 1525 fw->catas_bar = (fw->catas_bar >> 6) * 2; 1526 1527 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n", 1528 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar); 1529 1530 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET); 1531 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET); 1532 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET); 1533 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2; 1534 1535 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET); 1536 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET); 1537 fw->comm_bar = (fw->comm_bar >> 6) * 2; 1538 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n", 1539 fw->comm_bar, fw->comm_base); 1540 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2); 1541 1542 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET); 1543 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR); 1544 fw->clock_bar = (fw->clock_bar >> 6) * 2; 1545 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n", 1546 fw->clock_bar, fw->clock_offset); 1547 1548 /* 1549 * Round up number of system pages needed in case 1550 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. 1551 */ 1552 fw->fw_pages = 1553 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> 1554 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); 1555 1556 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n", 1557 (unsigned long long) fw->clr_int_base, fw->clr_int_bar); 1558 1559out: 1560 mlx4_free_cmd_mailbox(dev, mailbox); 1561 return err; 1562} 1563 1564int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, 1565 struct mlx4_vhcr *vhcr, 1566 struct mlx4_cmd_mailbox *inbox, 1567 struct mlx4_cmd_mailbox *outbox, 1568 struct mlx4_cmd_info *cmd) 1569{ 1570 u8 *outbuf; 1571 int err; 1572 1573 outbuf = outbox->buf; 1574 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW, 1575 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1576 if (err) 1577 return err; 1578 1579 /* for slaves, set pci PPF ID to invalid and zero out everything 1580 * else except FW version */ 1581 outbuf[0] = outbuf[1] = 0; 1582 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8); 1583 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID; 1584 1585 return 0; 1586} 1587 1588static void get_board_id(void *vsd, char *board_id) 1589{ 1590 int i; 1591 1592#define VSD_OFFSET_SIG1 0x00 1593#define VSD_OFFSET_SIG2 0xde 1594#define VSD_OFFSET_MLX_BOARD_ID 0xd0 1595#define VSD_OFFSET_TS_BOARD_ID 0x20 1596 1597#define VSD_SIGNATURE_TOPSPIN 0x5ad 1598 1599 memset(board_id, 0, MLX4_BOARD_ID_LEN); 1600 1601 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN && 1602 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) { 1603 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN); 1604 } else { 1605 /* 1606 * The board ID is a string but the firmware byte 1607 * swaps each 4-byte word before passing it back to 1608 * us. Therefore we need to swab it before printing. 1609 */ 1610 u32 *bid_u32 = (u32 *)board_id; 1611 1612 for (i = 0; i < 4; ++i) { 1613 u32 *addr; 1614 u32 val; 1615 1616 addr = (u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4); 1617 val = get_unaligned(addr); 1618 val = swab32(val); 1619 put_unaligned(val, &bid_u32[i]); 1620 } 1621 } 1622} 1623 1624int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter) 1625{ 1626 struct mlx4_cmd_mailbox *mailbox; 1627 u32 *outbox; 1628 int err; 1629 1630#define QUERY_ADAPTER_OUT_SIZE 0x100 1631#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10 1632#define QUERY_ADAPTER_VSD_OFFSET 0x20 1633 1634 mailbox = mlx4_alloc_cmd_mailbox(dev); 1635 if (IS_ERR(mailbox)) 1636 return PTR_ERR(mailbox); 1637 outbox = mailbox->buf; 1638 1639 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER, 1640 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1641 if (err) 1642 goto out; 1643 1644 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET); 1645 1646 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4, 1647 adapter->board_id); 1648 1649out: 1650 mlx4_free_cmd_mailbox(dev, mailbox); 1651 return err; 1652} 1653 1654int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param) 1655{ 1656 struct mlx4_cmd_mailbox *mailbox; 1657 __be32 *inbox; 1658 int err; 1659 static const u8 a0_dmfs_hw_steering[] = { 1660 [MLX4_STEERING_DMFS_A0_DEFAULT] = 0, 1661 [MLX4_STEERING_DMFS_A0_DYNAMIC] = 1, 1662 [MLX4_STEERING_DMFS_A0_STATIC] = 2, 1663 [MLX4_STEERING_DMFS_A0_DISABLE] = 3 1664 }; 1665 1666#define INIT_HCA_IN_SIZE 0x200 1667#define INIT_HCA_VERSION_OFFSET 0x000 1668#define INIT_HCA_VERSION 2 1669#define INIT_HCA_VXLAN_OFFSET 0x0c 1670#define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e 1671#define INIT_HCA_FLAGS_OFFSET 0x014 1672#define INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET 0x018 1673#define INIT_HCA_QPC_OFFSET 0x020 1674#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) 1675#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17) 1676#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28) 1677#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f) 1678#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30) 1679#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37) 1680#define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38) 1681#define INIT_HCA_EQE_CQE_STRIDE_OFFSET (INIT_HCA_QPC_OFFSET + 0x3b) 1682#define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40) 1683#define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50) 1684#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60) 1685#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67) 1686#define INIT_HCA_NUM_SYS_EQS_OFFSET (INIT_HCA_QPC_OFFSET + 0x6a) 1687#define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70) 1688#define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77) 1689#define INIT_HCA_MCAST_OFFSET 0x0c0 1690#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00) 1691#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12) 1692#define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16) 1693#define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18) 1694#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b) 1695#define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6 1696#define INIT_HCA_FS_PARAM_OFFSET 0x1d0 1697#define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00) 1698#define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12) 1699#define INIT_HCA_FS_A0_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x18) 1700#define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b) 1701#define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21) 1702#define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22) 1703#define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25) 1704#define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26) 1705#define INIT_HCA_TPT_OFFSET 0x0f0 1706#define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00) 1707#define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08) 1708#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b) 1709#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10) 1710#define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18) 1711#define INIT_HCA_UAR_OFFSET 0x120 1712#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a) 1713#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b) 1714 1715 mailbox = mlx4_alloc_cmd_mailbox(dev); 1716 if (IS_ERR(mailbox)) 1717 return PTR_ERR(mailbox); 1718 inbox = mailbox->buf; 1719 1720 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION; 1721 1722 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) = 1723 (ilog2(cache_line_size()) - 4) << 5; 1724 1725#if defined(__LITTLE_ENDIAN) 1726 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1); 1727#elif defined(__BIG_ENDIAN) 1728 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1); 1729#else 1730#error Host endianness not defined 1731#endif 1732 /* Check port for UD address vector: */ 1733 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1); 1734 1735 /* Enable IPoIB checksumming if we can: */ 1736 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) 1737 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3); 1738 1739 /* Enable QoS support if module parameter set */ 1740 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG && enable_qos) 1741 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2); 1742 1743 /* enable counters */ 1744 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS) 1745 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4); 1746 1747 /* Enable RSS spread to fragmented IP packets when supported */ 1748 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_RSS_IP_FRAG) 1749 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 13); 1750 1751 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ 1752 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) { 1753 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29); 1754 dev->caps.eqe_size = 64; 1755 dev->caps.eqe_factor = 1; 1756 } else { 1757 dev->caps.eqe_size = 32; 1758 dev->caps.eqe_factor = 0; 1759 } 1760 1761 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) { 1762 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30); 1763 dev->caps.cqe_size = 64; 1764 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 1765 } else { 1766 dev->caps.cqe_size = 32; 1767 } 1768 1769 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */ 1770 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) && 1771 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) { 1772 dev->caps.eqe_size = cache_line_size(); 1773 dev->caps.cqe_size = cache_line_size(); 1774 dev->caps.eqe_factor = 0; 1775 MLX4_PUT(inbox, (u8)((ilog2(dev->caps.eqe_size) - 5) << 4 | 1776 (ilog2(dev->caps.eqe_size) - 5)), 1777 INIT_HCA_EQE_CQE_STRIDE_OFFSET); 1778 1779 /* User still need to know to support CQE > 32B */ 1780 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 1781 } 1782 1783 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT) 1784 *(inbox + INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET / 4) |= cpu_to_be32(1 << 31); 1785 1786 /* QPC/EEC/CQC/EQC/RDMARC attributes */ 1787 1788 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); 1789 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); 1790 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); 1791 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); 1792 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); 1793 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); 1794 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET); 1795 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET); 1796 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); 1797 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); 1798 MLX4_PUT(inbox, param->num_sys_eqs, INIT_HCA_NUM_SYS_EQS_OFFSET); 1799 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET); 1800 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET); 1801 1802 /* steering attributes */ 1803 if (dev->caps.steering_mode == 1804 MLX4_STEERING_MODE_DEVICE_MANAGED) { 1805 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= 1806 cpu_to_be32(1 << 1807 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN); 1808 1809 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET); 1810 MLX4_PUT(inbox, param->log_mc_entry_sz, 1811 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); 1812 MLX4_PUT(inbox, param->log_mc_table_sz, 1813 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); 1814 /* Enable Ethernet flow steering 1815 * with udp unicast and tcp unicast 1816 */ 1817 if (dev->caps.dmfs_high_steer_mode != 1818 MLX4_STEERING_DMFS_A0_STATIC) 1819 MLX4_PUT(inbox, 1820 (u8)(MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), 1821 INIT_HCA_FS_ETH_BITS_OFFSET); 1822 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, 1823 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET); 1824 /* Enable IPoIB flow steering 1825 * with udp unicast and tcp unicast 1826 */ 1827 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), 1828 INIT_HCA_FS_IB_BITS_OFFSET); 1829 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, 1830 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET); 1831 1832 if (dev->caps.dmfs_high_steer_mode != 1833 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 1834 MLX4_PUT(inbox, 1835 ((u8)(a0_dmfs_hw_steering[dev->caps.dmfs_high_steer_mode] 1836 << 6)), 1837 INIT_HCA_FS_A0_OFFSET); 1838 } else { 1839 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); 1840 MLX4_PUT(inbox, param->log_mc_entry_sz, 1841 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); 1842 MLX4_PUT(inbox, param->log_mc_hash_sz, 1843 INIT_HCA_LOG_MC_HASH_SZ_OFFSET); 1844 MLX4_PUT(inbox, param->log_mc_table_sz, 1845 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); 1846 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0) 1847 MLX4_PUT(inbox, (u8) (1 << 3), 1848 INIT_HCA_UC_STEERING_OFFSET); 1849 } 1850 1851 /* TPT attributes */ 1852 1853 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET); 1854 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET); 1855 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); 1856 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); 1857 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET); 1858 1859 /* UAR attributes */ 1860 1861 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET); 1862 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); 1863 1864 /* set parser VXLAN attributes */ 1865 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) { 1866 u8 parser_params = 0; 1867 MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET); 1868 } 1869 1870 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 1871 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE); 1872 1873 if (err) 1874 mlx4_err(dev, "INIT_HCA returns %d\n", err); 1875 1876 mlx4_free_cmd_mailbox(dev, mailbox); 1877 return err; 1878} 1879 1880int mlx4_QUERY_HCA(struct mlx4_dev *dev, 1881 struct mlx4_init_hca_param *param) 1882{ 1883 struct mlx4_cmd_mailbox *mailbox; 1884 __be32 *outbox; 1885 u32 dword_field; 1886 int err; 1887 u8 byte_field; 1888 static const u8 a0_dmfs_query_hw_steering[] = { 1889 [0] = MLX4_STEERING_DMFS_A0_DEFAULT, 1890 [1] = MLX4_STEERING_DMFS_A0_DYNAMIC, 1891 [2] = MLX4_STEERING_DMFS_A0_STATIC, 1892 [3] = MLX4_STEERING_DMFS_A0_DISABLE 1893 }; 1894 1895#define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04 1896#define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c 1897 1898 mailbox = mlx4_alloc_cmd_mailbox(dev); 1899 if (IS_ERR(mailbox)) 1900 return PTR_ERR(mailbox); 1901 outbox = mailbox->buf; 1902 1903 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 1904 MLX4_CMD_QUERY_HCA, 1905 MLX4_CMD_TIME_CLASS_B, 1906 !mlx4_is_slave(dev)); 1907 if (err) 1908 goto out; 1909 1910 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET); 1911 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); 1912 1913 /* QPC/EEC/CQC/EQC/RDMARC attributes */ 1914 1915 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET); 1916 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET); 1917 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET); 1918 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET); 1919 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET); 1920 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET); 1921 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET); 1922 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET); 1923 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET); 1924 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET); 1925 MLX4_GET(param->num_sys_eqs, outbox, INIT_HCA_NUM_SYS_EQS_OFFSET); 1926 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET); 1927 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET); 1928 1929 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET); 1930 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) { 1931 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; 1932 } else { 1933 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET); 1934 if (byte_field & 0x8) 1935 param->steering_mode = MLX4_STEERING_MODE_B0; 1936 else 1937 param->steering_mode = MLX4_STEERING_MODE_A0; 1938 } 1939 1940 if (dword_field & (1 << 13)) 1941 param->rss_ip_frags = 1; 1942 1943 /* steering attributes */ 1944 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { 1945 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET); 1946 MLX4_GET(param->log_mc_entry_sz, outbox, 1947 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); 1948 MLX4_GET(param->log_mc_table_sz, outbox, 1949 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); 1950 MLX4_GET(byte_field, outbox, 1951 INIT_HCA_FS_A0_OFFSET); 1952 param->dmfs_high_steer_mode = 1953 a0_dmfs_query_hw_steering[(byte_field >> 6) & 3]; 1954 } else { 1955 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET); 1956 MLX4_GET(param->log_mc_entry_sz, outbox, 1957 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); 1958 MLX4_GET(param->log_mc_hash_sz, outbox, 1959 INIT_HCA_LOG_MC_HASH_SZ_OFFSET); 1960 MLX4_GET(param->log_mc_table_sz, outbox, 1961 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); 1962 } 1963 1964 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ 1965 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS); 1966 if (byte_field & 0x20) /* 64-bytes eqe enabled */ 1967 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED; 1968 if (byte_field & 0x40) /* 64-bytes cqe enabled */ 1969 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED; 1970 1971 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */ 1972 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_STRIDE_OFFSET); 1973 if (byte_field) { 1974 param->dev_cap_enabled |= MLX4_DEV_CAP_EQE_STRIDE_ENABLED; 1975 param->dev_cap_enabled |= MLX4_DEV_CAP_CQE_STRIDE_ENABLED; 1976 param->cqe_size = 1 << ((byte_field & 1977 MLX4_CQE_SIZE_MASK_STRIDE) + 5); 1978 param->eqe_size = 1 << (((byte_field & 1979 MLX4_EQE_SIZE_MASK_STRIDE) >> 4) + 5); 1980 } 1981 1982 /* TPT attributes */ 1983 1984 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET); 1985 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET); 1986 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET); 1987 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET); 1988 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET); 1989 1990 /* UAR attributes */ 1991 1992 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET); 1993 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET); 1994 1995out: 1996 mlx4_free_cmd_mailbox(dev, mailbox); 1997 1998 return err; 1999} 2000 2001static int mlx4_hca_core_clock_update(struct mlx4_dev *dev) 2002{ 2003 struct mlx4_cmd_mailbox *mailbox; 2004 __be32 *outbox; 2005 int err; 2006 2007 mailbox = mlx4_alloc_cmd_mailbox(dev); 2008 if (IS_ERR(mailbox)) { 2009 mlx4_warn(dev, "hca_core_clock mailbox allocation failed\n"); 2010 return PTR_ERR(mailbox); 2011 } 2012 outbox = mailbox->buf; 2013 2014 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 2015 MLX4_CMD_QUERY_HCA, 2016 MLX4_CMD_TIME_CLASS_B, 2017 !mlx4_is_slave(dev)); 2018 if (err) { 2019 mlx4_warn(dev, "hca_core_clock update failed\n"); 2020 goto out; 2021 } 2022 2023 MLX4_GET(dev->caps.hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); 2024 2025out: 2026 mlx4_free_cmd_mailbox(dev, mailbox); 2027 2028 return err; 2029} 2030 2031/* for IB-type ports only in SRIOV mode. Checks that both proxy QP0 2032 * and real QP0 are active, so that the paravirtualized QP0 is ready 2033 * to operate */ 2034static int check_qp0_state(struct mlx4_dev *dev, int function, int port) 2035{ 2036 struct mlx4_priv *priv = mlx4_priv(dev); 2037 /* irrelevant if not infiniband */ 2038 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active && 2039 priv->mfunc.master.qp0_state[port].qp0_active) 2040 return 1; 2041 return 0; 2042} 2043 2044int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, 2045 struct mlx4_vhcr *vhcr, 2046 struct mlx4_cmd_mailbox *inbox, 2047 struct mlx4_cmd_mailbox *outbox, 2048 struct mlx4_cmd_info *cmd) 2049{ 2050 struct mlx4_priv *priv = mlx4_priv(dev); 2051 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier); 2052 int err; 2053 2054 if (port < 0) 2055 return -EINVAL; 2056 2057 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port)) 2058 return 0; 2059 2060 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { 2061 /* Enable port only if it was previously disabled */ 2062 if (!priv->mfunc.master.init_port_ref[port]) { 2063 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 2064 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2065 if (err) 2066 return err; 2067 } 2068 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 2069 } else { 2070 if (slave == mlx4_master_func_num(dev)) { 2071 if (check_qp0_state(dev, slave, port) && 2072 !priv->mfunc.master.qp0_state[port].port_active) { 2073 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 2074 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2075 if (err) 2076 return err; 2077 priv->mfunc.master.qp0_state[port].port_active = 1; 2078 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 2079 } 2080 } else 2081 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 2082 } 2083 ++priv->mfunc.master.init_port_ref[port]; 2084 return 0; 2085} 2086 2087int mlx4_INIT_PORT(struct mlx4_dev *dev, int port) 2088{ 2089 struct mlx4_cmd_mailbox *mailbox; 2090 u32 *inbox; 2091 int err; 2092 u32 flags; 2093 u16 field; 2094 2095 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 2096#define INIT_PORT_IN_SIZE 256 2097#define INIT_PORT_FLAGS_OFFSET 0x00 2098#define INIT_PORT_FLAG_SIG (1 << 18) 2099#define INIT_PORT_FLAG_NG (1 << 17) 2100#define INIT_PORT_FLAG_G0 (1 << 16) 2101#define INIT_PORT_VL_SHIFT 4 2102#define INIT_PORT_PORT_WIDTH_SHIFT 8 2103#define INIT_PORT_MTU_OFFSET 0x04 2104#define INIT_PORT_MAX_GID_OFFSET 0x06 2105#define INIT_PORT_MAX_PKEY_OFFSET 0x0a 2106#define INIT_PORT_GUID0_OFFSET 0x10 2107#define INIT_PORT_NODE_GUID_OFFSET 0x18 2108#define INIT_PORT_SI_GUID_OFFSET 0x20 2109 2110 mailbox = mlx4_alloc_cmd_mailbox(dev); 2111 if (IS_ERR(mailbox)) 2112 return PTR_ERR(mailbox); 2113 inbox = mailbox->buf; 2114 2115 flags = 0; 2116 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT; 2117 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT; 2118 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET); 2119 2120 field = 128 << dev->caps.ib_mtu_cap[port]; 2121 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET); 2122 field = dev->caps.gid_table_len[port]; 2123 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET); 2124 field = dev->caps.pkey_table_len[port]; 2125 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET); 2126 2127 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT, 2128 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2129 2130 mlx4_free_cmd_mailbox(dev, mailbox); 2131 } else 2132 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 2133 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 2134 2135 if (!err) 2136 mlx4_hca_core_clock_update(dev); 2137 2138 return err; 2139} 2140EXPORT_SYMBOL_GPL(mlx4_INIT_PORT); 2141 2142int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, 2143 struct mlx4_vhcr *vhcr, 2144 struct mlx4_cmd_mailbox *inbox, 2145 struct mlx4_cmd_mailbox *outbox, 2146 struct mlx4_cmd_info *cmd) 2147{ 2148 struct mlx4_priv *priv = mlx4_priv(dev); 2149 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier); 2150 int err; 2151 2152 if (port < 0) 2153 return -EINVAL; 2154 2155 if (!(priv->mfunc.master.slave_state[slave].init_port_mask & 2156 (1 << port))) 2157 return 0; 2158 2159 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { 2160 if (priv->mfunc.master.init_port_ref[port] == 1) { 2161 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 2162 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2163 if (err) 2164 return err; 2165 } 2166 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 2167 } else { 2168 /* infiniband port */ 2169 if (slave == mlx4_master_func_num(dev)) { 2170 if (!priv->mfunc.master.qp0_state[port].qp0_active && 2171 priv->mfunc.master.qp0_state[port].port_active) { 2172 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 2173 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2174 if (err) 2175 return err; 2176 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 2177 priv->mfunc.master.qp0_state[port].port_active = 0; 2178 } 2179 } else 2180 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 2181 } 2182 --priv->mfunc.master.init_port_ref[port]; 2183 return 0; 2184} 2185 2186int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port) 2187{ 2188 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 2189 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 2190} 2191EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT); 2192 2193int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic) 2194{ 2195 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 2196 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE); 2197} 2198 2199struct mlx4_config_dev { 2200 __be32 update_flags; 2201 __be32 rsvd1[3]; 2202 __be16 vxlan_udp_dport; 2203 __be16 rsvd2; 2204 __be32 rsvd3; 2205 __be32 roce_flags; 2206 __be32 rsvd4[25]; 2207 __be16 rsvd5; 2208 u8 rsvd6; 2209 u8 rx_checksum_val; 2210}; 2211 2212#define MLX4_VXLAN_UDP_DPORT (1 << 0) 2213#define MLX4_DISABLE_RX_PORT BIT(18) 2214 2215static int mlx4_CONFIG_DEV_set(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev) 2216{ 2217 int err; 2218 struct mlx4_cmd_mailbox *mailbox; 2219 2220 mailbox = mlx4_alloc_cmd_mailbox(dev); 2221 if (IS_ERR(mailbox)) 2222 return PTR_ERR(mailbox); 2223 2224 memcpy(mailbox->buf, config_dev, sizeof(*config_dev)); 2225 2226 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_CONFIG_DEV, 2227 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2228 2229 mlx4_free_cmd_mailbox(dev, mailbox); 2230 return err; 2231} 2232 2233static int mlx4_CONFIG_DEV_get(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev) 2234{ 2235 int err; 2236 struct mlx4_cmd_mailbox *mailbox; 2237 2238 mailbox = mlx4_alloc_cmd_mailbox(dev); 2239 if (IS_ERR(mailbox)) 2240 return PTR_ERR(mailbox); 2241 2242 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 1, MLX4_CMD_CONFIG_DEV, 2243 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2244 2245 if (!err) 2246 memcpy(config_dev, mailbox->buf, sizeof(*config_dev)); 2247 2248 mlx4_free_cmd_mailbox(dev, mailbox); 2249 return err; 2250} 2251 2252/* Conversion between the HW values and the actual functionality. 2253 * The value represented by the array index, 2254 * and the functionality determined by the flags. 2255 */ 2256static const u8 config_dev_csum_flags[] = { 2257 [0] = 0, 2258 [1] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP, 2259 [2] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP | 2260 MLX4_RX_CSUM_MODE_L4, 2261 [3] = MLX4_RX_CSUM_MODE_L4 | 2262 MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP | 2263 MLX4_RX_CSUM_MODE_MULTI_VLAN 2264}; 2265 2266int mlx4_config_dev_retrieval(struct mlx4_dev *dev, 2267 struct mlx4_config_dev_params *params) 2268{ 2269 struct mlx4_config_dev config_dev = {0}; 2270 int err; 2271 u8 csum_mask; 2272 2273#define CONFIG_DEV_RX_CSUM_MODE_MASK 0x7 2274#define CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET 0 2275#define CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET 4 2276 2277 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CONFIG_DEV)) 2278 return -ENOTSUPP; 2279 2280 err = mlx4_CONFIG_DEV_get(dev, &config_dev); 2281 if (err) 2282 return err; 2283 2284 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET) & 2285 CONFIG_DEV_RX_CSUM_MODE_MASK; 2286 2287 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0])) 2288 return -EINVAL; 2289 params->rx_csum_flags_port_1 = config_dev_csum_flags[csum_mask]; 2290 2291 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET) & 2292 CONFIG_DEV_RX_CSUM_MODE_MASK; 2293 2294 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0])) 2295 return -EINVAL; 2296 params->rx_csum_flags_port_2 = config_dev_csum_flags[csum_mask]; 2297 2298 params->vxlan_udp_dport = be16_to_cpu(config_dev.vxlan_udp_dport); 2299 2300 return 0; 2301} 2302EXPORT_SYMBOL_GPL(mlx4_config_dev_retrieval); 2303 2304int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port) 2305{ 2306 struct mlx4_config_dev config_dev; 2307 2308 memset(&config_dev, 0, sizeof(config_dev)); 2309 config_dev.update_flags = cpu_to_be32(MLX4_VXLAN_UDP_DPORT); 2310 config_dev.vxlan_udp_dport = udp_port; 2311 2312 return mlx4_CONFIG_DEV_set(dev, &config_dev); 2313} 2314EXPORT_SYMBOL_GPL(mlx4_config_vxlan_port); 2315 2316#define CONFIG_DISABLE_RX_PORT BIT(15) 2317int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis) 2318{ 2319 struct mlx4_config_dev config_dev; 2320 2321 memset(&config_dev, 0, sizeof(config_dev)); 2322 config_dev.update_flags = cpu_to_be32(MLX4_DISABLE_RX_PORT); 2323 if (dis) 2324 config_dev.roce_flags = 2325 cpu_to_be32(CONFIG_DISABLE_RX_PORT); 2326 2327 return mlx4_CONFIG_DEV_set(dev, &config_dev); 2328} 2329 2330int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2) 2331{ 2332 struct mlx4_cmd_mailbox *mailbox; 2333 struct { 2334 __be32 v_port1; 2335 __be32 v_port2; 2336 } *v2p; 2337 int err; 2338 2339 mailbox = mlx4_alloc_cmd_mailbox(dev); 2340 if (IS_ERR(mailbox)) 2341 return -ENOMEM; 2342 2343 v2p = mailbox->buf; 2344 v2p->v_port1 = cpu_to_be32(port1); 2345 v2p->v_port2 = cpu_to_be32(port2); 2346 2347 err = mlx4_cmd(dev, mailbox->dma, 0, 2348 MLX4_SET_PORT_VIRT2PHY, MLX4_CMD_VIRT_PORT_MAP, 2349 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2350 2351 mlx4_free_cmd_mailbox(dev, mailbox); 2352 return err; 2353} 2354 2355 2356int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages) 2357{ 2358 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0, 2359 MLX4_CMD_SET_ICM_SIZE, 2360 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2361 if (ret) 2362 return ret; 2363 2364 /* 2365 * Round up number of system pages needed in case 2366 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. 2367 */ 2368 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> 2369 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); 2370 2371 return 0; 2372} 2373 2374int mlx4_NOP(struct mlx4_dev *dev) 2375{ 2376 /* Input modifier of 0x1f means "finish as soon as possible." */ 2377 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, MLX4_CMD_TIME_CLASS_A, 2378 MLX4_CMD_NATIVE); 2379} 2380 2381int mlx4_get_phys_port_id(struct mlx4_dev *dev) 2382{ 2383 u8 port; 2384 u32 *outbox; 2385 struct mlx4_cmd_mailbox *mailbox; 2386 u32 in_mod; 2387 u32 guid_hi, guid_lo; 2388 int err, ret = 0; 2389#define MOD_STAT_CFG_PORT_OFFSET 8 2390#define MOD_STAT_CFG_GUID_H 0X14 2391#define MOD_STAT_CFG_GUID_L 0X1c 2392 2393 mailbox = mlx4_alloc_cmd_mailbox(dev); 2394 if (IS_ERR(mailbox)) 2395 return PTR_ERR(mailbox); 2396 outbox = mailbox->buf; 2397 2398 for (port = 1; port <= dev->caps.num_ports; port++) { 2399 in_mod = port << MOD_STAT_CFG_PORT_OFFSET; 2400 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_mod, 0x2, 2401 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, 2402 MLX4_CMD_NATIVE); 2403 if (err) { 2404 mlx4_err(dev, "Fail to get port %d uplink guid\n", 2405 port); 2406 ret = err; 2407 } else { 2408 MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H); 2409 MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L); 2410 dev->caps.phys_port_id[port] = (u64)guid_lo | 2411 (u64)guid_hi << 32; 2412 } 2413 } 2414 mlx4_free_cmd_mailbox(dev, mailbox); 2415 return ret; 2416} 2417 2418#define MLX4_WOL_SETUP_MODE (5 << 28) 2419int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port) 2420{ 2421 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; 2422 2423 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3, 2424 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, 2425 MLX4_CMD_NATIVE); 2426} 2427EXPORT_SYMBOL_GPL(mlx4_wol_read); 2428 2429int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port) 2430{ 2431 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; 2432 2433 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG, 2434 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2435} 2436EXPORT_SYMBOL_GPL(mlx4_wol_write); 2437 2438enum { 2439 ADD_TO_MCG = 0x26, 2440}; 2441 2442 2443void mlx4_opreq_action(struct work_struct *work) 2444{ 2445 struct mlx4_priv *priv = container_of(work, struct mlx4_priv, 2446 opreq_task); 2447 struct mlx4_dev *dev = &priv->dev; 2448 int num_tasks = atomic_read(&priv->opreq_count); 2449 struct mlx4_cmd_mailbox *mailbox; 2450 struct mlx4_mgm *mgm; 2451 u32 *outbox; 2452 u32 modifier; 2453 u16 token; 2454 u16 type; 2455 int err; 2456 u32 num_qps; 2457 struct mlx4_qp qp; 2458 int i; 2459 u8 rem_mcg; 2460 u8 prot; 2461 2462#define GET_OP_REQ_MODIFIER_OFFSET 0x08 2463#define GET_OP_REQ_TOKEN_OFFSET 0x14 2464#define GET_OP_REQ_TYPE_OFFSET 0x1a 2465#define GET_OP_REQ_DATA_OFFSET 0x20 2466 2467 mailbox = mlx4_alloc_cmd_mailbox(dev); 2468 if (IS_ERR(mailbox)) { 2469 mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n"); 2470 return; 2471 } 2472 outbox = mailbox->buf; 2473 2474 while (num_tasks) { 2475 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 2476 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A, 2477 MLX4_CMD_NATIVE); 2478 if (err) { 2479 mlx4_err(dev, "Failed to retrieve required operation: %d\n", 2480 err); 2481 return; 2482 } 2483 MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET); 2484 MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET); 2485 MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET); 2486 type &= 0xfff; 2487 2488 switch (type) { 2489 case ADD_TO_MCG: 2490 if (dev->caps.steering_mode == 2491 MLX4_STEERING_MODE_DEVICE_MANAGED) { 2492 mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n"); 2493 err = EPERM; 2494 break; 2495 } 2496 mgm = (struct mlx4_mgm *)((u8 *)(outbox) + 2497 GET_OP_REQ_DATA_OFFSET); 2498 num_qps = be32_to_cpu(mgm->members_count) & 2499 MGM_QPN_MASK; 2500 rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1; 2501 prot = ((u8 *)(&mgm->members_count))[0] >> 6; 2502 2503 for (i = 0; i < num_qps; i++) { 2504 qp.qpn = be32_to_cpu(mgm->qp[i]); 2505 if (rem_mcg) 2506 err = mlx4_multicast_detach(dev, &qp, 2507 mgm->gid, 2508 prot, 0); 2509 else 2510 err = mlx4_multicast_attach(dev, &qp, 2511 mgm->gid, 2512 mgm->gid[5] 2513 , 0, prot, 2514 NULL); 2515 if (err) 2516 break; 2517 } 2518 break; 2519 default: 2520 mlx4_warn(dev, "Bad type for required operation\n"); 2521 err = EINVAL; 2522 break; 2523 } 2524 err = mlx4_cmd(dev, 0, ((u32) err | 2525 (__force u32)cpu_to_be32(token) << 16), 2526 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A, 2527 MLX4_CMD_NATIVE); 2528 if (err) { 2529 mlx4_err(dev, "Failed to acknowledge required request: %d\n", 2530 err); 2531 goto out; 2532 } 2533 memset(outbox, 0, 0xffc); 2534 num_tasks = atomic_dec_return(&priv->opreq_count); 2535 } 2536 2537out: 2538 mlx4_free_cmd_mailbox(dev, mailbox); 2539} 2540 2541static int mlx4_check_smp_firewall_active(struct mlx4_dev *dev, 2542 struct mlx4_cmd_mailbox *mailbox) 2543{ 2544#define MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET 0x10 2545#define MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET 0x20 2546#define MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET 0x40 2547#define MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET 0x70 2548 2549 u32 set_attr_mask, getresp_attr_mask; 2550 u32 trap_attr_mask, traprepress_attr_mask; 2551 2552 MLX4_GET(set_attr_mask, mailbox->buf, 2553 MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET); 2554 mlx4_dbg(dev, "SMP firewall set_attribute_mask = 0x%x\n", 2555 set_attr_mask); 2556 2557 MLX4_GET(getresp_attr_mask, mailbox->buf, 2558 MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET); 2559 mlx4_dbg(dev, "SMP firewall getresp_attribute_mask = 0x%x\n", 2560 getresp_attr_mask); 2561 2562 MLX4_GET(trap_attr_mask, mailbox->buf, 2563 MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET); 2564 mlx4_dbg(dev, "SMP firewall trap_attribute_mask = 0x%x\n", 2565 trap_attr_mask); 2566 2567 MLX4_GET(traprepress_attr_mask, mailbox->buf, 2568 MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET); 2569 mlx4_dbg(dev, "SMP firewall traprepress_attribute_mask = 0x%x\n", 2570 traprepress_attr_mask); 2571 2572 if (set_attr_mask && getresp_attr_mask && trap_attr_mask && 2573 traprepress_attr_mask) 2574 return 1; 2575 2576 return 0; 2577} 2578 2579int mlx4_config_mad_demux(struct mlx4_dev *dev) 2580{ 2581 struct mlx4_cmd_mailbox *mailbox; 2582 int secure_host_active; 2583 int err; 2584 2585 /* Check if mad_demux is supported */ 2586 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX)) 2587 return 0; 2588 2589 mailbox = mlx4_alloc_cmd_mailbox(dev); 2590 if (IS_ERR(mailbox)) { 2591 mlx4_warn(dev, "Failed to allocate mailbox for cmd MAD_DEMUX"); 2592 return -ENOMEM; 2593 } 2594 2595 /* Query mad_demux to find out which MADs are handled by internal sma */ 2596 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0x01 /* subn mgmt class */, 2597 MLX4_CMD_MAD_DEMUX_QUERY_RESTR, MLX4_CMD_MAD_DEMUX, 2598 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2599 if (err) { 2600 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: query restrictions failed (%d)\n", 2601 err); 2602 goto out; 2603 } 2604 2605 secure_host_active = mlx4_check_smp_firewall_active(dev, mailbox); 2606 2607 /* Config mad_demux to handle all MADs returned by the query above */ 2608 err = mlx4_cmd(dev, mailbox->dma, 0x01 /* subn mgmt class */, 2609 MLX4_CMD_MAD_DEMUX_CONFIG, MLX4_CMD_MAD_DEMUX, 2610 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2611 if (err) { 2612 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: configure failed (%d)\n", err); 2613 goto out; 2614 } 2615 2616 if (secure_host_active) 2617 mlx4_warn(dev, "HCA operating in secure-host mode. SMP firewall activated.\n"); 2618out: 2619 mlx4_free_cmd_mailbox(dev, mailbox); 2620 return err; 2621} 2622 2623/* Access Reg commands */ 2624enum mlx4_access_reg_masks { 2625 MLX4_ACCESS_REG_STATUS_MASK = 0x7f, 2626 MLX4_ACCESS_REG_METHOD_MASK = 0x7f, 2627 MLX4_ACCESS_REG_LEN_MASK = 0x7ff 2628}; 2629 2630struct mlx4_access_reg { 2631 __be16 constant1; 2632 u8 status; 2633 u8 resrvd1; 2634 __be16 reg_id; 2635 u8 method; 2636 u8 constant2; 2637 __be32 resrvd2[2]; 2638 __be16 len_const; 2639 __be16 resrvd3; 2640#define MLX4_ACCESS_REG_HEADER_SIZE (20) 2641 u8 reg_data[MLX4_MAILBOX_SIZE-MLX4_ACCESS_REG_HEADER_SIZE]; 2642} __attribute__((__packed__)); 2643 2644/** 2645 * mlx4_ACCESS_REG - Generic access reg command. 2646 * @dev: mlx4_dev. 2647 * @reg_id: register ID to access. 2648 * @method: Access method Read/Write. 2649 * @reg_len: register length to Read/Write in bytes. 2650 * @reg_data: reg_data pointer to Read/Write From/To. 2651 * 2652 * Access ConnectX registers FW command. 2653 * Returns 0 on success and copies outbox mlx4_access_reg data 2654 * field into reg_data or a negative error code. 2655 */ 2656static int mlx4_ACCESS_REG(struct mlx4_dev *dev, u16 reg_id, 2657 enum mlx4_access_reg_method method, 2658 u16 reg_len, void *reg_data) 2659{ 2660 struct mlx4_cmd_mailbox *inbox, *outbox; 2661 struct mlx4_access_reg *inbuf, *outbuf; 2662 int err; 2663 2664 inbox = mlx4_alloc_cmd_mailbox(dev); 2665 if (IS_ERR(inbox)) 2666 return PTR_ERR(inbox); 2667 2668 outbox = mlx4_alloc_cmd_mailbox(dev); 2669 if (IS_ERR(outbox)) { 2670 mlx4_free_cmd_mailbox(dev, inbox); 2671 return PTR_ERR(outbox); 2672 } 2673 2674 inbuf = inbox->buf; 2675 outbuf = outbox->buf; 2676 2677 inbuf->constant1 = cpu_to_be16(0x1<<11 | 0x4); 2678 inbuf->constant2 = 0x1; 2679 inbuf->reg_id = cpu_to_be16(reg_id); 2680 inbuf->method = method & MLX4_ACCESS_REG_METHOD_MASK; 2681 2682 reg_len = min(reg_len, (u16)(sizeof(inbuf->reg_data))); 2683 inbuf->len_const = 2684 cpu_to_be16(((reg_len/4 + 1) & MLX4_ACCESS_REG_LEN_MASK) | 2685 ((0x3) << 12)); 2686 2687 memcpy(inbuf->reg_data, reg_data, reg_len); 2688 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, 0, 0, 2689 MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C, 2690 MLX4_CMD_WRAPPED); 2691 if (err) 2692 goto out; 2693 2694 if (outbuf->status & MLX4_ACCESS_REG_STATUS_MASK) { 2695 err = outbuf->status & MLX4_ACCESS_REG_STATUS_MASK; 2696 mlx4_err(dev, 2697 "MLX4_CMD_ACCESS_REG(%x) returned REG status (%x)\n", 2698 reg_id, err); 2699 goto out; 2700 } 2701 2702 memcpy(reg_data, outbuf->reg_data, reg_len); 2703out: 2704 mlx4_free_cmd_mailbox(dev, inbox); 2705 mlx4_free_cmd_mailbox(dev, outbox); 2706 return err; 2707} 2708 2709/* ConnectX registers IDs */ 2710enum mlx4_reg_id { 2711 MLX4_REG_ID_PTYS = 0x5004, 2712}; 2713 2714/** 2715 * mlx4_ACCESS_PTYS_REG - Access PTYs (Port Type and Speed) 2716 * register 2717 * @dev: mlx4_dev. 2718 * @method: Access method Read/Write. 2719 * @ptys_reg: PTYS register data pointer. 2720 * 2721 * Access ConnectX PTYS register, to Read/Write Port Type/Speed 2722 * configuration 2723 * Returns 0 on success or a negative error code. 2724 */ 2725int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev, 2726 enum mlx4_access_reg_method method, 2727 struct mlx4_ptys_reg *ptys_reg) 2728{ 2729 return mlx4_ACCESS_REG(dev, MLX4_REG_ID_PTYS, 2730 method, sizeof(*ptys_reg), ptys_reg); 2731} 2732EXPORT_SYMBOL_GPL(mlx4_ACCESS_PTYS_REG); 2733 2734int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave, 2735 struct mlx4_vhcr *vhcr, 2736 struct mlx4_cmd_mailbox *inbox, 2737 struct mlx4_cmd_mailbox *outbox, 2738 struct mlx4_cmd_info *cmd) 2739{ 2740 struct mlx4_access_reg *inbuf = inbox->buf; 2741 u8 method = inbuf->method & MLX4_ACCESS_REG_METHOD_MASK; 2742 u16 reg_id = be16_to_cpu(inbuf->reg_id); 2743 2744 if (slave != mlx4_master_func_num(dev) && 2745 method == MLX4_ACCESS_REG_WRITE) 2746 return -EPERM; 2747 2748 if (reg_id == MLX4_REG_ID_PTYS) { 2749 struct mlx4_ptys_reg *ptys_reg = 2750 (struct mlx4_ptys_reg *)inbuf->reg_data; 2751 2752 ptys_reg->local_port = 2753 mlx4_slave_convert_port(dev, slave, 2754 ptys_reg->local_port); 2755 } 2756 2757 return mlx4_cmd_box(dev, inbox->dma, outbox->dma, vhcr->in_modifier, 2758 0, MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C, 2759 MLX4_CMD_NATIVE); 2760} 2761