1/* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34#ifndef _MLX4_EN_H_ 35#define _MLX4_EN_H_ 36 37#include <linux/bitops.h> 38#include <linux/compiler.h> 39#include <linux/list.h> 40#include <linux/mutex.h> 41#include <linux/netdevice.h> 42#include <linux/if_vlan.h> 43#include <linux/net_tstamp.h> 44#ifdef CONFIG_MLX4_EN_DCB 45#include <linux/dcbnl.h> 46#endif 47#include <linux/cpu_rmap.h> 48#include <linux/ptp_clock_kernel.h> 49 50#include <linux/mlx4/device.h> 51#include <linux/mlx4/qp.h> 52#include <linux/mlx4/cq.h> 53#include <linux/mlx4/srq.h> 54#include <linux/mlx4/doorbell.h> 55#include <linux/mlx4/cmd.h> 56 57#include "en_port.h" 58#include "mlx4_stats.h" 59 60#define DRV_NAME "mlx4_en" 61#define DRV_VERSION "2.2-1" 62#define DRV_RELDATE "Feb 2014" 63 64#define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN) 65 66/* 67 * Device constants 68 */ 69 70 71#define MLX4_EN_PAGE_SHIFT 12 72#define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT) 73#define DEF_RX_RINGS 16 74#define MAX_RX_RINGS 128 75#define MIN_RX_RINGS 4 76#define TXBB_SIZE 64 77#define HEADROOM (2048 / TXBB_SIZE + 1) 78#define STAMP_STRIDE 64 79#define STAMP_DWORDS (STAMP_STRIDE / 4) 80#define STAMP_SHIFT 31 81#define STAMP_VAL 0x7fffffff 82#define STATS_DELAY (HZ / 4) 83#define SERVICE_TASK_DELAY (HZ / 4) 84#define MAX_NUM_OF_FS_RULES 256 85 86#define MLX4_EN_FILTER_HASH_SHIFT 4 87#define MLX4_EN_FILTER_EXPIRY_QUOTA 60 88 89/* Typical TSO descriptor with 16 gather entries is 352 bytes... */ 90#define MAX_DESC_SIZE 512 91#define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE) 92 93/* 94 * OS related constants and tunables 95 */ 96 97#define MLX4_EN_PRIV_FLAGS_BLUEFLAME 1 98 99#define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ) 100 101/* Use the maximum between 16384 and a single page */ 102#define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384) 103 104#define MLX4_EN_ALLOC_PREFER_ORDER PAGE_ALLOC_COSTLY_ORDER 105 106/* Receive fragment sizes; we use at most 3 fragments (for 9600 byte MTU 107 * and 4K allocations) */ 108enum { 109 FRAG_SZ0 = 1536 - NET_IP_ALIGN, 110 FRAG_SZ1 = 4096, 111 FRAG_SZ2 = 4096, 112 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE 113}; 114#define MLX4_EN_MAX_RX_FRAGS 4 115 116/* Maximum ring sizes */ 117#define MLX4_EN_MAX_TX_SIZE 8192 118#define MLX4_EN_MAX_RX_SIZE 8192 119 120/* Minimum ring size for our page-allocation scheme to work */ 121#define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES) 122#define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE) 123 124#define MLX4_EN_SMALL_PKT_SIZE 64 125#define MLX4_EN_MIN_TX_RING_P_UP 1 126#define MLX4_EN_MAX_TX_RING_P_UP 32 127#define MLX4_EN_NUM_UP 8 128#define MLX4_EN_DEF_TX_RING_SIZE 512 129#define MLX4_EN_DEF_RX_RING_SIZE 1024 130#define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \ 131 MLX4_EN_NUM_UP) 132 133#define MLX4_EN_DEFAULT_TX_WORK 256 134 135/* Target number of packets to coalesce with interrupt moderation */ 136#define MLX4_EN_RX_COAL_TARGET 44 137#define MLX4_EN_RX_COAL_TIME 0x10 138 139#define MLX4_EN_TX_COAL_PKTS 16 140#define MLX4_EN_TX_COAL_TIME 0x10 141 142#define MLX4_EN_RX_RATE_LOW 400000 143#define MLX4_EN_RX_COAL_TIME_LOW 0 144#define MLX4_EN_RX_RATE_HIGH 450000 145#define MLX4_EN_RX_COAL_TIME_HIGH 128 146#define MLX4_EN_RX_SIZE_THRESH 1024 147#define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH) 148#define MLX4_EN_SAMPLE_INTERVAL 0 149#define MLX4_EN_AVG_PKT_SMALL 256 150 151#define MLX4_EN_AUTO_CONF 0xffff 152 153#define MLX4_EN_DEF_RX_PAUSE 1 154#define MLX4_EN_DEF_TX_PAUSE 1 155 156/* Interval between successive polls in the Tx routine when polling is used 157 instead of interrupts (in per-core Tx rings) - should be power of 2 */ 158#define MLX4_EN_TX_POLL_MODER 16 159#define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4) 160 161#define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN) 162#define HEADER_COPY_SIZE (128 - NET_IP_ALIGN) 163#define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN) 164 165#define MLX4_EN_MIN_MTU 46 166#define ETH_BCAST 0xffffffffffffULL 167 168#define MLX4_EN_LOOPBACK_RETRIES 5 169#define MLX4_EN_LOOPBACK_TIMEOUT 100 170 171#ifdef MLX4_EN_PERF_STAT 172/* Number of samples to 'average' */ 173#define AVG_SIZE 128 174#define AVG_FACTOR 1024 175 176#define INC_PERF_COUNTER(cnt) (++(cnt)) 177#define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add)) 178#define AVG_PERF_COUNTER(cnt, sample) \ 179 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE) 180#define GET_PERF_COUNTER(cnt) (cnt) 181#define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR) 182 183#else 184 185#define INC_PERF_COUNTER(cnt) do {} while (0) 186#define ADD_PERF_COUNTER(cnt, add) do {} while (0) 187#define AVG_PERF_COUNTER(cnt, sample) do {} while (0) 188#define GET_PERF_COUNTER(cnt) (0) 189#define GET_AVG_PERF_COUNTER(cnt) (0) 190#endif /* MLX4_EN_PERF_STAT */ 191 192/* Constants for TX flow */ 193enum { 194 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */ 195 MAX_BF = 256, 196 MIN_PKT_LEN = 17, 197}; 198 199/* 200 * Configurables 201 */ 202 203enum cq_type { 204 RX = 0, 205 TX = 1, 206}; 207 208 209/* 210 * Useful macros 211 */ 212#define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x)) 213#define XNOR(x, y) (!(x) == !(y)) 214 215 216struct mlx4_en_tx_info { 217 struct sk_buff *skb; 218 dma_addr_t map0_dma; 219 u32 map0_byte_count; 220 u32 nr_txbb; 221 u32 nr_bytes; 222 u8 linear; 223 u8 data_offset; 224 u8 inl; 225 u8 ts_requested; 226 u8 nr_maps; 227} ____cacheline_aligned_in_smp; 228 229 230#define MLX4_EN_BIT_DESC_OWN 0x80000000 231#define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg) 232#define MLX4_EN_MEMTYPE_PAD 0x100 233#define DS_SIZE sizeof(struct mlx4_wqe_data_seg) 234 235 236struct mlx4_en_tx_desc { 237 struct mlx4_wqe_ctrl_seg ctrl; 238 union { 239 struct mlx4_wqe_data_seg data; /* at least one data segment */ 240 struct mlx4_wqe_lso_seg lso; 241 struct mlx4_wqe_inline_seg inl; 242 }; 243}; 244 245#define MLX4_EN_USE_SRQ 0x01000000 246 247#define MLX4_EN_CX3_LOW_ID 0x1000 248#define MLX4_EN_CX3_HIGH_ID 0x1005 249 250struct mlx4_en_rx_alloc { 251 struct page *page; 252 dma_addr_t dma; 253 u32 page_offset; 254 u32 page_size; 255}; 256 257struct mlx4_en_tx_ring { 258 /* cache line used and dirtied in tx completion 259 * (mlx4_en_free_tx_buf()) 260 */ 261 u32 last_nr_txbb; 262 u32 cons; 263 unsigned long wake_queue; 264 265 /* cache line used and dirtied in mlx4_en_xmit() */ 266 u32 prod ____cacheline_aligned_in_smp; 267 unsigned long bytes; 268 unsigned long packets; 269 unsigned long tx_csum; 270 unsigned long tso_packets; 271 unsigned long xmit_more; 272 struct mlx4_bf bf; 273 unsigned long queue_stopped; 274 275 /* Following part should be mostly read */ 276 cpumask_t affinity_mask; 277 struct mlx4_qp qp; 278 struct mlx4_hwq_resources wqres; 279 u32 size; /* number of TXBBs */ 280 u32 size_mask; 281 u16 stride; 282 u32 full_size; 283 u16 cqn; /* index of port CQ associated with this ring */ 284 u32 buf_size; 285 __be32 doorbell_qpn; 286 __be32 mr_key; 287 void *buf; 288 struct mlx4_en_tx_info *tx_info; 289 u8 *bounce_buf; 290 struct mlx4_qp_context context; 291 int qpn; 292 enum mlx4_qp_state qp_state; 293 u8 queue_index; 294 bool bf_enabled; 295 bool bf_alloced; 296 struct netdev_queue *tx_queue; 297 int hwtstamp_tx_type; 298} ____cacheline_aligned_in_smp; 299 300struct mlx4_en_rx_desc { 301 /* actual number of entries depends on rx ring stride */ 302 struct mlx4_wqe_data_seg data[0]; 303}; 304 305struct mlx4_en_rx_ring { 306 struct mlx4_hwq_resources wqres; 307 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS]; 308 u32 size ; /* number of Rx descs*/ 309 u32 actual_size; 310 u32 size_mask; 311 u16 stride; 312 u16 log_stride; 313 u16 cqn; /* index of port CQ associated with this ring */ 314 u32 prod; 315 u32 cons; 316 u32 buf_size; 317 u8 fcs_del; 318 void *buf; 319 void *rx_info; 320 unsigned long bytes; 321 unsigned long packets; 322#ifdef CONFIG_NET_RX_BUSY_POLL 323 unsigned long yields; 324 unsigned long misses; 325 unsigned long cleaned; 326#endif 327 unsigned long csum_ok; 328 unsigned long csum_none; 329 unsigned long csum_complete; 330 int hwtstamp_rx_filter; 331 cpumask_var_t affinity_mask; 332}; 333 334struct mlx4_en_cq { 335 struct mlx4_cq mcq; 336 struct mlx4_hwq_resources wqres; 337 int ring; 338 struct net_device *dev; 339 struct napi_struct napi; 340 int size; 341 int buf_size; 342 unsigned vector; 343 enum cq_type is_tx; 344 u16 moder_time; 345 u16 moder_cnt; 346 struct mlx4_cqe *buf; 347#define MLX4_EN_OPCODE_ERROR 0x1e 348 349#ifdef CONFIG_NET_RX_BUSY_POLL 350 unsigned int state; 351#define MLX4_EN_CQ_STATE_IDLE 0 352#define MLX4_EN_CQ_STATE_NAPI 1 /* NAPI owns this CQ */ 353#define MLX4_EN_CQ_STATE_POLL 2 /* poll owns this CQ */ 354#define MLX4_CQ_LOCKED (MLX4_EN_CQ_STATE_NAPI | MLX4_EN_CQ_STATE_POLL) 355#define MLX4_EN_CQ_STATE_NAPI_YIELD 4 /* NAPI yielded this CQ */ 356#define MLX4_EN_CQ_STATE_POLL_YIELD 8 /* poll yielded this CQ */ 357#define CQ_YIELD (MLX4_EN_CQ_STATE_NAPI_YIELD | MLX4_EN_CQ_STATE_POLL_YIELD) 358#define CQ_USER_PEND (MLX4_EN_CQ_STATE_POLL | MLX4_EN_CQ_STATE_POLL_YIELD) 359 spinlock_t poll_lock; /* protects from LLS/napi conflicts */ 360#endif /* CONFIG_NET_RX_BUSY_POLL */ 361 struct irq_desc *irq_desc; 362}; 363 364struct mlx4_en_port_profile { 365 u32 flags; 366 u32 tx_ring_num; 367 u32 rx_ring_num; 368 u32 tx_ring_size; 369 u32 rx_ring_size; 370 u8 rx_pause; 371 u8 rx_ppp; 372 u8 tx_pause; 373 u8 tx_ppp; 374 int rss_rings; 375 int inline_thold; 376}; 377 378struct mlx4_en_profile { 379 int udp_rss; 380 u8 rss_mask; 381 u32 active_ports; 382 u32 small_pkt_int; 383 u8 no_reset; 384 u8 num_tx_rings_p_up; 385 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1]; 386}; 387 388struct mlx4_en_dev { 389 struct mlx4_dev *dev; 390 struct pci_dev *pdev; 391 struct mutex state_lock; 392 struct net_device *pndev[MLX4_MAX_PORTS + 1]; 393 struct net_device *upper[MLX4_MAX_PORTS + 1]; 394 u32 port_cnt; 395 bool device_up; 396 struct mlx4_en_profile profile; 397 u32 LSO_support; 398 struct workqueue_struct *workqueue; 399 struct device *dma_device; 400 void __iomem *uar_map; 401 struct mlx4_uar priv_uar; 402 struct mlx4_mr mr; 403 u32 priv_pdn; 404 spinlock_t uar_lock; 405 u8 mac_removed[MLX4_MAX_PORTS + 1]; 406 rwlock_t clock_lock; 407 u32 nominal_c_mult; 408 struct cyclecounter cycles; 409 struct timecounter clock; 410 unsigned long last_overflow_check; 411 unsigned long overflow_period; 412 struct ptp_clock *ptp_clock; 413 struct ptp_clock_info ptp_clock_info; 414 struct notifier_block nb; 415}; 416 417 418struct mlx4_en_rss_map { 419 int base_qpn; 420 struct mlx4_qp qps[MAX_RX_RINGS]; 421 enum mlx4_qp_state state[MAX_RX_RINGS]; 422 struct mlx4_qp indir_qp; 423 enum mlx4_qp_state indir_state; 424}; 425 426enum mlx4_en_port_flag { 427 MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */ 428 MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */ 429}; 430 431struct mlx4_en_port_state { 432 int link_state; 433 int link_speed; 434 int transceiver; 435 u32 flags; 436}; 437 438enum mlx4_en_mclist_act { 439 MCLIST_NONE, 440 MCLIST_REM, 441 MCLIST_ADD, 442}; 443 444struct mlx4_en_mc_list { 445 struct list_head list; 446 enum mlx4_en_mclist_act action; 447 u8 addr[ETH_ALEN]; 448 u64 reg_id; 449 u64 tunnel_reg_id; 450}; 451 452struct mlx4_en_frag_info { 453 u16 frag_size; 454 u16 frag_prefix_size; 455 u16 frag_stride; 456}; 457 458#ifdef CONFIG_MLX4_EN_DCB 459/* Minimal TC BW - setting to 0 will block traffic */ 460#define MLX4_EN_BW_MIN 1 461#define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */ 462 463#define MLX4_EN_TC_ETS 7 464 465#endif 466 467struct ethtool_flow_id { 468 struct list_head list; 469 struct ethtool_rx_flow_spec flow_spec; 470 u64 id; 471}; 472 473enum { 474 MLX4_EN_FLAG_PROMISC = (1 << 0), 475 MLX4_EN_FLAG_MC_PROMISC = (1 << 1), 476 /* whether we need to enable hardware loopback by putting dmac 477 * in Tx WQE 478 */ 479 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2), 480 /* whether we need to drop packets that hardware loopback-ed */ 481 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3), 482 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4), 483 MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP = (1 << 5), 484}; 485 486#define PORT_BEACON_MAX_LIMIT (65535) 487#define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE) 488#define MLX4_EN_MAC_HASH_IDX 5 489 490struct mlx4_en_stats_bitmap { 491 DECLARE_BITMAP(bitmap, NUM_ALL_STATS); 492 struct mutex mutex; /* for mutual access to stats bitmap */ 493}; 494 495struct mlx4_en_priv { 496 struct mlx4_en_dev *mdev; 497 struct mlx4_en_port_profile *prof; 498 struct net_device *dev; 499 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 500 struct net_device_stats stats; 501 struct net_device_stats ret_stats; 502 struct mlx4_en_port_state port_state; 503 spinlock_t stats_lock; 504 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES]; 505 /* To allow rules removal while port is going down */ 506 struct list_head ethtool_list; 507 508 unsigned long last_moder_packets[MAX_RX_RINGS]; 509 unsigned long last_moder_tx_packets; 510 unsigned long last_moder_bytes[MAX_RX_RINGS]; 511 unsigned long last_moder_jiffies; 512 int last_moder_time[MAX_RX_RINGS]; 513 u16 rx_usecs; 514 u16 rx_frames; 515 u16 tx_usecs; 516 u16 tx_frames; 517 u32 pkt_rate_low; 518 u16 rx_usecs_low; 519 u32 pkt_rate_high; 520 u16 rx_usecs_high; 521 u16 sample_interval; 522 u16 adaptive_rx_coal; 523 u32 msg_enable; 524 u32 loopback_ok; 525 u32 validate_loopback; 526 527 struct mlx4_hwq_resources res; 528 int link_state; 529 int last_link_state; 530 bool port_up; 531 int port; 532 int registered; 533 int allocated; 534 int stride; 535 unsigned char current_mac[ETH_ALEN + 2]; 536 int mac_index; 537 unsigned max_mtu; 538 int base_qpn; 539 int cqe_factor; 540 int cqe_size; 541 542 struct mlx4_en_rss_map rss_map; 543 __be32 ctrl_flags; 544 u32 flags; 545 u8 num_tx_rings_p_up; 546 u32 tx_work_limit; 547 u32 tx_ring_num; 548 u32 rx_ring_num; 549 u32 rx_skb_size; 550 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS]; 551 u16 num_frags; 552 u16 log_rx_info; 553 554 struct mlx4_en_tx_ring **tx_ring; 555 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS]; 556 struct mlx4_en_cq **tx_cq; 557 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS]; 558 struct mlx4_qp drop_qp; 559 struct work_struct rx_mode_task; 560 struct work_struct watchdog_task; 561 struct work_struct linkstate_task; 562 struct delayed_work stats_task; 563 struct delayed_work service_task; 564#ifdef CONFIG_MLX4_EN_VXLAN 565 struct work_struct vxlan_add_task; 566 struct work_struct vxlan_del_task; 567#endif 568 struct mlx4_en_perf_stats pstats; 569 struct mlx4_en_pkt_stats pkstats; 570 struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES]; 571 struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES]; 572 struct mlx4_en_flow_stats_rx rx_flowstats; 573 struct mlx4_en_flow_stats_tx tx_flowstats; 574 struct mlx4_en_port_stats port_stats; 575 struct mlx4_en_stats_bitmap stats_bitmap; 576 struct list_head mc_list; 577 struct list_head curr_list; 578 u64 broadcast_id; 579 struct mlx4_en_stat_out_mbox hw_stats; 580 int vids[128]; 581 bool wol; 582 struct device *ddev; 583 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE]; 584 struct hwtstamp_config hwtstamp_config; 585 586#ifdef CONFIG_MLX4_EN_DCB 587 struct ieee_ets ets; 588 u16 maxrate[IEEE_8021QAZ_MAX_TCS]; 589 enum dcbnl_cndd_states cndd_state[IEEE_8021QAZ_MAX_TCS]; 590#endif 591#ifdef CONFIG_RFS_ACCEL 592 spinlock_t filters_lock; 593 int last_filter_id; 594 struct list_head filters; 595 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT]; 596#endif 597 u64 tunnel_reg_id; 598 __be16 vxlan_port; 599 600 u32 pflags; 601 u8 rss_key[MLX4_EN_RSS_KEY_SIZE]; 602 u8 rss_hash_fn; 603}; 604 605enum mlx4_en_wol { 606 MLX4_EN_WOL_MAGIC = (1ULL << 61), 607 MLX4_EN_WOL_ENABLED = (1ULL << 62), 608}; 609 610struct mlx4_mac_entry { 611 struct hlist_node hlist; 612 unsigned char mac[ETH_ALEN + 2]; 613 u64 reg_id; 614 struct rcu_head rcu; 615}; 616 617static inline struct mlx4_cqe *mlx4_en_get_cqe(void *buf, int idx, int cqe_sz) 618{ 619 return buf + idx * cqe_sz; 620} 621 622#ifdef CONFIG_NET_RX_BUSY_POLL 623static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq) 624{ 625 spin_lock_init(&cq->poll_lock); 626 cq->state = MLX4_EN_CQ_STATE_IDLE; 627} 628 629/* called from the device poll rutine to get ownership of a cq */ 630static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq) 631{ 632 int rc = true; 633 spin_lock(&cq->poll_lock); 634 if (cq->state & MLX4_CQ_LOCKED) { 635 WARN_ON(cq->state & MLX4_EN_CQ_STATE_NAPI); 636 cq->state |= MLX4_EN_CQ_STATE_NAPI_YIELD; 637 rc = false; 638 } else 639 /* we don't care if someone yielded */ 640 cq->state = MLX4_EN_CQ_STATE_NAPI; 641 spin_unlock(&cq->poll_lock); 642 return rc; 643} 644 645/* returns true is someone tried to get the cq while napi had it */ 646static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq) 647{ 648 int rc = false; 649 spin_lock(&cq->poll_lock); 650 WARN_ON(cq->state & (MLX4_EN_CQ_STATE_POLL | 651 MLX4_EN_CQ_STATE_NAPI_YIELD)); 652 653 if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD) 654 rc = true; 655 cq->state = MLX4_EN_CQ_STATE_IDLE; 656 spin_unlock(&cq->poll_lock); 657 return rc; 658} 659 660/* called from mlx4_en_low_latency_poll() */ 661static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq) 662{ 663 int rc = true; 664 spin_lock_bh(&cq->poll_lock); 665 if ((cq->state & MLX4_CQ_LOCKED)) { 666 struct net_device *dev = cq->dev; 667 struct mlx4_en_priv *priv = netdev_priv(dev); 668 struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring]; 669 670 cq->state |= MLX4_EN_CQ_STATE_POLL_YIELD; 671 rc = false; 672 rx_ring->yields++; 673 } else 674 /* preserve yield marks */ 675 cq->state |= MLX4_EN_CQ_STATE_POLL; 676 spin_unlock_bh(&cq->poll_lock); 677 return rc; 678} 679 680/* returns true if someone tried to get the cq while it was locked */ 681static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq) 682{ 683 int rc = false; 684 spin_lock_bh(&cq->poll_lock); 685 WARN_ON(cq->state & (MLX4_EN_CQ_STATE_NAPI)); 686 687 if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD) 688 rc = true; 689 cq->state = MLX4_EN_CQ_STATE_IDLE; 690 spin_unlock_bh(&cq->poll_lock); 691 return rc; 692} 693 694/* true if a socket is polling, even if it did not get the lock */ 695static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq) 696{ 697 WARN_ON(!(cq->state & MLX4_CQ_LOCKED)); 698 return cq->state & CQ_USER_PEND; 699} 700#else 701static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq) 702{ 703} 704 705static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq) 706{ 707 return true; 708} 709 710static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq) 711{ 712 return false; 713} 714 715static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq) 716{ 717 return false; 718} 719 720static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq) 721{ 722 return false; 723} 724 725static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq) 726{ 727 return false; 728} 729#endif /* CONFIG_NET_RX_BUSY_POLL */ 730 731#define MLX4_EN_WOL_DO_MODIFY (1ULL << 63) 732 733void mlx4_en_update_loopback_state(struct net_device *dev, 734 netdev_features_t features); 735 736void mlx4_en_destroy_netdev(struct net_device *dev); 737int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, 738 struct mlx4_en_port_profile *prof); 739 740int mlx4_en_start_port(struct net_device *dev); 741void mlx4_en_stop_port(struct net_device *dev, int detach); 742 743void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev, 744 struct mlx4_en_stats_bitmap *stats_bitmap, 745 u8 rx_ppp, u8 rx_pause, 746 u8 tx_ppp, u8 tx_pause); 747 748void mlx4_en_free_resources(struct mlx4_en_priv *priv); 749int mlx4_en_alloc_resources(struct mlx4_en_priv *priv); 750 751int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq, 752 int entries, int ring, enum cq_type mode, int node); 753void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq); 754int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq, 755 int cq_idx); 756void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 757int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 758int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 759 760void mlx4_en_tx_irq(struct mlx4_cq *mcq); 761u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, 762 void *accel_priv, select_queue_fallback_t fallback); 763netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev); 764 765int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 766 struct mlx4_en_tx_ring **pring, 767 u32 size, u16 stride, 768 int node, int queue_index); 769void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 770 struct mlx4_en_tx_ring **pring); 771int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 772 struct mlx4_en_tx_ring *ring, 773 int cq, int user_prio); 774void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 775 struct mlx4_en_tx_ring *ring); 776void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev); 777void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv); 778int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 779 struct mlx4_en_rx_ring **pring, 780 u32 size, u16 stride, int node); 781void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 782 struct mlx4_en_rx_ring **pring, 783 u32 size, u16 stride); 784int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv); 785void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, 786 struct mlx4_en_rx_ring *ring); 787int mlx4_en_process_rx_cq(struct net_device *dev, 788 struct mlx4_en_cq *cq, 789 int budget); 790int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget); 791int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget); 792void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, 793 int is_tx, int rss, int qpn, int cqn, int user_prio, 794 struct mlx4_qp_context *context); 795void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event); 796int mlx4_en_map_buffer(struct mlx4_buf *buf); 797void mlx4_en_unmap_buffer(struct mlx4_buf *buf); 798 799void mlx4_en_calc_rx_buf(struct net_device *dev); 800int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv); 801void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv); 802int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv); 803void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv); 804int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring); 805void mlx4_en_rx_irq(struct mlx4_cq *mcq); 806 807int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 808int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv); 809 810int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset); 811int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port); 812 813#ifdef CONFIG_MLX4_EN_DCB 814extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops; 815extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops; 816#endif 817 818int mlx4_en_setup_tc(struct net_device *dev, u8 up); 819 820#ifdef CONFIG_RFS_ACCEL 821void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv); 822#endif 823 824#define MLX4_EN_NUM_SELF_TEST 5 825void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf); 826void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev); 827 828#define DEV_FEATURE_CHANGED(dev, new_features, feature) \ 829 ((dev->features & feature) ^ (new_features & feature)) 830 831int mlx4_en_reset_config(struct net_device *dev, 832 struct hwtstamp_config ts_config, 833 netdev_features_t new_features); 834void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev, 835 struct mlx4_en_stats_bitmap *stats_bitmap, 836 u8 rx_ppp, u8 rx_pause, 837 u8 tx_ppp, u8 tx_pause); 838int mlx4_en_netdev_event(struct notifier_block *this, 839 unsigned long event, void *ptr); 840 841/* 842 * Functions for time stamping 843 */ 844u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe); 845void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev, 846 struct skb_shared_hwtstamps *hwts, 847 u64 timestamp); 848void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev); 849void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev); 850 851/* Globals 852 */ 853extern const struct ethtool_ops mlx4_en_ethtool_ops; 854 855 856 857/* 858 * printk / logging functions 859 */ 860 861__printf(3, 4) 862void en_print(const char *level, const struct mlx4_en_priv *priv, 863 const char *format, ...); 864 865#define en_dbg(mlevel, priv, format, ...) \ 866do { \ 867 if (NETIF_MSG_##mlevel & (priv)->msg_enable) \ 868 en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__); \ 869} while (0) 870#define en_warn(priv, format, ...) \ 871 en_print(KERN_WARNING, priv, format, ##__VA_ARGS__) 872#define en_err(priv, format, ...) \ 873 en_print(KERN_ERR, priv, format, ##__VA_ARGS__) 874#define en_info(priv, format, ...) \ 875 en_print(KERN_INFO, priv, format, ##__VA_ARGS__) 876 877#define mlx4_err(mdev, format, ...) \ 878 pr_err(DRV_NAME " %s: " format, \ 879 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 880#define mlx4_info(mdev, format, ...) \ 881 pr_info(DRV_NAME " %s: " format, \ 882 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 883#define mlx4_warn(mdev, format, ...) \ 884 pr_warn(DRV_NAME " %s: " format, \ 885 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 886 887#endif 888