1/**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2009-2013 Solarflare Communications Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published 7 * by the Free Software Foundation, incorporated herein by reference. 8 */ 9 10 11#ifndef MCDI_PCOL_H 12#define MCDI_PCOL_H 13 14/* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */ 15/* Power-on reset state */ 16#define MC_FW_STATE_POR (1) 17/* If this is set in MC_RESET_STATE_REG then it should be 18 * possible to jump into IMEM without loading code from flash. */ 19#define MC_FW_WARM_BOOT_OK (2) 20/* The MC main image has started to boot. */ 21#define MC_FW_STATE_BOOTING (4) 22/* The Scheduler has started. */ 23#define MC_FW_STATE_SCHED (8) 24/* If this is set in MC_RESET_STATE_REG then it should be 25 * possible to jump into IMEM without loading code from flash. 26 * Unlike a warm boot, assume DMEM has been reloaded, so that 27 * the MC persistent data must be reinitialised. */ 28#define MC_FW_TEPID_BOOT_OK (16) 29/* BIST state has been initialized */ 30#define MC_FW_BIST_INIT_OK (128) 31 32/* Siena MC shared memmory offsets */ 33/* The 'doorbell' addresses are hard-wired to alert the MC when written */ 34#define MC_SMEM_P0_DOORBELL_OFST 0x000 35#define MC_SMEM_P1_DOORBELL_OFST 0x004 36/* The rest of these are firmware-defined */ 37#define MC_SMEM_P0_PDU_OFST 0x008 38#define MC_SMEM_P1_PDU_OFST 0x108 39#define MC_SMEM_PDU_LEN 0x100 40#define MC_SMEM_P0_PTP_TIME_OFST 0x7f0 41#define MC_SMEM_P0_STATUS_OFST 0x7f8 42#define MC_SMEM_P1_STATUS_OFST 0x7fc 43 44/* Values to be written to the per-port status dword in shared 45 * memory on reboot and assert */ 46#define MC_STATUS_DWORD_REBOOT (0xb007b007) 47#define MC_STATUS_DWORD_ASSERT (0xdeaddead) 48 49/* Check whether an mcfw version (in host order) belongs to a bootloader */ 50#define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007) 51 52/* The current version of the MCDI protocol. 53 * 54 * Note that the ROM burnt into the card only talks V0, so at the very 55 * least every driver must support version 0 and MCDI_PCOL_VERSION 56 */ 57#define MCDI_PCOL_VERSION 2 58 59/* Unused commands: 0x23, 0x27, 0x30, 0x31 */ 60 61/* MCDI version 1 62 * 63 * Each MCDI request starts with an MCDI_HEADER, which is a 32bit 64 * structure, filled in by the client. 65 * 66 * 0 7 8 16 20 22 23 24 31 67 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS | 68 * | | | 69 * | | \--- Response 70 * | \------- Error 71 * \------------------------------ Resync (always set) 72 * 73 * The client writes it's request into MC shared memory, and rings the 74 * doorbell. Each request is completed by either by the MC writting 75 * back into shared memory, or by writting out an event. 76 * 77 * All MCDI commands support completion by shared memory response. Each 78 * request may also contain additional data (accounted for by HEADER.LEN), 79 * and some response's may also contain additional data (again, accounted 80 * for by HEADER.LEN). 81 * 82 * Some MCDI commands support completion by event, in which any associated 83 * response data is included in the event. 84 * 85 * The protocol requires one response to be delivered for every request, a 86 * request should not be sent unless the response for the previous request 87 * has been received (either by polling shared memory, or by receiving 88 * an event). 89 */ 90 91/** Request/Response structure */ 92#define MCDI_HEADER_OFST 0 93#define MCDI_HEADER_CODE_LBN 0 94#define MCDI_HEADER_CODE_WIDTH 7 95#define MCDI_HEADER_RESYNC_LBN 7 96#define MCDI_HEADER_RESYNC_WIDTH 1 97#define MCDI_HEADER_DATALEN_LBN 8 98#define MCDI_HEADER_DATALEN_WIDTH 8 99#define MCDI_HEADER_SEQ_LBN 16 100#define MCDI_HEADER_SEQ_WIDTH 4 101#define MCDI_HEADER_RSVD_LBN 20 102#define MCDI_HEADER_RSVD_WIDTH 1 103#define MCDI_HEADER_NOT_EPOCH_LBN 21 104#define MCDI_HEADER_NOT_EPOCH_WIDTH 1 105#define MCDI_HEADER_ERROR_LBN 22 106#define MCDI_HEADER_ERROR_WIDTH 1 107#define MCDI_HEADER_RESPONSE_LBN 23 108#define MCDI_HEADER_RESPONSE_WIDTH 1 109#define MCDI_HEADER_XFLAGS_LBN 24 110#define MCDI_HEADER_XFLAGS_WIDTH 8 111/* Request response using event */ 112#define MCDI_HEADER_XFLAGS_EVREQ 0x01 113 114/* Maximum number of payload bytes */ 115#define MCDI_CTL_SDU_LEN_MAX_V1 0xfc 116#define MCDI_CTL_SDU_LEN_MAX_V2 0x400 117 118#define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2 119 120 121/* The MC can generate events for two reasons: 122 * - To complete a shared memory request if XFLAGS_EVREQ was set 123 * - As a notification (link state, i2c event), controlled 124 * via MC_CMD_LOG_CTRL 125 * 126 * Both events share a common structure: 127 * 128 * 0 32 33 36 44 52 60 129 * | Data | Cont | Level | Src | Code | Rsvd | 130 * | 131 * \ There is another event pending in this notification 132 * 133 * If Code==CMDDONE, then the fields are further interpreted as: 134 * 135 * - LEVEL==INFO Command succeeded 136 * - LEVEL==ERR Command failed 137 * 138 * 0 8 16 24 32 139 * | Seq | Datalen | Errno | Rsvd | 140 * 141 * These fields are taken directly out of the standard MCDI header, i.e., 142 * LEVEL==ERR, Datalen == 0 => Reboot 143 * 144 * Events can be squirted out of the UART (using LOG_CTRL) without a 145 * MCDI header. An event can be distinguished from a MCDI response by 146 * examining the first byte which is 0xc0. This corresponds to the 147 * non-existent MCDI command MC_CMD_DEBUG_LOG. 148 * 149 * 0 7 8 150 * | command | Resync | = 0xc0 151 * 152 * Since the event is written in big-endian byte order, this works 153 * providing bits 56-63 of the event are 0xc0. 154 * 155 * 56 60 63 156 * | Rsvd | Code | = 0xc0 157 * 158 * Which means for convenience the event code is 0xc for all MC 159 * generated events. 160 */ 161#define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc 162 163 164/* Operation not permitted. */ 165#define MC_CMD_ERR_EPERM 1 166/* Non-existent command target */ 167#define MC_CMD_ERR_ENOENT 2 168/* assert() has killed the MC */ 169#define MC_CMD_ERR_EINTR 4 170/* I/O failure */ 171#define MC_CMD_ERR_EIO 5 172/* Try again */ 173#define MC_CMD_ERR_EAGAIN 11 174/* Out of memory */ 175#define MC_CMD_ERR_ENOMEM 12 176/* Caller does not hold required locks */ 177#define MC_CMD_ERR_EACCES 13 178/* Resource is currently unavailable (e.g. lock contention) */ 179#define MC_CMD_ERR_EBUSY 16 180/* No such device */ 181#define MC_CMD_ERR_ENODEV 19 182/* Invalid argument to target */ 183#define MC_CMD_ERR_EINVAL 22 184/* Out of range */ 185#define MC_CMD_ERR_ERANGE 34 186/* Non-recursive resource is already acquired */ 187#define MC_CMD_ERR_EDEADLK 35 188/* Operation not implemented */ 189#define MC_CMD_ERR_ENOSYS 38 190/* Operation timed out */ 191#define MC_CMD_ERR_ETIME 62 192/* Link has been severed */ 193#define MC_CMD_ERR_ENOLINK 67 194/* Protocol error */ 195#define MC_CMD_ERR_EPROTO 71 196/* Operation not supported */ 197#define MC_CMD_ERR_ENOTSUP 95 198/* Address not available */ 199#define MC_CMD_ERR_EADDRNOTAVAIL 99 200/* Not connected */ 201#define MC_CMD_ERR_ENOTCONN 107 202/* Operation already in progress */ 203#define MC_CMD_ERR_EALREADY 114 204 205/* Resource allocation failed. */ 206#define MC_CMD_ERR_ALLOC_FAIL 0x1000 207/* V-adaptor not found. */ 208#define MC_CMD_ERR_NO_VADAPTOR 0x1001 209/* EVB port not found. */ 210#define MC_CMD_ERR_NO_EVB_PORT 0x1002 211/* V-switch not found. */ 212#define MC_CMD_ERR_NO_VSWITCH 0x1003 213/* Too many VLAN tags. */ 214#define MC_CMD_ERR_VLAN_LIMIT 0x1004 215/* Bad PCI function number. */ 216#define MC_CMD_ERR_BAD_PCI_FUNC 0x1005 217/* Invalid VLAN mode. */ 218#define MC_CMD_ERR_BAD_VLAN_MODE 0x1006 219/* Invalid v-switch type. */ 220#define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007 221/* Invalid v-port type. */ 222#define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008 223/* MAC address exists. */ 224#define MC_CMD_ERR_MAC_EXIST 0x1009 225/* Slave core not present */ 226#define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a 227/* The datapath is disabled. */ 228#define MC_CMD_ERR_DATAPATH_DISABLED 0x100b 229 230#define MC_CMD_ERR_CODE_OFST 0 231 232/* We define 8 "escape" commands to allow 233 for command number space extension */ 234 235#define MC_CMD_CMD_SPACE_ESCAPE_0 0x78 236#define MC_CMD_CMD_SPACE_ESCAPE_1 0x79 237#define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A 238#define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B 239#define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C 240#define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D 241#define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E 242#define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F 243 244/* Vectors in the boot ROM */ 245/* Point to the copycode entry point. */ 246#define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4) 247#define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4) 248/* Points to the recovery mode entry point. */ 249#define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4) 250#define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4) 251 252/* The command set exported by the boot ROM (MCDI v0) */ 253#define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \ 254 (1 << MC_CMD_READ32) | \ 255 (1 << MC_CMD_WRITE32) | \ 256 (1 << MC_CMD_COPYCODE) | \ 257 (1 << MC_CMD_GET_VERSION), \ 258 0, 0, 0 } 259 260#define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \ 261 (MC_CMD_SENSOR_ENTRY_OFST + (_x)) 262 263#define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \ 264 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 265 MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST + \ 266 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 267 268#define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \ 269 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 270 MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST + \ 271 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 272 273#define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \ 274 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 275 MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST + \ 276 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 277 278 279/* Version 2 adds an optional argument to error returns: the errno value 280 * may be followed by the (0-based) number of the first argument that 281 * could not be processed. 282 */ 283#define MC_CMD_ERR_ARG_OFST 4 284 285/* No space */ 286#define MC_CMD_ERR_ENOSPC 28 287 288/* MCDI_EVENT structuredef */ 289#define MCDI_EVENT_LEN 8 290#define MCDI_EVENT_CONT_LBN 32 291#define MCDI_EVENT_CONT_WIDTH 1 292#define MCDI_EVENT_LEVEL_LBN 33 293#define MCDI_EVENT_LEVEL_WIDTH 3 294/* enum: Info. */ 295#define MCDI_EVENT_LEVEL_INFO 0x0 296/* enum: Warning. */ 297#define MCDI_EVENT_LEVEL_WARN 0x1 298/* enum: Error. */ 299#define MCDI_EVENT_LEVEL_ERR 0x2 300/* enum: Fatal. */ 301#define MCDI_EVENT_LEVEL_FATAL 0x3 302#define MCDI_EVENT_DATA_OFST 0 303#define MCDI_EVENT_CMDDONE_SEQ_LBN 0 304#define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8 305#define MCDI_EVENT_CMDDONE_DATALEN_LBN 8 306#define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8 307#define MCDI_EVENT_CMDDONE_ERRNO_LBN 16 308#define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8 309#define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0 310#define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16 311#define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16 312#define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4 313/* enum: 100Mbs */ 314#define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1 315/* enum: 1Gbs */ 316#define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2 317/* enum: 10Gbs */ 318#define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3 319/* enum: 40Gbs */ 320#define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4 321#define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20 322#define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4 323#define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24 324#define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8 325#define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0 326#define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8 327#define MCDI_EVENT_SENSOREVT_STATE_LBN 8 328#define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8 329#define MCDI_EVENT_SENSOREVT_VALUE_LBN 16 330#define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16 331#define MCDI_EVENT_FWALERT_DATA_LBN 8 332#define MCDI_EVENT_FWALERT_DATA_WIDTH 24 333#define MCDI_EVENT_FWALERT_REASON_LBN 0 334#define MCDI_EVENT_FWALERT_REASON_WIDTH 8 335/* enum: SRAM Access. */ 336#define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1 337#define MCDI_EVENT_FLR_VF_LBN 0 338#define MCDI_EVENT_FLR_VF_WIDTH 8 339#define MCDI_EVENT_TX_ERR_TXQ_LBN 0 340#define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12 341#define MCDI_EVENT_TX_ERR_TYPE_LBN 12 342#define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4 343/* enum: Descriptor loader reported failure */ 344#define MCDI_EVENT_TX_ERR_DL_FAIL 0x1 345/* enum: Descriptor ring empty and no EOP seen for packet */ 346#define MCDI_EVENT_TX_ERR_NO_EOP 0x2 347/* enum: Overlength packet */ 348#define MCDI_EVENT_TX_ERR_2BIG 0x3 349/* enum: Malformed option descriptor */ 350#define MCDI_EVENT_TX_BAD_OPTDESC 0x5 351/* enum: Option descriptor part way through a packet */ 352#define MCDI_EVENT_TX_OPT_IN_PKT 0x8 353/* enum: DMA or PIO data access error */ 354#define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9 355#define MCDI_EVENT_TX_ERR_INFO_LBN 16 356#define MCDI_EVENT_TX_ERR_INFO_WIDTH 16 357#define MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12 358#define MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1 359#define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0 360#define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12 361#define MCDI_EVENT_PTP_ERR_TYPE_LBN 0 362#define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8 363/* enum: PLL lost lock */ 364#define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1 365/* enum: Filter overflow (PDMA) */ 366#define MCDI_EVENT_PTP_ERR_FILTER 0x2 367/* enum: FIFO overflow (FPGA) */ 368#define MCDI_EVENT_PTP_ERR_FIFO 0x3 369/* enum: Merge queue overflow */ 370#define MCDI_EVENT_PTP_ERR_QUEUE 0x4 371#define MCDI_EVENT_AOE_ERR_TYPE_LBN 0 372#define MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8 373/* enum: AOE failed to load - no valid image? */ 374#define MCDI_EVENT_AOE_NO_LOAD 0x1 375/* enum: AOE FC reported an exception */ 376#define MCDI_EVENT_AOE_FC_ASSERT 0x2 377/* enum: AOE FC watchdogged */ 378#define MCDI_EVENT_AOE_FC_WATCHDOG 0x3 379/* enum: AOE FC failed to start */ 380#define MCDI_EVENT_AOE_FC_NO_START 0x4 381/* enum: Generic AOE fault - likely to have been reported via other means too 382 * but intended for use by aoex driver. 383 */ 384#define MCDI_EVENT_AOE_FAULT 0x5 385/* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */ 386#define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6 387/* enum: AOE loaded successfully */ 388#define MCDI_EVENT_AOE_LOAD 0x7 389/* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */ 390#define MCDI_EVENT_AOE_DMA 0x8 391/* enum: AOE byteblaster connected/disconnected (Connection status in 392 * AOE_ERR_DATA) 393 */ 394#define MCDI_EVENT_AOE_BYTEBLASTER 0x9 395/* enum: DDR ECC status update */ 396#define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa 397#define MCDI_EVENT_AOE_ERR_DATA_LBN 8 398#define MCDI_EVENT_AOE_ERR_DATA_WIDTH 8 399#define MCDI_EVENT_RX_ERR_RXQ_LBN 0 400#define MCDI_EVENT_RX_ERR_RXQ_WIDTH 12 401#define MCDI_EVENT_RX_ERR_TYPE_LBN 12 402#define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4 403#define MCDI_EVENT_RX_ERR_INFO_LBN 16 404#define MCDI_EVENT_RX_ERR_INFO_WIDTH 16 405#define MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12 406#define MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1 407#define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0 408#define MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12 409#define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0 410#define MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16 411#define MCDI_EVENT_DATA_LBN 0 412#define MCDI_EVENT_DATA_WIDTH 32 413#define MCDI_EVENT_SRC_LBN 36 414#define MCDI_EVENT_SRC_WIDTH 8 415#define MCDI_EVENT_EV_CODE_LBN 60 416#define MCDI_EVENT_EV_CODE_WIDTH 4 417#define MCDI_EVENT_CODE_LBN 44 418#define MCDI_EVENT_CODE_WIDTH 8 419/* enum: Bad assert. */ 420#define MCDI_EVENT_CODE_BADSSERT 0x1 421/* enum: PM Notice. */ 422#define MCDI_EVENT_CODE_PMNOTICE 0x2 423/* enum: Command done. */ 424#define MCDI_EVENT_CODE_CMDDONE 0x3 425/* enum: Link change. */ 426#define MCDI_EVENT_CODE_LINKCHANGE 0x4 427/* enum: Sensor Event. */ 428#define MCDI_EVENT_CODE_SENSOREVT 0x5 429/* enum: Schedule error. */ 430#define MCDI_EVENT_CODE_SCHEDERR 0x6 431/* enum: Reboot. */ 432#define MCDI_EVENT_CODE_REBOOT 0x7 433/* enum: Mac stats DMA. */ 434#define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8 435/* enum: Firmware alert. */ 436#define MCDI_EVENT_CODE_FWALERT 0x9 437/* enum: Function level reset. */ 438#define MCDI_EVENT_CODE_FLR 0xa 439/* enum: Transmit error */ 440#define MCDI_EVENT_CODE_TX_ERR 0xb 441/* enum: Tx flush has completed */ 442#define MCDI_EVENT_CODE_TX_FLUSH 0xc 443/* enum: PTP packet received timestamp */ 444#define MCDI_EVENT_CODE_PTP_RX 0xd 445/* enum: PTP NIC failure */ 446#define MCDI_EVENT_CODE_PTP_FAULT 0xe 447/* enum: PTP PPS event */ 448#define MCDI_EVENT_CODE_PTP_PPS 0xf 449/* enum: Rx flush has completed */ 450#define MCDI_EVENT_CODE_RX_FLUSH 0x10 451/* enum: Receive error */ 452#define MCDI_EVENT_CODE_RX_ERR 0x11 453/* enum: AOE fault */ 454#define MCDI_EVENT_CODE_AOE 0x12 455/* enum: Network port calibration failed (VCAL). */ 456#define MCDI_EVENT_CODE_VCAL_FAIL 0x13 457/* enum: HW PPS event */ 458#define MCDI_EVENT_CODE_HW_PPS 0x14 459/* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and 460 * a different format) 461 */ 462#define MCDI_EVENT_CODE_MC_REBOOT 0x15 463/* enum: the MC has detected a parity error */ 464#define MCDI_EVENT_CODE_PAR_ERR 0x16 465/* enum: the MC has detected a correctable error */ 466#define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17 467/* enum: the MC has detected an uncorrectable error */ 468#define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18 469/* enum: The MC has entered offline BIST mode */ 470#define MCDI_EVENT_CODE_MC_BIST 0x19 471/* enum: PTP tick event providing current NIC time */ 472#define MCDI_EVENT_CODE_PTP_TIME 0x1a 473/* enum: Artificial event generated by host and posted via MC for test 474 * purposes. 475 */ 476#define MCDI_EVENT_CODE_TESTGEN 0xfa 477#define MCDI_EVENT_CMDDONE_DATA_OFST 0 478#define MCDI_EVENT_CMDDONE_DATA_LBN 0 479#define MCDI_EVENT_CMDDONE_DATA_WIDTH 32 480#define MCDI_EVENT_LINKCHANGE_DATA_OFST 0 481#define MCDI_EVENT_LINKCHANGE_DATA_LBN 0 482#define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32 483#define MCDI_EVENT_SENSOREVT_DATA_OFST 0 484#define MCDI_EVENT_SENSOREVT_DATA_LBN 0 485#define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32 486#define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0 487#define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0 488#define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32 489#define MCDI_EVENT_TX_ERR_DATA_OFST 0 490#define MCDI_EVENT_TX_ERR_DATA_LBN 0 491#define MCDI_EVENT_TX_ERR_DATA_WIDTH 32 492/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of 493 * timestamp 494 */ 495#define MCDI_EVENT_PTP_SECONDS_OFST 0 496#define MCDI_EVENT_PTP_SECONDS_LBN 0 497#define MCDI_EVENT_PTP_SECONDS_WIDTH 32 498/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of 499 * timestamp 500 */ 501#define MCDI_EVENT_PTP_MAJOR_OFST 0 502#define MCDI_EVENT_PTP_MAJOR_LBN 0 503#define MCDI_EVENT_PTP_MAJOR_WIDTH 32 504/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field 505 * of timestamp 506 */ 507#define MCDI_EVENT_PTP_NANOSECONDS_OFST 0 508#define MCDI_EVENT_PTP_NANOSECONDS_LBN 0 509#define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32 510/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of 511 * timestamp 512 */ 513#define MCDI_EVENT_PTP_MINOR_OFST 0 514#define MCDI_EVENT_PTP_MINOR_LBN 0 515#define MCDI_EVENT_PTP_MINOR_WIDTH 32 516/* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet 517 */ 518#define MCDI_EVENT_PTP_UUID_OFST 0 519#define MCDI_EVENT_PTP_UUID_LBN 0 520#define MCDI_EVENT_PTP_UUID_WIDTH 32 521#define MCDI_EVENT_RX_ERR_DATA_OFST 0 522#define MCDI_EVENT_RX_ERR_DATA_LBN 0 523#define MCDI_EVENT_RX_ERR_DATA_WIDTH 32 524#define MCDI_EVENT_PAR_ERR_DATA_OFST 0 525#define MCDI_EVENT_PAR_ERR_DATA_LBN 0 526#define MCDI_EVENT_PAR_ERR_DATA_WIDTH 32 527#define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0 528#define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0 529#define MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32 530#define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0 531#define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0 532#define MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32 533/* For CODE_PTP_TIME events, the major value of the PTP clock */ 534#define MCDI_EVENT_PTP_TIME_MAJOR_OFST 0 535#define MCDI_EVENT_PTP_TIME_MAJOR_LBN 0 536#define MCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32 537/* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */ 538#define MCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36 539#define MCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8 540 541/* FCDI_EVENT structuredef */ 542#define FCDI_EVENT_LEN 8 543#define FCDI_EVENT_CONT_LBN 32 544#define FCDI_EVENT_CONT_WIDTH 1 545#define FCDI_EVENT_LEVEL_LBN 33 546#define FCDI_EVENT_LEVEL_WIDTH 3 547/* enum: Info. */ 548#define FCDI_EVENT_LEVEL_INFO 0x0 549/* enum: Warning. */ 550#define FCDI_EVENT_LEVEL_WARN 0x1 551/* enum: Error. */ 552#define FCDI_EVENT_LEVEL_ERR 0x2 553/* enum: Fatal. */ 554#define FCDI_EVENT_LEVEL_FATAL 0x3 555#define FCDI_EVENT_DATA_OFST 0 556#define FCDI_EVENT_LINK_STATE_STATUS_LBN 0 557#define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1 558#define FCDI_EVENT_LINK_DOWN 0x0 /* enum */ 559#define FCDI_EVENT_LINK_UP 0x1 /* enum */ 560#define FCDI_EVENT_DATA_LBN 0 561#define FCDI_EVENT_DATA_WIDTH 32 562#define FCDI_EVENT_SRC_LBN 36 563#define FCDI_EVENT_SRC_WIDTH 8 564#define FCDI_EVENT_EV_CODE_LBN 60 565#define FCDI_EVENT_EV_CODE_WIDTH 4 566#define FCDI_EVENT_CODE_LBN 44 567#define FCDI_EVENT_CODE_WIDTH 8 568/* enum: The FC was rebooted. */ 569#define FCDI_EVENT_CODE_REBOOT 0x1 570/* enum: Bad assert. */ 571#define FCDI_EVENT_CODE_ASSERT 0x2 572/* enum: DDR3 test result. */ 573#define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3 574/* enum: Link status. */ 575#define FCDI_EVENT_CODE_LINK_STATE 0x4 576/* enum: A timed read is ready to be serviced. */ 577#define FCDI_EVENT_CODE_TIMED_READ 0x5 578/* enum: One or more PPS IN events */ 579#define FCDI_EVENT_CODE_PPS_IN 0x6 580/* enum: Tick event from PTP clock */ 581#define FCDI_EVENT_CODE_PTP_TICK 0x7 582/* enum: ECC error counters */ 583#define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8 584#define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0 585#define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0 586#define FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32 587#define FCDI_EVENT_ASSERT_TYPE_LBN 36 588#define FCDI_EVENT_ASSERT_TYPE_WIDTH 8 589#define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36 590#define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8 591#define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0 592#define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0 593#define FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32 594#define FCDI_EVENT_LINK_STATE_DATA_OFST 0 595#define FCDI_EVENT_LINK_STATE_DATA_LBN 0 596#define FCDI_EVENT_LINK_STATE_DATA_WIDTH 32 597#define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 36 598#define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 8 599#define FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0 600#define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0 601#define FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32 602 603/* FCDI_EXTENDED_EVENT_PPS structuredef: Extended FCDI event to send PPS events 604 * to the MC. Note that this structure | is overlayed over a normal FCDI event 605 * such that bits 32-63 containing | event code, level, source etc remain the 606 * same. In this case the data | field of the header is defined to be the 607 * number of timestamps 608 */ 609#define FCDI_EXTENDED_EVENT_PPS_LENMIN 16 610#define FCDI_EXTENDED_EVENT_PPS_LENMAX 248 611#define FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num)) 612/* Number of timestamps following */ 613#define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0 614#define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0 615#define FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32 616/* Seconds field of a timestamp record */ 617#define FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8 618#define FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64 619#define FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32 620/* Nanoseconds field of a timestamp record */ 621#define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12 622#define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96 623#define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32 624/* Timestamp records comprising the event */ 625#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8 626#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8 627#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8 628#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12 629#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1 630#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30 631#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64 632#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64 633 634 635/***********************************/ 636/* MC_CMD_READ32 637 * Read multiple 32byte words from MC memory. 638 */ 639#define MC_CMD_READ32 0x1 640 641/* MC_CMD_READ32_IN msgrequest */ 642#define MC_CMD_READ32_IN_LEN 8 643#define MC_CMD_READ32_IN_ADDR_OFST 0 644#define MC_CMD_READ32_IN_NUMWORDS_OFST 4 645 646/* MC_CMD_READ32_OUT msgresponse */ 647#define MC_CMD_READ32_OUT_LENMIN 4 648#define MC_CMD_READ32_OUT_LENMAX 252 649#define MC_CMD_READ32_OUT_LEN(num) (0+4*(num)) 650#define MC_CMD_READ32_OUT_BUFFER_OFST 0 651#define MC_CMD_READ32_OUT_BUFFER_LEN 4 652#define MC_CMD_READ32_OUT_BUFFER_MINNUM 1 653#define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63 654 655 656/***********************************/ 657/* MC_CMD_WRITE32 658 * Write multiple 32byte words to MC memory. 659 */ 660#define MC_CMD_WRITE32 0x2 661 662/* MC_CMD_WRITE32_IN msgrequest */ 663#define MC_CMD_WRITE32_IN_LENMIN 8 664#define MC_CMD_WRITE32_IN_LENMAX 252 665#define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num)) 666#define MC_CMD_WRITE32_IN_ADDR_OFST 0 667#define MC_CMD_WRITE32_IN_BUFFER_OFST 4 668#define MC_CMD_WRITE32_IN_BUFFER_LEN 4 669#define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1 670#define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62 671 672/* MC_CMD_WRITE32_OUT msgresponse */ 673#define MC_CMD_WRITE32_OUT_LEN 0 674 675 676/***********************************/ 677/* MC_CMD_COPYCODE 678 * Copy MC code between two locations and jump. 679 */ 680#define MC_CMD_COPYCODE 0x3 681 682/* MC_CMD_COPYCODE_IN msgrequest */ 683#define MC_CMD_COPYCODE_IN_LEN 16 684/* Source address */ 685#define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0 686/* enum: The main image should be entered via a copy of a single word from and 687 * to this address when none of the other magic behaviours are required. 688 */ 689#define MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000 690/* enum: Entering the main image via a copy of a single word from and to this 691 * address indicates that it should not attempt to start the datapath CPUs. 692 * This is useful for certain soft rebooting scenarios. (Huntington only) 693 */ 694#define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0 695/* enum: Entering the main image via a copy of a single word from and to this 696 * address indicates that it should not attempt to parse any configuration from 697 * flash. (In addition, the datapath CPUs will not be started, as for 698 * MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR above.) This is useful for 699 * certain soft rebooting scenarios. (Huntington only) 700 */ 701#define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc 702/* Destination address */ 703#define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4 704#define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8 705/* Address of where to jump after copy. */ 706#define MC_CMD_COPYCODE_IN_JUMP_OFST 12 707/* enum: Control should return to the caller rather than jumping */ 708#define MC_CMD_COPYCODE_JUMP_NONE 0x1 709 710/* MC_CMD_COPYCODE_OUT msgresponse */ 711#define MC_CMD_COPYCODE_OUT_LEN 0 712 713 714/***********************************/ 715/* MC_CMD_SET_FUNC 716 * Select function for function-specific commands. 717 */ 718#define MC_CMD_SET_FUNC 0x4 719 720/* MC_CMD_SET_FUNC_IN msgrequest */ 721#define MC_CMD_SET_FUNC_IN_LEN 4 722/* Set function */ 723#define MC_CMD_SET_FUNC_IN_FUNC_OFST 0 724 725/* MC_CMD_SET_FUNC_OUT msgresponse */ 726#define MC_CMD_SET_FUNC_OUT_LEN 0 727 728 729/***********************************/ 730/* MC_CMD_GET_BOOT_STATUS 731 * Get the instruction address from which the MC booted. 732 */ 733#define MC_CMD_GET_BOOT_STATUS 0x5 734 735/* MC_CMD_GET_BOOT_STATUS_IN msgrequest */ 736#define MC_CMD_GET_BOOT_STATUS_IN_LEN 0 737 738/* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */ 739#define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8 740/* ?? */ 741#define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0 742/* enum: indicates that the MC wasn't flash booted */ 743#define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef 744#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4 745#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0 746#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1 747#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1 748#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1 749#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2 750#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1 751 752 753/***********************************/ 754/* MC_CMD_GET_ASSERTS 755 * Get (and optionally clear) the current assertion status. Only 756 * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other 757 * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS 758 */ 759#define MC_CMD_GET_ASSERTS 0x6 760 761/* MC_CMD_GET_ASSERTS_IN msgrequest */ 762#define MC_CMD_GET_ASSERTS_IN_LEN 4 763/* Set to clear assertion */ 764#define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0 765 766/* MC_CMD_GET_ASSERTS_OUT msgresponse */ 767#define MC_CMD_GET_ASSERTS_OUT_LEN 140 768/* Assertion status flag. */ 769#define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0 770/* enum: No assertions have failed. */ 771#define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 772/* enum: A system-level assertion has failed. */ 773#define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 774/* enum: A thread-level assertion has failed. */ 775#define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 776/* enum: The system was reset by the watchdog. */ 777#define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 778/* enum: An illegal address trap stopped the system (huntington and later) */ 779#define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 780/* Failing PC value */ 781#define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4 782/* Saved GP regs */ 783#define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8 784#define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4 785#define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31 786/* Failing thread address */ 787#define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132 788#define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136 789 790 791/***********************************/ 792/* MC_CMD_LOG_CTRL 793 * Configure the output stream for various events and messages. 794 */ 795#define MC_CMD_LOG_CTRL 0x7 796 797/* MC_CMD_LOG_CTRL_IN msgrequest */ 798#define MC_CMD_LOG_CTRL_IN_LEN 8 799/* Log destination */ 800#define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0 801/* enum: UART. */ 802#define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1 803/* enum: Event queue. */ 804#define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2 805#define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4 806 807/* MC_CMD_LOG_CTRL_OUT msgresponse */ 808#define MC_CMD_LOG_CTRL_OUT_LEN 0 809 810 811/***********************************/ 812/* MC_CMD_GET_VERSION 813 * Get version information about the MC firmware. 814 */ 815#define MC_CMD_GET_VERSION 0x8 816 817/* MC_CMD_GET_VERSION_IN msgrequest */ 818#define MC_CMD_GET_VERSION_IN_LEN 0 819 820/* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */ 821#define MC_CMD_GET_VERSION_EXT_IN_LEN 4 822/* placeholder, set to 0 */ 823#define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0 824 825/* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */ 826#define MC_CMD_GET_VERSION_V0_OUT_LEN 4 827#define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 828/* enum: Reserved version number to indicate "any" version. */ 829#define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff 830/* enum: Bootrom version value for Siena. */ 831#define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000 832/* enum: Bootrom version value for Huntington. */ 833#define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001 834 835/* MC_CMD_GET_VERSION_OUT msgresponse */ 836#define MC_CMD_GET_VERSION_OUT_LEN 32 837/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 838/* Enum values, see field(s): */ 839/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 840#define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4 841/* 128bit mask of functions supported by the current firmware */ 842#define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8 843#define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16 844#define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24 845#define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8 846#define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24 847#define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28 848 849/* MC_CMD_GET_VERSION_EXT_OUT msgresponse */ 850#define MC_CMD_GET_VERSION_EXT_OUT_LEN 48 851/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 852/* Enum values, see field(s): */ 853/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 854#define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4 855/* 128bit mask of functions supported by the current firmware */ 856#define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8 857#define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16 858#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24 859#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8 860#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24 861#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28 862/* extra info */ 863#define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32 864#define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16 865 866 867/***********************************/ 868/* MC_CMD_PTP 869 * Perform PTP operation 870 */ 871#define MC_CMD_PTP 0xb 872 873/* MC_CMD_PTP_IN msgrequest */ 874#define MC_CMD_PTP_IN_LEN 1 875/* PTP operation code */ 876#define MC_CMD_PTP_IN_OP_OFST 0 877#define MC_CMD_PTP_IN_OP_LEN 1 878/* enum: Enable PTP packet timestamping operation. */ 879#define MC_CMD_PTP_OP_ENABLE 0x1 880/* enum: Disable PTP packet timestamping operation. */ 881#define MC_CMD_PTP_OP_DISABLE 0x2 882/* enum: Send a PTP packet. */ 883#define MC_CMD_PTP_OP_TRANSMIT 0x3 884/* enum: Read the current NIC time. */ 885#define MC_CMD_PTP_OP_READ_NIC_TIME 0x4 886/* enum: Get the current PTP status. */ 887#define MC_CMD_PTP_OP_STATUS 0x5 888/* enum: Adjust the PTP NIC's time. */ 889#define MC_CMD_PTP_OP_ADJUST 0x6 890/* enum: Synchronize host and NIC time. */ 891#define MC_CMD_PTP_OP_SYNCHRONIZE 0x7 892/* enum: Basic manufacturing tests. */ 893#define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8 894/* enum: Packet based manufacturing tests. */ 895#define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9 896/* enum: Reset some of the PTP related statistics */ 897#define MC_CMD_PTP_OP_RESET_STATS 0xa 898/* enum: Debug operations to MC. */ 899#define MC_CMD_PTP_OP_DEBUG 0xb 900/* enum: Read an FPGA register */ 901#define MC_CMD_PTP_OP_FPGAREAD 0xc 902/* enum: Write an FPGA register */ 903#define MC_CMD_PTP_OP_FPGAWRITE 0xd 904/* enum: Apply an offset to the NIC clock */ 905#define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe 906/* enum: Change Apply an offset to the NIC clock */ 907#define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf 908/* enum: Set the MC packet filter VLAN tags for received PTP packets */ 909#define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10 910/* enum: Set the MC packet filter UUID for received PTP packets */ 911#define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11 912/* enum: Set the MC packet filter Domain for received PTP packets */ 913#define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12 914/* enum: Set the clock source */ 915#define MC_CMD_PTP_OP_SET_CLK_SRC 0x13 916/* enum: Reset value of Timer Reg. */ 917#define MC_CMD_PTP_OP_RST_CLK 0x14 918/* enum: Enable the forwarding of PPS events to the host */ 919#define MC_CMD_PTP_OP_PPS_ENABLE 0x15 920/* enum: Get the time format used by this NIC for PTP operations */ 921#define MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16 922/* enum: Get the clock attributes. NOTE- extended version of 923 * MC_CMD_PTP_OP_GET_TIME_FORMAT 924 */ 925#define MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16 926/* enum: Get corrections that should be applied to the various different 927 * timestamps 928 */ 929#define MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17 930/* enum: Subscribe to receive periodic time events indicating the current NIC 931 * time 932 */ 933#define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18 934/* enum: Unsubscribe to stop receiving time events */ 935#define MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19 936/* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS 937 * input on the same NIC. 938 */ 939#define MC_CMD_PTP_OP_MANFTEST_PPS 0x1a 940/* enum: Above this for future use. */ 941#define MC_CMD_PTP_OP_MAX 0x1b 942 943/* MC_CMD_PTP_IN_ENABLE msgrequest */ 944#define MC_CMD_PTP_IN_ENABLE_LEN 16 945#define MC_CMD_PTP_IN_CMD_OFST 0 946#define MC_CMD_PTP_IN_PERIPH_ID_OFST 4 947/* Event queue for PTP events */ 948#define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8 949/* PTP timestamping mode */ 950#define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12 951/* enum: PTP, version 1 */ 952#define MC_CMD_PTP_MODE_V1 0x0 953/* enum: PTP, version 1, with VLAN headers - deprecated */ 954#define MC_CMD_PTP_MODE_V1_VLAN 0x1 955/* enum: PTP, version 2 */ 956#define MC_CMD_PTP_MODE_V2 0x2 957/* enum: PTP, version 2, with VLAN headers - deprecated */ 958#define MC_CMD_PTP_MODE_V2_VLAN 0x3 959/* enum: PTP, version 2, with improved UUID filtering */ 960#define MC_CMD_PTP_MODE_V2_ENHANCED 0x4 961/* enum: FCoE (seconds and microseconds) */ 962#define MC_CMD_PTP_MODE_FCOE 0x5 963 964/* MC_CMD_PTP_IN_DISABLE msgrequest */ 965#define MC_CMD_PTP_IN_DISABLE_LEN 8 966/* MC_CMD_PTP_IN_CMD_OFST 0 */ 967/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 968 969/* MC_CMD_PTP_IN_TRANSMIT msgrequest */ 970#define MC_CMD_PTP_IN_TRANSMIT_LENMIN 13 971#define MC_CMD_PTP_IN_TRANSMIT_LENMAX 252 972#define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num)) 973/* MC_CMD_PTP_IN_CMD_OFST 0 */ 974/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 975/* Transmit packet length */ 976#define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8 977/* Transmit packet data */ 978#define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12 979#define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1 980#define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1 981#define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240 982 983/* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */ 984#define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8 985/* MC_CMD_PTP_IN_CMD_OFST 0 */ 986/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 987 988/* MC_CMD_PTP_IN_STATUS msgrequest */ 989#define MC_CMD_PTP_IN_STATUS_LEN 8 990/* MC_CMD_PTP_IN_CMD_OFST 0 */ 991/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 992 993/* MC_CMD_PTP_IN_ADJUST msgrequest */ 994#define MC_CMD_PTP_IN_ADJUST_LEN 24 995/* MC_CMD_PTP_IN_CMD_OFST 0 */ 996/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 997/* Frequency adjustment 40 bit fixed point ns */ 998#define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8 999#define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8 1000#define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8 1001#define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12 1002/* enum: Number of fractional bits in frequency adjustment */ 1003#define MC_CMD_PTP_IN_ADJUST_BITS 0x28 1004/* Time adjustment in seconds */ 1005#define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16 1006/* Time adjustment major value */ 1007#define MC_CMD_PTP_IN_ADJUST_MAJOR_OFST 16 1008/* Time adjustment in nanoseconds */ 1009#define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20 1010/* Time adjustment minor value */ 1011#define MC_CMD_PTP_IN_ADJUST_MINOR_OFST 20 1012 1013/* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */ 1014#define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20 1015/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1016/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1017/* Number of time readings to capture */ 1018#define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8 1019/* Host address in which to write "synchronization started" indication (64 1020 * bits) 1021 */ 1022#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12 1023#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8 1024#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12 1025#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16 1026 1027/* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */ 1028#define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8 1029/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1030/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1031 1032/* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */ 1033#define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12 1034/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1035/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1036/* Enable or disable packet testing */ 1037#define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8 1038 1039/* MC_CMD_PTP_IN_RESET_STATS msgrequest */ 1040#define MC_CMD_PTP_IN_RESET_STATS_LEN 8 1041/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1042/* Reset PTP statistics */ 1043/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1044 1045/* MC_CMD_PTP_IN_DEBUG msgrequest */ 1046#define MC_CMD_PTP_IN_DEBUG_LEN 12 1047/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1048/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1049/* Debug operations */ 1050#define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8 1051 1052/* MC_CMD_PTP_IN_FPGAREAD msgrequest */ 1053#define MC_CMD_PTP_IN_FPGAREAD_LEN 16 1054/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1055/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1056#define MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8 1057#define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12 1058 1059/* MC_CMD_PTP_IN_FPGAWRITE msgrequest */ 1060#define MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13 1061#define MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252 1062#define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num)) 1063/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1064/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1065#define MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8 1066#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12 1067#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1 1068#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1 1069#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240 1070 1071/* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */ 1072#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16 1073/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1074/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1075/* Time adjustment in seconds */ 1076#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8 1077/* Time adjustment major value */ 1078#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_OFST 8 1079/* Time adjustment in nanoseconds */ 1080#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12 1081/* Time adjustment minor value */ 1082#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_OFST 12 1083 1084/* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */ 1085#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16 1086/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1087/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1088/* Frequency adjustment 40 bit fixed point ns */ 1089#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8 1090#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8 1091#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8 1092#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12 1093/* enum: Number of fractional bits in frequency adjustment */ 1094/* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */ 1095 1096/* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */ 1097#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24 1098/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1099/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1100/* Number of VLAN tags, 0 if not VLAN */ 1101#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8 1102/* Set of VLAN tags to filter against */ 1103#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12 1104#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4 1105#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3 1106 1107/* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */ 1108#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20 1109/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1110/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1111/* 1 to enable UUID filtering, 0 to disable */ 1112#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8 1113/* UUID to filter against */ 1114#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12 1115#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8 1116#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12 1117#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16 1118 1119/* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */ 1120#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16 1121/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1122/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1123/* 1 to enable Domain filtering, 0 to disable */ 1124#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8 1125/* Domain number to filter against */ 1126#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12 1127 1128/* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */ 1129#define MC_CMD_PTP_IN_SET_CLK_SRC_LEN 12 1130/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1131/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1132/* Set the clock source. */ 1133#define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8 1134/* enum: Internal. */ 1135#define MC_CMD_PTP_CLK_SRC_INTERNAL 0x0 1136/* enum: External. */ 1137#define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1 1138 1139/* MC_CMD_PTP_IN_RST_CLK msgrequest */ 1140#define MC_CMD_PTP_IN_RST_CLK_LEN 8 1141/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1142/* Reset value of Timer Reg. */ 1143/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1144 1145/* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */ 1146#define MC_CMD_PTP_IN_PPS_ENABLE_LEN 12 1147/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1148/* Enable or disable */ 1149#define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4 1150/* enum: Enable */ 1151#define MC_CMD_PTP_ENABLE_PPS 0x0 1152/* enum: Disable */ 1153#define MC_CMD_PTP_DISABLE_PPS 0x1 1154/* Queue id to send events back */ 1155#define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8 1156 1157/* MC_CMD_PTP_IN_GET_TIME_FORMAT msgrequest */ 1158#define MC_CMD_PTP_IN_GET_TIME_FORMAT_LEN 8 1159/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1160/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1161 1162/* MC_CMD_PTP_IN_GET_ATTRIBUTES msgrequest */ 1163#define MC_CMD_PTP_IN_GET_ATTRIBUTES_LEN 8 1164/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1165/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1166 1167/* MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS msgrequest */ 1168#define MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS_LEN 8 1169/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1170/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1171 1172/* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE msgrequest */ 1173#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN 12 1174/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1175/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1176/* Event queue to send PTP time events to */ 1177#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 8 1178 1179/* MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE msgrequest */ 1180#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN 16 1181/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1182/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1183/* Unsubscribe options */ 1184#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_OFST 8 1185/* enum: Unsubscribe a single queue */ 1186#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0 1187/* enum: Unsubscribe all queues */ 1188#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1 1189/* Event queue ID */ 1190#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12 1191 1192/* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */ 1193#define MC_CMD_PTP_IN_MANFTEST_PPS_LEN 12 1194/* MC_CMD_PTP_IN_CMD_OFST 0 */ 1195/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1196/* 1 to enable PPS test mode, 0 to disable and return result. */ 1197#define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_OFST 8 1198 1199/* MC_CMD_PTP_OUT msgresponse */ 1200#define MC_CMD_PTP_OUT_LEN 0 1201 1202/* MC_CMD_PTP_OUT_TRANSMIT msgresponse */ 1203#define MC_CMD_PTP_OUT_TRANSMIT_LEN 8 1204/* Value of seconds timestamp */ 1205#define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0 1206/* Timestamp major value */ 1207#define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0 1208/* Value of nanoseconds timestamp */ 1209#define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4 1210/* Timestamp minor value */ 1211#define MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4 1212 1213/* MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE msgresponse */ 1214#define MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0 1215 1216/* MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE msgresponse */ 1217#define MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0 1218 1219/* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */ 1220#define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8 1221/* Value of seconds timestamp */ 1222#define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0 1223/* Timestamp major value */ 1224#define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0 1225/* Value of nanoseconds timestamp */ 1226#define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4 1227/* Timestamp minor value */ 1228#define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4 1229 1230/* MC_CMD_PTP_OUT_STATUS msgresponse */ 1231#define MC_CMD_PTP_OUT_STATUS_LEN 64 1232/* Frequency of NIC's hardware clock */ 1233#define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0 1234/* Number of packets transmitted and timestamped */ 1235#define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4 1236/* Number of packets received and timestamped */ 1237#define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8 1238/* Number of packets timestamped by the FPGA */ 1239#define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12 1240/* Number of packets filter matched */ 1241#define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16 1242/* Number of packets not filter matched */ 1243#define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20 1244/* Number of PPS overflows (noise on input?) */ 1245#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24 1246/* Number of PPS bad periods */ 1247#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28 1248/* Minimum period of PPS pulse in nanoseconds */ 1249#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32 1250/* Maximum period of PPS pulse in nanoseconds */ 1251#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36 1252/* Last period of PPS pulse in nanoseconds */ 1253#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40 1254/* Mean period of PPS pulse in nanoseconds */ 1255#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44 1256/* Minimum offset of PPS pulse in nanoseconds (signed) */ 1257#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48 1258/* Maximum offset of PPS pulse in nanoseconds (signed) */ 1259#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52 1260/* Last offset of PPS pulse in nanoseconds (signed) */ 1261#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56 1262/* Mean offset of PPS pulse in nanoseconds (signed) */ 1263#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60 1264 1265/* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */ 1266#define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20 1267#define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240 1268#define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num)) 1269/* A set of host and NIC times */ 1270#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0 1271#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20 1272#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1 1273#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12 1274/* Host time immediately before NIC's hardware clock read */ 1275#define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0 1276/* Value of seconds timestamp */ 1277#define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4 1278/* Timestamp major value */ 1279#define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4 1280/* Value of nanoseconds timestamp */ 1281#define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8 1282/* Timestamp minor value */ 1283#define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 8 1284/* Host time immediately after NIC's hardware clock read */ 1285#define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12 1286/* Number of nanoseconds waited after reading NIC's hardware clock */ 1287#define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16 1288 1289/* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */ 1290#define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8 1291/* Results of testing */ 1292#define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0 1293/* enum: Successful test */ 1294#define MC_CMD_PTP_MANF_SUCCESS 0x0 1295/* enum: FPGA load failed */ 1296#define MC_CMD_PTP_MANF_FPGA_LOAD 0x1 1297/* enum: FPGA version invalid */ 1298#define MC_CMD_PTP_MANF_FPGA_VERSION 0x2 1299/* enum: FPGA registers incorrect */ 1300#define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3 1301/* enum: Oscillator possibly not working? */ 1302#define MC_CMD_PTP_MANF_OSCILLATOR 0x4 1303/* enum: Timestamps not increasing */ 1304#define MC_CMD_PTP_MANF_TIMESTAMPS 0x5 1305/* enum: Mismatched packet count */ 1306#define MC_CMD_PTP_MANF_PACKET_COUNT 0x6 1307/* enum: Mismatched packet count (Siena filter and FPGA) */ 1308#define MC_CMD_PTP_MANF_FILTER_COUNT 0x7 1309/* enum: Not enough packets to perform timestamp check */ 1310#define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8 1311/* enum: Timestamp trigger GPIO not working */ 1312#define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9 1313/* enum: Insufficient PPS events to perform checks */ 1314#define MC_CMD_PTP_MANF_PPS_ENOUGH 0xa 1315/* enum: PPS time event period not sufficiently close to 1s. */ 1316#define MC_CMD_PTP_MANF_PPS_PERIOD 0xb 1317/* enum: PPS time event nS reading not sufficiently close to zero. */ 1318#define MC_CMD_PTP_MANF_PPS_NS 0xc 1319/* enum: PTP peripheral registers incorrect */ 1320#define MC_CMD_PTP_MANF_REGISTERS 0xd 1321/* enum: Failed to read time from PTP peripheral */ 1322#define MC_CMD_PTP_MANF_CLOCK_READ 0xe 1323/* Presence of external oscillator */ 1324#define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4 1325 1326/* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */ 1327#define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12 1328/* Results of testing */ 1329#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0 1330/* Number of packets received by FPGA */ 1331#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4 1332/* Number of packets received by Siena filters */ 1333#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8 1334 1335/* MC_CMD_PTP_OUT_FPGAREAD msgresponse */ 1336#define MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1 1337#define MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252 1338#define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num)) 1339#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0 1340#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1 1341#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1 1342#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252 1343 1344/* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */ 1345#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4 1346/* Time format required/used by for this NIC. Applies to all PTP MCDI 1347 * operations that pass times between the host and firmware. If this operation 1348 * is not supported (older firmware) a format of seconds and nanoseconds should 1349 * be assumed. 1350 */ 1351#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0 1352/* enum: Times are in seconds and nanoseconds */ 1353#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0 1354/* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ 1355#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1 1356/* enum: Major register has units of seconds, minor 2^-27s per tick */ 1357#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2 1358 1359/* MC_CMD_PTP_OUT_GET_ATTRIBUTES msgresponse */ 1360#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_LEN 8 1361/* Time format required/used by for this NIC. Applies to all PTP MCDI 1362 * operations that pass times between the host and firmware. If this operation 1363 * is not supported (older firmware) a format of seconds and nanoseconds should 1364 * be assumed. 1365 */ 1366#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0 1367/* enum: Times are in seconds and nanoseconds */ 1368#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0 1369/* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ 1370#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1 1371/* enum: Major register has units of seconds, minor 2^-27s per tick */ 1372#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2 1373/* Minimum acceptable value for a corrected synchronization timeset. When 1374 * comparing host and NIC clock times, the MC returns a set of samples that 1375 * contain the host start and end time, the MC time when the host start was 1376 * detected and the time the MC waited between reading the time and detecting 1377 * the host end. The corrected sync window is the difference between the host 1378 * end and start times minus the time that the MC waited for host end. 1379 */ 1380#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4 1381 1382/* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */ 1383#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16 1384/* Uncorrected error on transmit timestamps in NIC clock format */ 1385#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0 1386/* Uncorrected error on receive timestamps in NIC clock format */ 1387#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4 1388/* Uncorrected error on PPS output in NIC clock format */ 1389#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8 1390/* Uncorrected error on PPS input in NIC clock format */ 1391#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12 1392 1393/* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */ 1394#define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4 1395/* Results of testing */ 1396#define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0 1397/* Enum values, see field(s): */ 1398/* MC_CMD_PTP_OUT_MANFTEST_BASIC/TEST_RESULT */ 1399 1400 1401/***********************************/ 1402/* MC_CMD_CSR_READ32 1403 * Read 32bit words from the indirect memory map. 1404 */ 1405#define MC_CMD_CSR_READ32 0xc 1406 1407/* MC_CMD_CSR_READ32_IN msgrequest */ 1408#define MC_CMD_CSR_READ32_IN_LEN 12 1409/* Address */ 1410#define MC_CMD_CSR_READ32_IN_ADDR_OFST 0 1411#define MC_CMD_CSR_READ32_IN_STEP_OFST 4 1412#define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8 1413 1414/* MC_CMD_CSR_READ32_OUT msgresponse */ 1415#define MC_CMD_CSR_READ32_OUT_LENMIN 4 1416#define MC_CMD_CSR_READ32_OUT_LENMAX 252 1417#define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num)) 1418/* The last dword is the status, not a value read */ 1419#define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0 1420#define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4 1421#define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1 1422#define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63 1423 1424 1425/***********************************/ 1426/* MC_CMD_CSR_WRITE32 1427 * Write 32bit dwords to the indirect memory map. 1428 */ 1429#define MC_CMD_CSR_WRITE32 0xd 1430 1431/* MC_CMD_CSR_WRITE32_IN msgrequest */ 1432#define MC_CMD_CSR_WRITE32_IN_LENMIN 12 1433#define MC_CMD_CSR_WRITE32_IN_LENMAX 252 1434#define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num)) 1435/* Address */ 1436#define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0 1437#define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4 1438#define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8 1439#define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4 1440#define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1 1441#define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61 1442 1443/* MC_CMD_CSR_WRITE32_OUT msgresponse */ 1444#define MC_CMD_CSR_WRITE32_OUT_LEN 4 1445#define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0 1446 1447 1448/***********************************/ 1449/* MC_CMD_HP 1450 * These commands are used for HP related features. They are grouped under one 1451 * MCDI command to avoid creating too many MCDI commands. 1452 */ 1453#define MC_CMD_HP 0x54 1454 1455/* MC_CMD_HP_IN msgrequest */ 1456#define MC_CMD_HP_IN_LEN 16 1457/* HP OCSD sub-command. When address is not NULL, request activation of OCSD at 1458 * the specified address with the specified interval.When address is NULL, 1459 * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current 1460 * state / 2: (debug) Show temperature reported by one of the supported 1461 * sensors. 1462 */ 1463#define MC_CMD_HP_IN_SUBCMD_OFST 0 1464/* enum: OCSD (Option Card Sensor Data) sub-command. */ 1465#define MC_CMD_HP_IN_OCSD_SUBCMD 0x0 1466/* enum: Last known valid HP sub-command. */ 1467#define MC_CMD_HP_IN_LAST_SUBCMD 0x0 1468/* The address to the array of sensor fields. (Or NULL to use a sub-command.) 1469 */ 1470#define MC_CMD_HP_IN_OCSD_ADDR_OFST 4 1471#define MC_CMD_HP_IN_OCSD_ADDR_LEN 8 1472#define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4 1473#define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8 1474/* The requested update interval, in seconds. (Or the sub-command if ADDR is 1475 * NULL.) 1476 */ 1477#define MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12 1478 1479/* MC_CMD_HP_OUT msgresponse */ 1480#define MC_CMD_HP_OUT_LEN 4 1481#define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0 1482/* enum: OCSD stopped for this card. */ 1483#define MC_CMD_HP_OUT_OCSD_STOPPED 0x1 1484/* enum: OCSD was successfully started with the address provided. */ 1485#define MC_CMD_HP_OUT_OCSD_STARTED 0x2 1486/* enum: OCSD was already started for this card. */ 1487#define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3 1488 1489 1490/***********************************/ 1491/* MC_CMD_STACKINFO 1492 * Get stack information. 1493 */ 1494#define MC_CMD_STACKINFO 0xf 1495 1496/* MC_CMD_STACKINFO_IN msgrequest */ 1497#define MC_CMD_STACKINFO_IN_LEN 0 1498 1499/* MC_CMD_STACKINFO_OUT msgresponse */ 1500#define MC_CMD_STACKINFO_OUT_LENMIN 12 1501#define MC_CMD_STACKINFO_OUT_LENMAX 252 1502#define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num)) 1503/* (thread ptr, stack size, free space) for each thread in system */ 1504#define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0 1505#define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12 1506#define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1 1507#define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21 1508 1509 1510/***********************************/ 1511/* MC_CMD_MDIO_READ 1512 * MDIO register read. 1513 */ 1514#define MC_CMD_MDIO_READ 0x10 1515 1516/* MC_CMD_MDIO_READ_IN msgrequest */ 1517#define MC_CMD_MDIO_READ_IN_LEN 16 1518/* Bus number; there are two MDIO buses: one for the internal PHY, and one for 1519 * external devices. 1520 */ 1521#define MC_CMD_MDIO_READ_IN_BUS_OFST 0 1522/* enum: Internal. */ 1523#define MC_CMD_MDIO_BUS_INTERNAL 0x0 1524/* enum: External. */ 1525#define MC_CMD_MDIO_BUS_EXTERNAL 0x1 1526/* Port address */ 1527#define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4 1528/* Device Address or clause 22. */ 1529#define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8 1530/* enum: By default all the MCDI MDIO operations perform clause45 mode. If you 1531 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 1532 */ 1533#define MC_CMD_MDIO_CLAUSE22 0x20 1534/* Address */ 1535#define MC_CMD_MDIO_READ_IN_ADDR_OFST 12 1536 1537/* MC_CMD_MDIO_READ_OUT msgresponse */ 1538#define MC_CMD_MDIO_READ_OUT_LEN 8 1539/* Value */ 1540#define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0 1541/* Status the MDIO commands return the raw status bits from the MDIO block. A 1542 * "good" transaction should have the DONE bit set and all other bits clear. 1543 */ 1544#define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4 1545/* enum: Good. */ 1546#define MC_CMD_MDIO_STATUS_GOOD 0x8 1547 1548 1549/***********************************/ 1550/* MC_CMD_MDIO_WRITE 1551 * MDIO register write. 1552 */ 1553#define MC_CMD_MDIO_WRITE 0x11 1554 1555/* MC_CMD_MDIO_WRITE_IN msgrequest */ 1556#define MC_CMD_MDIO_WRITE_IN_LEN 20 1557/* Bus number; there are two MDIO buses: one for the internal PHY, and one for 1558 * external devices. 1559 */ 1560#define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0 1561/* enum: Internal. */ 1562/* MC_CMD_MDIO_BUS_INTERNAL 0x0 */ 1563/* enum: External. */ 1564/* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */ 1565/* Port address */ 1566#define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4 1567/* Device Address or clause 22. */ 1568#define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8 1569/* enum: By default all the MCDI MDIO operations perform clause45 mode. If you 1570 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 1571 */ 1572/* MC_CMD_MDIO_CLAUSE22 0x20 */ 1573/* Address */ 1574#define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12 1575/* Value */ 1576#define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16 1577 1578/* MC_CMD_MDIO_WRITE_OUT msgresponse */ 1579#define MC_CMD_MDIO_WRITE_OUT_LEN 4 1580/* Status; the MDIO commands return the raw status bits from the MDIO block. A 1581 * "good" transaction should have the DONE bit set and all other bits clear. 1582 */ 1583#define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0 1584/* enum: Good. */ 1585/* MC_CMD_MDIO_STATUS_GOOD 0x8 */ 1586 1587 1588/***********************************/ 1589/* MC_CMD_DBI_WRITE 1590 * Write DBI register(s). 1591 */ 1592#define MC_CMD_DBI_WRITE 0x12 1593 1594/* MC_CMD_DBI_WRITE_IN msgrequest */ 1595#define MC_CMD_DBI_WRITE_IN_LENMIN 12 1596#define MC_CMD_DBI_WRITE_IN_LENMAX 252 1597#define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num)) 1598/* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset 1599 * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF. 1600 */ 1601#define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0 1602#define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12 1603#define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1 1604#define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21 1605 1606/* MC_CMD_DBI_WRITE_OUT msgresponse */ 1607#define MC_CMD_DBI_WRITE_OUT_LEN 0 1608 1609/* MC_CMD_DBIWROP_TYPEDEF structuredef */ 1610#define MC_CMD_DBIWROP_TYPEDEF_LEN 12 1611#define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0 1612#define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0 1613#define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32 1614#define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4 1615#define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16 1616#define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16 1617#define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15 1618#define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1 1619#define MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14 1620#define MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1 1621#define MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32 1622#define MC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 32 1623#define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8 1624#define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64 1625#define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32 1626 1627 1628/***********************************/ 1629/* MC_CMD_PORT_READ32 1630 * Read a 32-bit register from the indirect port register map. The port to 1631 * access is implied by the Shared memory channel used. 1632 */ 1633#define MC_CMD_PORT_READ32 0x14 1634 1635/* MC_CMD_PORT_READ32_IN msgrequest */ 1636#define MC_CMD_PORT_READ32_IN_LEN 4 1637/* Address */ 1638#define MC_CMD_PORT_READ32_IN_ADDR_OFST 0 1639 1640/* MC_CMD_PORT_READ32_OUT msgresponse */ 1641#define MC_CMD_PORT_READ32_OUT_LEN 8 1642/* Value */ 1643#define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0 1644/* Status */ 1645#define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4 1646 1647 1648/***********************************/ 1649/* MC_CMD_PORT_WRITE32 1650 * Write a 32-bit register to the indirect port register map. The port to 1651 * access is implied by the Shared memory channel used. 1652 */ 1653#define MC_CMD_PORT_WRITE32 0x15 1654 1655/* MC_CMD_PORT_WRITE32_IN msgrequest */ 1656#define MC_CMD_PORT_WRITE32_IN_LEN 8 1657/* Address */ 1658#define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0 1659/* Value */ 1660#define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4 1661 1662/* MC_CMD_PORT_WRITE32_OUT msgresponse */ 1663#define MC_CMD_PORT_WRITE32_OUT_LEN 4 1664/* Status */ 1665#define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0 1666 1667 1668/***********************************/ 1669/* MC_CMD_PORT_READ128 1670 * Read a 128-bit register from the indirect port register map. The port to 1671 * access is implied by the Shared memory channel used. 1672 */ 1673#define MC_CMD_PORT_READ128 0x16 1674 1675/* MC_CMD_PORT_READ128_IN msgrequest */ 1676#define MC_CMD_PORT_READ128_IN_LEN 4 1677/* Address */ 1678#define MC_CMD_PORT_READ128_IN_ADDR_OFST 0 1679 1680/* MC_CMD_PORT_READ128_OUT msgresponse */ 1681#define MC_CMD_PORT_READ128_OUT_LEN 20 1682/* Value */ 1683#define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0 1684#define MC_CMD_PORT_READ128_OUT_VALUE_LEN 16 1685/* Status */ 1686#define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16 1687 1688 1689/***********************************/ 1690/* MC_CMD_PORT_WRITE128 1691 * Write a 128-bit register to the indirect port register map. The port to 1692 * access is implied by the Shared memory channel used. 1693 */ 1694#define MC_CMD_PORT_WRITE128 0x17 1695 1696/* MC_CMD_PORT_WRITE128_IN msgrequest */ 1697#define MC_CMD_PORT_WRITE128_IN_LEN 20 1698/* Address */ 1699#define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0 1700/* Value */ 1701#define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4 1702#define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16 1703 1704/* MC_CMD_PORT_WRITE128_OUT msgresponse */ 1705#define MC_CMD_PORT_WRITE128_OUT_LEN 4 1706/* Status */ 1707#define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0 1708 1709/* MC_CMD_CAPABILITIES structuredef */ 1710#define MC_CMD_CAPABILITIES_LEN 4 1711/* Small buf table. */ 1712#define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0 1713#define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1 1714/* Turbo mode (for Maranello). */ 1715#define MC_CMD_CAPABILITIES_TURBO_LBN 1 1716#define MC_CMD_CAPABILITIES_TURBO_WIDTH 1 1717/* Turbo mode active (for Maranello). */ 1718#define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 2 1719#define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1 1720/* PTP offload. */ 1721#define MC_CMD_CAPABILITIES_PTP_LBN 3 1722#define MC_CMD_CAPABILITIES_PTP_WIDTH 1 1723/* AOE mode. */ 1724#define MC_CMD_CAPABILITIES_AOE_LBN 4 1725#define MC_CMD_CAPABILITIES_AOE_WIDTH 1 1726/* AOE mode active. */ 1727#define MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 5 1728#define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1 1729/* AOE mode active. */ 1730#define MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 6 1731#define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1 1732#define MC_CMD_CAPABILITIES_RESERVED_LBN 7 1733#define MC_CMD_CAPABILITIES_RESERVED_WIDTH 25 1734 1735 1736/***********************************/ 1737/* MC_CMD_GET_BOARD_CFG 1738 * Returns the MC firmware configuration structure. 1739 */ 1740#define MC_CMD_GET_BOARD_CFG 0x18 1741 1742/* MC_CMD_GET_BOARD_CFG_IN msgrequest */ 1743#define MC_CMD_GET_BOARD_CFG_IN_LEN 0 1744 1745/* MC_CMD_GET_BOARD_CFG_OUT msgresponse */ 1746#define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96 1747#define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136 1748#define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num)) 1749#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0 1750#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4 1751#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32 1752/* See MC_CMD_CAPABILITIES */ 1753#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36 1754/* See MC_CMD_CAPABILITIES */ 1755#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40 1756#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44 1757#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6 1758#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50 1759#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6 1760#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56 1761#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60 1762#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64 1763#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68 1764/* This field contains a 16-bit value for each of the types of NVRAM area. The 1765 * values are defined in the firmware/mc/platform/.c file for a specific board 1766 * type, but otherwise have no meaning to the MC; they are used by the driver 1767 * to manage selection of appropriate firmware updates. 1768 */ 1769#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72 1770#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2 1771#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12 1772#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32 1773 1774 1775/***********************************/ 1776/* MC_CMD_DBI_READX 1777 * Read DBI register(s) -- extended functionality 1778 */ 1779#define MC_CMD_DBI_READX 0x19 1780 1781/* MC_CMD_DBI_READX_IN msgrequest */ 1782#define MC_CMD_DBI_READX_IN_LENMIN 8 1783#define MC_CMD_DBI_READX_IN_LENMAX 248 1784#define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num)) 1785/* Each Read op consists of an address (offset 0), VF/CS2) */ 1786#define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0 1787#define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8 1788#define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0 1789#define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4 1790#define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1 1791#define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31 1792 1793/* MC_CMD_DBI_READX_OUT msgresponse */ 1794#define MC_CMD_DBI_READX_OUT_LENMIN 4 1795#define MC_CMD_DBI_READX_OUT_LENMAX 252 1796#define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num)) 1797/* Value */ 1798#define MC_CMD_DBI_READX_OUT_VALUE_OFST 0 1799#define MC_CMD_DBI_READX_OUT_VALUE_LEN 4 1800#define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1 1801#define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63 1802 1803/* MC_CMD_DBIRDOP_TYPEDEF structuredef */ 1804#define MC_CMD_DBIRDOP_TYPEDEF_LEN 8 1805#define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0 1806#define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0 1807#define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32 1808#define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4 1809#define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16 1810#define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16 1811#define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15 1812#define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1 1813#define MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14 1814#define MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1 1815#define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32 1816#define MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 32 1817 1818 1819/***********************************/ 1820/* MC_CMD_SET_RAND_SEED 1821 * Set the 16byte seed for the MC pseudo-random generator. 1822 */ 1823#define MC_CMD_SET_RAND_SEED 0x1a 1824 1825/* MC_CMD_SET_RAND_SEED_IN msgrequest */ 1826#define MC_CMD_SET_RAND_SEED_IN_LEN 16 1827/* Seed value. */ 1828#define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0 1829#define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16 1830 1831/* MC_CMD_SET_RAND_SEED_OUT msgresponse */ 1832#define MC_CMD_SET_RAND_SEED_OUT_LEN 0 1833 1834 1835/***********************************/ 1836/* MC_CMD_LTSSM_HIST 1837 * Retrieve the history of the LTSSM, if the build supports it. 1838 */ 1839#define MC_CMD_LTSSM_HIST 0x1b 1840 1841/* MC_CMD_LTSSM_HIST_IN msgrequest */ 1842#define MC_CMD_LTSSM_HIST_IN_LEN 0 1843 1844/* MC_CMD_LTSSM_HIST_OUT msgresponse */ 1845#define MC_CMD_LTSSM_HIST_OUT_LENMIN 0 1846#define MC_CMD_LTSSM_HIST_OUT_LENMAX 252 1847#define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num)) 1848/* variable number of LTSSM values, as bytes. The history is read-to-clear. */ 1849#define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0 1850#define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4 1851#define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0 1852#define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63 1853 1854 1855/***********************************/ 1856/* MC_CMD_DRV_ATTACH 1857 * Inform MCPU that this port is managed on the host (i.e. driver active). For 1858 * Huntington, also request the preferred datapath firmware to use if possible 1859 * (it may not be possible for this request to be fulfilled; the driver must 1860 * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which 1861 * features are actually available). The FIRMWARE_ID field is ignored by older 1862 * platforms. 1863 */ 1864#define MC_CMD_DRV_ATTACH 0x1c 1865 1866/* MC_CMD_DRV_ATTACH_IN msgrequest */ 1867#define MC_CMD_DRV_ATTACH_IN_LEN 12 1868/* new state (0=detached, 1=attached) to set if UPDATE=1 */ 1869#define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0 1870/* 1 to set new state, or 0 to just report the existing state */ 1871#define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4 1872/* preferred datapath firmware (for Huntington; ignored for Siena) */ 1873#define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8 1874/* enum: Prefer to use full featured firmware */ 1875#define MC_CMD_FW_FULL_FEATURED 0x0 1876/* enum: Prefer to use firmware with fewer features but lower latency */ 1877#define MC_CMD_FW_LOW_LATENCY 0x1 1878 1879/* MC_CMD_DRV_ATTACH_OUT msgresponse */ 1880#define MC_CMD_DRV_ATTACH_OUT_LEN 4 1881/* previous or existing state (0=detached, 1=attached) */ 1882#define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0 1883 1884/* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */ 1885#define MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8 1886/* previous or existing state (0=detached, 1=attached) */ 1887#define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0 1888/* Flags associated with this function */ 1889#define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4 1890/* enum: Labels the lowest-numbered function visible to the OS */ 1891#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0 1892/* enum: The function can control the link state of the physical port it is 1893 * bound to. 1894 */ 1895#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1 1896/* enum: The function can perform privileged operations */ 1897#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2 1898 1899 1900/***********************************/ 1901/* MC_CMD_SHMUART 1902 * Route UART output to circular buffer in shared memory instead. 1903 */ 1904#define MC_CMD_SHMUART 0x1f 1905 1906/* MC_CMD_SHMUART_IN msgrequest */ 1907#define MC_CMD_SHMUART_IN_LEN 4 1908/* ??? */ 1909#define MC_CMD_SHMUART_IN_FLAG_OFST 0 1910 1911/* MC_CMD_SHMUART_OUT msgresponse */ 1912#define MC_CMD_SHMUART_OUT_LEN 0 1913 1914 1915/***********************************/ 1916/* MC_CMD_PORT_RESET 1917 * Generic per-port reset. There is no equivalent for per-board reset. Locks 1918 * required: None; Return code: 0, ETIME. NOTE: This command is deprecated - 1919 * use MC_CMD_ENTITY_RESET instead. 1920 */ 1921#define MC_CMD_PORT_RESET 0x20 1922 1923/* MC_CMD_PORT_RESET_IN msgrequest */ 1924#define MC_CMD_PORT_RESET_IN_LEN 0 1925 1926/* MC_CMD_PORT_RESET_OUT msgresponse */ 1927#define MC_CMD_PORT_RESET_OUT_LEN 0 1928 1929 1930/***********************************/ 1931/* MC_CMD_ENTITY_RESET 1932 * Generic per-resource reset. There is no equivalent for per-board reset. 1933 * Locks required: None; Return code: 0, ETIME. NOTE: This command is an 1934 * extended version of the deprecated MC_CMD_PORT_RESET with added fields. 1935 */ 1936#define MC_CMD_ENTITY_RESET 0x20 1937 1938/* MC_CMD_ENTITY_RESET_IN msgrequest */ 1939#define MC_CMD_ENTITY_RESET_IN_LEN 4 1940/* Optional flags field. Omitting this will perform a "legacy" reset action 1941 * (TBD). 1942 */ 1943#define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0 1944#define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0 1945#define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1 1946 1947/* MC_CMD_ENTITY_RESET_OUT msgresponse */ 1948#define MC_CMD_ENTITY_RESET_OUT_LEN 0 1949 1950 1951/***********************************/ 1952/* MC_CMD_PCIE_CREDITS 1953 * Read instantaneous and minimum flow control thresholds. 1954 */ 1955#define MC_CMD_PCIE_CREDITS 0x21 1956 1957/* MC_CMD_PCIE_CREDITS_IN msgrequest */ 1958#define MC_CMD_PCIE_CREDITS_IN_LEN 8 1959/* poll period. 0 is disabled */ 1960#define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0 1961/* wipe statistics */ 1962#define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4 1963 1964/* MC_CMD_PCIE_CREDITS_OUT msgresponse */ 1965#define MC_CMD_PCIE_CREDITS_OUT_LEN 16 1966#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0 1967#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2 1968#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2 1969#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2 1970#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4 1971#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2 1972#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6 1973#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2 1974#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8 1975#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2 1976#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10 1977#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2 1978#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12 1979#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2 1980#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14 1981#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2 1982 1983 1984/***********************************/ 1985/* MC_CMD_RXD_MONITOR 1986 * Get histogram of RX queue fill level. 1987 */ 1988#define MC_CMD_RXD_MONITOR 0x22 1989 1990/* MC_CMD_RXD_MONITOR_IN msgrequest */ 1991#define MC_CMD_RXD_MONITOR_IN_LEN 12 1992#define MC_CMD_RXD_MONITOR_IN_QID_OFST 0 1993#define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4 1994#define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8 1995 1996/* MC_CMD_RXD_MONITOR_OUT msgresponse */ 1997#define MC_CMD_RXD_MONITOR_OUT_LEN 80 1998#define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0 1999#define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4 2000#define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8 2001#define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12 2002#define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16 2003#define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20 2004#define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24 2005#define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28 2006#define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32 2007#define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36 2008#define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40 2009#define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44 2010#define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48 2011#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52 2012#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56 2013#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60 2014#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64 2015#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68 2016#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72 2017#define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76 2018 2019 2020/***********************************/ 2021/* MC_CMD_PUTS 2022 * Copy the given ASCII string out onto UART and/or out of the network port. 2023 */ 2024#define MC_CMD_PUTS 0x23 2025 2026/* MC_CMD_PUTS_IN msgrequest */ 2027#define MC_CMD_PUTS_IN_LENMIN 13 2028#define MC_CMD_PUTS_IN_LENMAX 252 2029#define MC_CMD_PUTS_IN_LEN(num) (12+1*(num)) 2030#define MC_CMD_PUTS_IN_DEST_OFST 0 2031#define MC_CMD_PUTS_IN_UART_LBN 0 2032#define MC_CMD_PUTS_IN_UART_WIDTH 1 2033#define MC_CMD_PUTS_IN_PORT_LBN 1 2034#define MC_CMD_PUTS_IN_PORT_WIDTH 1 2035#define MC_CMD_PUTS_IN_DHOST_OFST 4 2036#define MC_CMD_PUTS_IN_DHOST_LEN 6 2037#define MC_CMD_PUTS_IN_STRING_OFST 12 2038#define MC_CMD_PUTS_IN_STRING_LEN 1 2039#define MC_CMD_PUTS_IN_STRING_MINNUM 1 2040#define MC_CMD_PUTS_IN_STRING_MAXNUM 240 2041 2042/* MC_CMD_PUTS_OUT msgresponse */ 2043#define MC_CMD_PUTS_OUT_LEN 0 2044 2045 2046/***********************************/ 2047/* MC_CMD_GET_PHY_CFG 2048 * Report PHY configuration. This guarantees to succeed even if the PHY is in a 2049 * 'zombie' state. Locks required: None 2050 */ 2051#define MC_CMD_GET_PHY_CFG 0x24 2052 2053/* MC_CMD_GET_PHY_CFG_IN msgrequest */ 2054#define MC_CMD_GET_PHY_CFG_IN_LEN 0 2055 2056/* MC_CMD_GET_PHY_CFG_OUT msgresponse */ 2057#define MC_CMD_GET_PHY_CFG_OUT_LEN 72 2058/* flags */ 2059#define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0 2060#define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0 2061#define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1 2062#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1 2063#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1 2064#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2 2065#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1 2066#define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3 2067#define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1 2068#define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4 2069#define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1 2070#define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5 2071#define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1 2072#define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6 2073#define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1 2074/* ?? */ 2075#define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4 2076/* Bitmask of supported capabilities */ 2077#define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8 2078#define MC_CMD_PHY_CAP_10HDX_LBN 1 2079#define MC_CMD_PHY_CAP_10HDX_WIDTH 1 2080#define MC_CMD_PHY_CAP_10FDX_LBN 2 2081#define MC_CMD_PHY_CAP_10FDX_WIDTH 1 2082#define MC_CMD_PHY_CAP_100HDX_LBN 3 2083#define MC_CMD_PHY_CAP_100HDX_WIDTH 1 2084#define MC_CMD_PHY_CAP_100FDX_LBN 4 2085#define MC_CMD_PHY_CAP_100FDX_WIDTH 1 2086#define MC_CMD_PHY_CAP_1000HDX_LBN 5 2087#define MC_CMD_PHY_CAP_1000HDX_WIDTH 1 2088#define MC_CMD_PHY_CAP_1000FDX_LBN 6 2089#define MC_CMD_PHY_CAP_1000FDX_WIDTH 1 2090#define MC_CMD_PHY_CAP_10000FDX_LBN 7 2091#define MC_CMD_PHY_CAP_10000FDX_WIDTH 1 2092#define MC_CMD_PHY_CAP_PAUSE_LBN 8 2093#define MC_CMD_PHY_CAP_PAUSE_WIDTH 1 2094#define MC_CMD_PHY_CAP_ASYM_LBN 9 2095#define MC_CMD_PHY_CAP_ASYM_WIDTH 1 2096#define MC_CMD_PHY_CAP_AN_LBN 10 2097#define MC_CMD_PHY_CAP_AN_WIDTH 1 2098#define MC_CMD_PHY_CAP_40000FDX_LBN 11 2099#define MC_CMD_PHY_CAP_40000FDX_WIDTH 1 2100#define MC_CMD_PHY_CAP_DDM_LBN 12 2101#define MC_CMD_PHY_CAP_DDM_WIDTH 1 2102/* ?? */ 2103#define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12 2104/* ?? */ 2105#define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16 2106/* ?? */ 2107#define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20 2108/* ?? */ 2109#define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24 2110#define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20 2111/* ?? */ 2112#define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44 2113/* enum: Xaui. */ 2114#define MC_CMD_MEDIA_XAUI 0x1 2115/* enum: CX4. */ 2116#define MC_CMD_MEDIA_CX4 0x2 2117/* enum: KX4. */ 2118#define MC_CMD_MEDIA_KX4 0x3 2119/* enum: XFP Far. */ 2120#define MC_CMD_MEDIA_XFP 0x4 2121/* enum: SFP+. */ 2122#define MC_CMD_MEDIA_SFP_PLUS 0x5 2123/* enum: 10GBaseT. */ 2124#define MC_CMD_MEDIA_BASE_T 0x6 2125/* enum: QSFP+. */ 2126#define MC_CMD_MEDIA_QSFP_PLUS 0x7 2127#define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48 2128/* enum: Native clause 22 */ 2129#define MC_CMD_MMD_CLAUSE22 0x0 2130#define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */ 2131#define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */ 2132#define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */ 2133#define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */ 2134#define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */ 2135#define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */ 2136#define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */ 2137/* enum: Clause22 proxied over clause45 by PHY. */ 2138#define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d 2139#define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */ 2140#define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */ 2141#define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52 2142#define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20 2143 2144 2145/***********************************/ 2146/* MC_CMD_START_BIST 2147 * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST 2148 * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held) 2149 */ 2150#define MC_CMD_START_BIST 0x25 2151 2152/* MC_CMD_START_BIST_IN msgrequest */ 2153#define MC_CMD_START_BIST_IN_LEN 4 2154/* Type of test. */ 2155#define MC_CMD_START_BIST_IN_TYPE_OFST 0 2156/* enum: Run the PHY's short cable BIST. */ 2157#define MC_CMD_PHY_BIST_CABLE_SHORT 0x1 2158/* enum: Run the PHY's long cable BIST. */ 2159#define MC_CMD_PHY_BIST_CABLE_LONG 0x2 2160/* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */ 2161#define MC_CMD_BPX_SERDES_BIST 0x3 2162/* enum: Run the MC loopback tests. */ 2163#define MC_CMD_MC_LOOPBACK_BIST 0x4 2164/* enum: Run the PHY's standard BIST. */ 2165#define MC_CMD_PHY_BIST 0x5 2166/* enum: Run MC RAM test. */ 2167#define MC_CMD_MC_MEM_BIST 0x6 2168/* enum: Run Port RAM test. */ 2169#define MC_CMD_PORT_MEM_BIST 0x7 2170/* enum: Run register test. */ 2171#define MC_CMD_REG_BIST 0x8 2172 2173/* MC_CMD_START_BIST_OUT msgresponse */ 2174#define MC_CMD_START_BIST_OUT_LEN 0 2175 2176 2177/***********************************/ 2178/* MC_CMD_POLL_BIST 2179 * Poll for BIST completion. Returns a single status code, and optionally some 2180 * PHY specific bist output. The driver should only consume the BIST output 2181 * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't 2182 * successfully parse the BIST output, it should still respect the pass/Fail in 2183 * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0, 2184 * EACCES (if PHY_LOCK is not held). 2185 */ 2186#define MC_CMD_POLL_BIST 0x26 2187 2188/* MC_CMD_POLL_BIST_IN msgrequest */ 2189#define MC_CMD_POLL_BIST_IN_LEN 0 2190 2191/* MC_CMD_POLL_BIST_OUT msgresponse */ 2192#define MC_CMD_POLL_BIST_OUT_LEN 8 2193/* result */ 2194#define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 2195/* enum: Running. */ 2196#define MC_CMD_POLL_BIST_RUNNING 0x1 2197/* enum: Passed. */ 2198#define MC_CMD_POLL_BIST_PASSED 0x2 2199/* enum: Failed. */ 2200#define MC_CMD_POLL_BIST_FAILED 0x3 2201/* enum: Timed-out. */ 2202#define MC_CMD_POLL_BIST_TIMEOUT 0x4 2203#define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4 2204 2205/* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */ 2206#define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36 2207/* result */ 2208/* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 2209/* Enum values, see field(s): */ 2210/* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 2211#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4 2212#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8 2213#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12 2214#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16 2215/* Status of each channel A */ 2216#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20 2217/* enum: Ok. */ 2218#define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1 2219/* enum: Open. */ 2220#define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2 2221/* enum: Intra-pair short. */ 2222#define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3 2223/* enum: Inter-pair short. */ 2224#define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4 2225/* enum: Busy. */ 2226#define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9 2227/* Status of each channel B */ 2228#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24 2229/* Enum values, see field(s): */ 2230/* CABLE_STATUS_A */ 2231/* Status of each channel C */ 2232#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28 2233/* Enum values, see field(s): */ 2234/* CABLE_STATUS_A */ 2235/* Status of each channel D */ 2236#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32 2237/* Enum values, see field(s): */ 2238/* CABLE_STATUS_A */ 2239 2240/* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */ 2241#define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8 2242/* result */ 2243/* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 2244/* Enum values, see field(s): */ 2245/* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 2246#define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4 2247/* enum: Complete. */ 2248#define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0 2249/* enum: Bus switch off I2C write. */ 2250#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1 2251/* enum: Bus switch off I2C no access IO exp. */ 2252#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2 2253/* enum: Bus switch off I2C no access module. */ 2254#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3 2255/* enum: IO exp I2C configure. */ 2256#define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4 2257/* enum: Bus switch I2C no cross talk. */ 2258#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5 2259/* enum: Module presence. */ 2260#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6 2261/* enum: Module ID I2C access. */ 2262#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7 2263/* enum: Module ID sane value. */ 2264#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8 2265 2266/* MC_CMD_POLL_BIST_OUT_MEM msgresponse */ 2267#define MC_CMD_POLL_BIST_OUT_MEM_LEN 36 2268/* result */ 2269/* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 2270/* Enum values, see field(s): */ 2271/* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 2272#define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4 2273/* enum: Test has completed. */ 2274#define MC_CMD_POLL_BIST_MEM_COMPLETE 0x0 2275/* enum: RAM test - walk ones. */ 2276#define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1 2277/* enum: RAM test - walk zeros. */ 2278#define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2 2279/* enum: RAM test - walking inversions zeros/ones. */ 2280#define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3 2281/* enum: RAM test - walking inversions checkerboard. */ 2282#define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4 2283/* enum: Register test - set / clear individual bits. */ 2284#define MC_CMD_POLL_BIST_MEM_REG 0x5 2285/* enum: ECC error detected. */ 2286#define MC_CMD_POLL_BIST_MEM_ECC 0x6 2287/* Failure address, only valid if result is POLL_BIST_FAILED */ 2288#define MC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 8 2289/* Bus or address space to which the failure address corresponds */ 2290#define MC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 12 2291/* enum: MC MIPS bus. */ 2292#define MC_CMD_POLL_BIST_MEM_BUS_MC 0x0 2293/* enum: CSR IREG bus. */ 2294#define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1 2295/* enum: RX DPCPU bus. */ 2296#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2 2297/* enum: TX0 DPCPU bus. */ 2298#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3 2299/* enum: TX1 DPCPU bus. */ 2300#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4 2301/* enum: RX DICPU bus. */ 2302#define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5 2303/* enum: TX DICPU bus. */ 2304#define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6 2305/* Pattern written to RAM / register */ 2306#define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 16 2307/* Actual value read from RAM / register */ 2308#define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 20 2309/* ECC error mask */ 2310#define MC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 24 2311/* ECC parity error mask */ 2312#define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 28 2313/* ECC fatal error mask */ 2314#define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32 2315 2316 2317/***********************************/ 2318/* MC_CMD_FLUSH_RX_QUEUES 2319 * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ 2320 * flushes should be initiated via this MCDI operation, rather than via 2321 * directly writing FLUSH_CMD. 2322 * 2323 * The flush is completed (either done/fail) asynchronously (after this command 2324 * returns). The driver must still wait for flush done/failure events as usual. 2325 */ 2326#define MC_CMD_FLUSH_RX_QUEUES 0x27 2327 2328/* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */ 2329#define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4 2330#define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252 2331#define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num)) 2332#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0 2333#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4 2334#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1 2335#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63 2336 2337/* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */ 2338#define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0 2339 2340 2341/***********************************/ 2342/* MC_CMD_GET_LOOPBACK_MODES 2343 * Returns a bitmask of loopback modes available at each speed. 2344 */ 2345#define MC_CMD_GET_LOOPBACK_MODES 0x28 2346 2347/* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */ 2348#define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0 2349 2350/* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */ 2351#define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 40 2352/* Supported loopbacks. */ 2353#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0 2354#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8 2355#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0 2356#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4 2357/* enum: None. */ 2358#define MC_CMD_LOOPBACK_NONE 0x0 2359/* enum: Data. */ 2360#define MC_CMD_LOOPBACK_DATA 0x1 2361/* enum: GMAC. */ 2362#define MC_CMD_LOOPBACK_GMAC 0x2 2363/* enum: XGMII. */ 2364#define MC_CMD_LOOPBACK_XGMII 0x3 2365/* enum: XGXS. */ 2366#define MC_CMD_LOOPBACK_XGXS 0x4 2367/* enum: XAUI. */ 2368#define MC_CMD_LOOPBACK_XAUI 0x5 2369/* enum: GMII. */ 2370#define MC_CMD_LOOPBACK_GMII 0x6 2371/* enum: SGMII. */ 2372#define MC_CMD_LOOPBACK_SGMII 0x7 2373/* enum: XGBR. */ 2374#define MC_CMD_LOOPBACK_XGBR 0x8 2375/* enum: XFI. */ 2376#define MC_CMD_LOOPBACK_XFI 0x9 2377/* enum: XAUI Far. */ 2378#define MC_CMD_LOOPBACK_XAUI_FAR 0xa 2379/* enum: GMII Far. */ 2380#define MC_CMD_LOOPBACK_GMII_FAR 0xb 2381/* enum: SGMII Far. */ 2382#define MC_CMD_LOOPBACK_SGMII_FAR 0xc 2383/* enum: XFI Far. */ 2384#define MC_CMD_LOOPBACK_XFI_FAR 0xd 2385/* enum: GPhy. */ 2386#define MC_CMD_LOOPBACK_GPHY 0xe 2387/* enum: PhyXS. */ 2388#define MC_CMD_LOOPBACK_PHYXS 0xf 2389/* enum: PCS. */ 2390#define MC_CMD_LOOPBACK_PCS 0x10 2391/* enum: PMA-PMD. */ 2392#define MC_CMD_LOOPBACK_PMAPMD 0x11 2393/* enum: Cross-Port. */ 2394#define MC_CMD_LOOPBACK_XPORT 0x12 2395/* enum: XGMII-Wireside. */ 2396#define MC_CMD_LOOPBACK_XGMII_WS 0x13 2397/* enum: XAUI Wireside. */ 2398#define MC_CMD_LOOPBACK_XAUI_WS 0x14 2399/* enum: XAUI Wireside Far. */ 2400#define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 2401/* enum: XAUI Wireside near. */ 2402#define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 2403/* enum: GMII Wireside. */ 2404#define MC_CMD_LOOPBACK_GMII_WS 0x17 2405/* enum: XFI Wireside. */ 2406#define MC_CMD_LOOPBACK_XFI_WS 0x18 2407/* enum: XFI Wireside Far. */ 2408#define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 2409/* enum: PhyXS Wireside. */ 2410#define MC_CMD_LOOPBACK_PHYXS_WS 0x1a 2411/* enum: PMA lanes MAC-Serdes. */ 2412#define MC_CMD_LOOPBACK_PMA_INT 0x1b 2413/* enum: KR Serdes Parallel (Encoder). */ 2414#define MC_CMD_LOOPBACK_SD_NEAR 0x1c 2415/* enum: KR Serdes Serial. */ 2416#define MC_CMD_LOOPBACK_SD_FAR 0x1d 2417/* enum: PMA lanes MAC-Serdes Wireside. */ 2418#define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e 2419/* enum: KR Serdes Parallel Wireside (Full PCS). */ 2420#define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f 2421/* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */ 2422#define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 2423/* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */ 2424#define MC_CMD_LOOPBACK_SD_FEP_WS 0x21 2425/* enum: KR Serdes Serial Wireside. */ 2426#define MC_CMD_LOOPBACK_SD_FES_WS 0x22 2427/* enum: Near side of AOE Siena side port */ 2428#define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 2429/* Supported loopbacks. */ 2430#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8 2431#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8 2432#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8 2433#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12 2434/* Enum values, see field(s): */ 2435/* 100M */ 2436/* Supported loopbacks. */ 2437#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16 2438#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8 2439#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16 2440#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20 2441/* Enum values, see field(s): */ 2442/* 100M */ 2443/* Supported loopbacks. */ 2444#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24 2445#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8 2446#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24 2447#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28 2448/* Enum values, see field(s): */ 2449/* 100M */ 2450/* Supported loopbacks. */ 2451#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32 2452#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8 2453#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32 2454#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36 2455/* Enum values, see field(s): */ 2456/* 100M */ 2457 2458 2459/***********************************/ 2460/* MC_CMD_GET_LINK 2461 * Read the unified MAC/PHY link state. Locks required: None Return code: 0, 2462 * ETIME. 2463 */ 2464#define MC_CMD_GET_LINK 0x29 2465 2466/* MC_CMD_GET_LINK_IN msgrequest */ 2467#define MC_CMD_GET_LINK_IN_LEN 0 2468 2469/* MC_CMD_GET_LINK_OUT msgresponse */ 2470#define MC_CMD_GET_LINK_OUT_LEN 28 2471/* near-side advertised capabilities */ 2472#define MC_CMD_GET_LINK_OUT_CAP_OFST 0 2473/* link-partner advertised capabilities */ 2474#define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4 2475/* Autonegotiated speed in mbit/s. The link may still be down even if this 2476 * reads non-zero. 2477 */ 2478#define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8 2479/* Current loopback setting. */ 2480#define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12 2481/* Enum values, see field(s): */ 2482/* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 2483#define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16 2484#define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0 2485#define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1 2486#define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1 2487#define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1 2488#define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2 2489#define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1 2490#define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3 2491#define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1 2492#define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6 2493#define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1 2494#define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7 2495#define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1 2496/* This returns the negotiated flow control value. */ 2497#define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20 2498/* enum: Flow control is off. */ 2499#define MC_CMD_FCNTL_OFF 0x0 2500/* enum: Respond to flow control. */ 2501#define MC_CMD_FCNTL_RESPOND 0x1 2502/* enum: Respond to and Issue flow control. */ 2503#define MC_CMD_FCNTL_BIDIR 0x2 2504#define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24 2505#define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 2506#define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 2507#define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 2508#define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 2509#define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 2510#define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 2511#define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 2512#define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 2513 2514 2515/***********************************/ 2516/* MC_CMD_SET_LINK 2517 * Write the unified MAC/PHY link configuration. Locks required: None. Return 2518 * code: 0, EINVAL, ETIME 2519 */ 2520#define MC_CMD_SET_LINK 0x2a 2521 2522/* MC_CMD_SET_LINK_IN msgrequest */ 2523#define MC_CMD_SET_LINK_IN_LEN 16 2524/* ??? */ 2525#define MC_CMD_SET_LINK_IN_CAP_OFST 0 2526/* Flags */ 2527#define MC_CMD_SET_LINK_IN_FLAGS_OFST 4 2528#define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0 2529#define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1 2530#define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1 2531#define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1 2532#define MC_CMD_SET_LINK_IN_TXDIS_LBN 2 2533#define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1 2534/* Loopback mode. */ 2535#define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8 2536/* Enum values, see field(s): */ 2537/* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 2538/* A loopback speed of "0" is supported, and means (choose any available 2539 * speed). 2540 */ 2541#define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12 2542 2543/* MC_CMD_SET_LINK_OUT msgresponse */ 2544#define MC_CMD_SET_LINK_OUT_LEN 0 2545 2546 2547/***********************************/ 2548/* MC_CMD_SET_ID_LED 2549 * Set identification LED state. Locks required: None. Return code: 0, EINVAL 2550 */ 2551#define MC_CMD_SET_ID_LED 0x2b 2552 2553/* MC_CMD_SET_ID_LED_IN msgrequest */ 2554#define MC_CMD_SET_ID_LED_IN_LEN 4 2555/* Set LED state. */ 2556#define MC_CMD_SET_ID_LED_IN_STATE_OFST 0 2557#define MC_CMD_LED_OFF 0x0 /* enum */ 2558#define MC_CMD_LED_ON 0x1 /* enum */ 2559#define MC_CMD_LED_DEFAULT 0x2 /* enum */ 2560 2561/* MC_CMD_SET_ID_LED_OUT msgresponse */ 2562#define MC_CMD_SET_ID_LED_OUT_LEN 0 2563 2564 2565/***********************************/ 2566/* MC_CMD_SET_MAC 2567 * Set MAC configuration. Locks required: None. Return code: 0, EINVAL 2568 */ 2569#define MC_CMD_SET_MAC 0x2c 2570 2571/* MC_CMD_SET_MAC_IN msgrequest */ 2572#define MC_CMD_SET_MAC_IN_LEN 24 2573/* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of 2574 * EtherII, VLAN, bug16011 padding). 2575 */ 2576#define MC_CMD_SET_MAC_IN_MTU_OFST 0 2577#define MC_CMD_SET_MAC_IN_DRAIN_OFST 4 2578#define MC_CMD_SET_MAC_IN_ADDR_OFST 8 2579#define MC_CMD_SET_MAC_IN_ADDR_LEN 8 2580#define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8 2581#define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12 2582#define MC_CMD_SET_MAC_IN_REJECT_OFST 16 2583#define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0 2584#define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1 2585#define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1 2586#define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1 2587#define MC_CMD_SET_MAC_IN_FCNTL_OFST 20 2588/* enum: Flow control is off. */ 2589/* MC_CMD_FCNTL_OFF 0x0 */ 2590/* enum: Respond to flow control. */ 2591/* MC_CMD_FCNTL_RESPOND 0x1 */ 2592/* enum: Respond to and Issue flow control. */ 2593/* MC_CMD_FCNTL_BIDIR 0x2 */ 2594/* enum: Auto neg flow control. */ 2595#define MC_CMD_FCNTL_AUTO 0x3 2596 2597/* MC_CMD_SET_MAC_OUT msgresponse */ 2598#define MC_CMD_SET_MAC_OUT_LEN 0 2599 2600 2601/***********************************/ 2602/* MC_CMD_PHY_STATS 2603 * Get generic PHY statistics. This call returns the statistics for a generic 2604 * PHY in a sparse array (indexed by the enumerate). Each value is represented 2605 * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the 2606 * statistics may be read from the message response. If DMA_ADDR != 0, then the 2607 * statistics are dmad to that (page-aligned location). Locks required: None. 2608 * Returns: 0, ETIME 2609 */ 2610#define MC_CMD_PHY_STATS 0x2d 2611 2612/* MC_CMD_PHY_STATS_IN msgrequest */ 2613#define MC_CMD_PHY_STATS_IN_LEN 8 2614/* ??? */ 2615#define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0 2616#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8 2617#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0 2618#define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4 2619 2620/* MC_CMD_PHY_STATS_OUT_DMA msgresponse */ 2621#define MC_CMD_PHY_STATS_OUT_DMA_LEN 0 2622 2623/* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */ 2624#define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3) 2625#define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0 2626#define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4 2627#define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS 2628/* enum: OUI. */ 2629#define MC_CMD_OUI 0x0 2630/* enum: PMA-PMD Link Up. */ 2631#define MC_CMD_PMA_PMD_LINK_UP 0x1 2632/* enum: PMA-PMD RX Fault. */ 2633#define MC_CMD_PMA_PMD_RX_FAULT 0x2 2634/* enum: PMA-PMD TX Fault. */ 2635#define MC_CMD_PMA_PMD_TX_FAULT 0x3 2636/* enum: PMA-PMD Signal */ 2637#define MC_CMD_PMA_PMD_SIGNAL 0x4 2638/* enum: PMA-PMD SNR A. */ 2639#define MC_CMD_PMA_PMD_SNR_A 0x5 2640/* enum: PMA-PMD SNR B. */ 2641#define MC_CMD_PMA_PMD_SNR_B 0x6 2642/* enum: PMA-PMD SNR C. */ 2643#define MC_CMD_PMA_PMD_SNR_C 0x7 2644/* enum: PMA-PMD SNR D. */ 2645#define MC_CMD_PMA_PMD_SNR_D 0x8 2646/* enum: PCS Link Up. */ 2647#define MC_CMD_PCS_LINK_UP 0x9 2648/* enum: PCS RX Fault. */ 2649#define MC_CMD_PCS_RX_FAULT 0xa 2650/* enum: PCS TX Fault. */ 2651#define MC_CMD_PCS_TX_FAULT 0xb 2652/* enum: PCS BER. */ 2653#define MC_CMD_PCS_BER 0xc 2654/* enum: PCS Block Errors. */ 2655#define MC_CMD_PCS_BLOCK_ERRORS 0xd 2656/* enum: PhyXS Link Up. */ 2657#define MC_CMD_PHYXS_LINK_UP 0xe 2658/* enum: PhyXS RX Fault. */ 2659#define MC_CMD_PHYXS_RX_FAULT 0xf 2660/* enum: PhyXS TX Fault. */ 2661#define MC_CMD_PHYXS_TX_FAULT 0x10 2662/* enum: PhyXS Align. */ 2663#define MC_CMD_PHYXS_ALIGN 0x11 2664/* enum: PhyXS Sync. */ 2665#define MC_CMD_PHYXS_SYNC 0x12 2666/* enum: AN link-up. */ 2667#define MC_CMD_AN_LINK_UP 0x13 2668/* enum: AN Complete. */ 2669#define MC_CMD_AN_COMPLETE 0x14 2670/* enum: AN 10GBaseT Status. */ 2671#define MC_CMD_AN_10GBT_STATUS 0x15 2672/* enum: Clause 22 Link-Up. */ 2673#define MC_CMD_CL22_LINK_UP 0x16 2674/* enum: (Last entry) */ 2675#define MC_CMD_PHY_NSTATS 0x17 2676 2677 2678/***********************************/ 2679/* MC_CMD_MAC_STATS 2680 * Get generic MAC statistics. This call returns unified statistics maintained 2681 * by the MC as it switches between the GMAC and XMAC. The MC will write out 2682 * all supported stats. The driver should zero initialise the buffer to 2683 * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is 2684 * performed, and the statistics may be read from the message response. If 2685 * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location). 2686 * Locks required: None. Returns: 0, ETIME 2687 */ 2688#define MC_CMD_MAC_STATS 0x2e 2689 2690/* MC_CMD_MAC_STATS_IN msgrequest */ 2691#define MC_CMD_MAC_STATS_IN_LEN 16 2692/* ??? */ 2693#define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0 2694#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8 2695#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0 2696#define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4 2697#define MC_CMD_MAC_STATS_IN_CMD_OFST 8 2698#define MC_CMD_MAC_STATS_IN_DMA_LBN 0 2699#define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1 2700#define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1 2701#define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1 2702#define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2 2703#define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1 2704#define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3 2705#define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1 2706#define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4 2707#define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1 2708#define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5 2709#define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1 2710#define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16 2711#define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16 2712#define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12 2713 2714/* MC_CMD_MAC_STATS_OUT_DMA msgresponse */ 2715#define MC_CMD_MAC_STATS_OUT_DMA_LEN 0 2716 2717/* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */ 2718#define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) 2719#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0 2720#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8 2721#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0 2722#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4 2723#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS 2724#define MC_CMD_MAC_GENERATION_START 0x0 /* enum */ 2725#define MC_CMD_MAC_TX_PKTS 0x1 /* enum */ 2726#define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */ 2727#define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */ 2728#define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */ 2729#define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */ 2730#define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */ 2731#define MC_CMD_MAC_TX_BYTES 0x7 /* enum */ 2732#define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */ 2733#define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */ 2734#define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */ 2735#define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */ 2736#define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */ 2737#define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */ 2738#define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */ 2739#define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */ 2740#define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */ 2741#define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */ 2742#define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */ 2743#define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */ 2744#define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */ 2745#define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */ 2746#define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */ 2747#define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */ 2748#define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */ 2749#define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */ 2750#define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */ 2751#define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */ 2752#define MC_CMD_MAC_RX_PKTS 0x1c /* enum */ 2753#define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */ 2754#define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */ 2755#define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */ 2756#define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */ 2757#define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */ 2758#define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */ 2759#define MC_CMD_MAC_RX_BYTES 0x23 /* enum */ 2760#define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */ 2761#define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */ 2762#define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */ 2763#define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */ 2764#define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */ 2765#define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */ 2766#define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */ 2767#define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */ 2768#define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */ 2769#define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */ 2770#define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */ 2771#define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */ 2772#define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */ 2773#define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */ 2774#define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */ 2775#define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */ 2776#define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */ 2777#define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */ 2778#define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */ 2779#define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */ 2780#define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */ 2781#define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */ 2782#define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */ 2783#define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */ 2784/* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 2785 * capability only. 2786 */ 2787#define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c 2788/* enum: PM discard_bb_overflow counter. Valid for EF10 with 2789 * PM_AND_RXDP_COUNTERS capability only. 2790 */ 2791#define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d 2792/* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 2793 * capability only. 2794 */ 2795#define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e 2796/* enum: PM discard_vfifo_full counter. Valid for EF10 with 2797 * PM_AND_RXDP_COUNTERS capability only. 2798 */ 2799#define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f 2800/* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 2801 * capability only. 2802 */ 2803#define MC_CMD_MAC_PM_TRUNC_QBB 0x40 2804/* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 2805 * capability only. 2806 */ 2807#define MC_CMD_MAC_PM_DISCARD_QBB 0x41 2808/* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 2809 * capability only. 2810 */ 2811#define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42 2812/* enum: RXDP counter: Number of packets dropped due to the queue being 2813 * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 2814 */ 2815#define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43 2816/* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10 2817 * with PM_AND_RXDP_COUNTERS capability only. 2818 */ 2819#define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45 2820/* enum: RXDP counter: Number of non-host packets. Valid for EF10 with 2821 * PM_AND_RXDP_COUNTERS capability only. 2822 */ 2823#define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46 2824/* enum: RXDP counter: Number of times an emergency descriptor fetch was 2825 * performed. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 2826 */ 2827#define MC_CMD_MAC_RXDP_EMERGENCY_FETCH_CONDITIONS 0x47 2828/* enum: RXDP counter: Number of times the DPCPU waited for an existing 2829 * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 2830 */ 2831#define MC_CMD_MAC_RXDP_EMERGENCY_WAIT_CONDITIONS 0x48 2832/* enum: Start of GMAC stats buffer space, for Siena only. */ 2833#define MC_CMD_GMAC_DMABUF_START 0x40 2834/* enum: End of GMAC stats buffer space, for Siena only. */ 2835#define MC_CMD_GMAC_DMABUF_END 0x5f 2836#define MC_CMD_MAC_GENERATION_END 0x60 /* enum */ 2837#define MC_CMD_MAC_NSTATS 0x61 /* enum */ 2838 2839 2840/***********************************/ 2841/* MC_CMD_SRIOV 2842 * to be documented 2843 */ 2844#define MC_CMD_SRIOV 0x30 2845 2846/* MC_CMD_SRIOV_IN msgrequest */ 2847#define MC_CMD_SRIOV_IN_LEN 12 2848#define MC_CMD_SRIOV_IN_ENABLE_OFST 0 2849#define MC_CMD_SRIOV_IN_VI_BASE_OFST 4 2850#define MC_CMD_SRIOV_IN_VF_COUNT_OFST 8 2851 2852/* MC_CMD_SRIOV_OUT msgresponse */ 2853#define MC_CMD_SRIOV_OUT_LEN 8 2854#define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0 2855#define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4 2856 2857/* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */ 2858#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32 2859/* this is only used for the first record */ 2860#define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0 2861#define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0 2862#define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32 2863#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4 2864#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32 2865#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32 2866#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8 2867#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8 2868#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8 2869#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12 2870#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64 2871#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64 2872#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16 2873#define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */ 2874#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128 2875#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32 2876#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20 2877#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8 2878#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20 2879#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24 2880#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160 2881#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64 2882#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28 2883#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224 2884#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32 2885 2886 2887/***********************************/ 2888/* MC_CMD_MEMCPY 2889 * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data 2890 * embedded directly in the command. 2891 * 2892 * A common pattern is for a client to use generation counts to signal a dma 2893 * update of a datastructure. To facilitate this, this MCDI operation can 2894 * contain multiple requests which are executed in strict order. Requests take 2895 * the form of duplicating the entire MCDI request continuously (including the 2896 * requests record, which is ignored in all but the first structure) 2897 * 2898 * The source data can either come from a DMA from the host, or it can be 2899 * embedded within the request directly, thereby eliminating a DMA read. To 2900 * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and 2901 * ADDR_LO=offset, and inserts the data at %offset from the start of the 2902 * payload. It's the callers responsibility to ensure that the embedded data 2903 * doesn't overlap the records. 2904 * 2905 * Returns: 0, EINVAL (invalid RID) 2906 */ 2907#define MC_CMD_MEMCPY 0x31 2908 2909/* MC_CMD_MEMCPY_IN msgrequest */ 2910#define MC_CMD_MEMCPY_IN_LENMIN 32 2911#define MC_CMD_MEMCPY_IN_LENMAX 224 2912#define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num)) 2913/* see MC_CMD_MEMCPY_RECORD_TYPEDEF */ 2914#define MC_CMD_MEMCPY_IN_RECORD_OFST 0 2915#define MC_CMD_MEMCPY_IN_RECORD_LEN 32 2916#define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1 2917#define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7 2918 2919/* MC_CMD_MEMCPY_OUT msgresponse */ 2920#define MC_CMD_MEMCPY_OUT_LEN 0 2921 2922 2923/***********************************/ 2924/* MC_CMD_WOL_FILTER_SET 2925 * Set a WoL filter. 2926 */ 2927#define MC_CMD_WOL_FILTER_SET 0x32 2928 2929/* MC_CMD_WOL_FILTER_SET_IN msgrequest */ 2930#define MC_CMD_WOL_FILTER_SET_IN_LEN 192 2931#define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 2932#define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */ 2933#define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */ 2934/* A type value of 1 is unused. */ 2935#define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 2936/* enum: Magic */ 2937#define MC_CMD_WOL_TYPE_MAGIC 0x0 2938/* enum: MS Windows Magic */ 2939#define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2 2940/* enum: IPv4 Syn */ 2941#define MC_CMD_WOL_TYPE_IPV4_SYN 0x3 2942/* enum: IPv6 Syn */ 2943#define MC_CMD_WOL_TYPE_IPV6_SYN 0x4 2944/* enum: Bitmap */ 2945#define MC_CMD_WOL_TYPE_BITMAP 0x5 2946/* enum: Link */ 2947#define MC_CMD_WOL_TYPE_LINK 0x6 2948/* enum: (Above this for future use) */ 2949#define MC_CMD_WOL_TYPE_MAX 0x7 2950#define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8 2951#define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4 2952#define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46 2953 2954/* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */ 2955#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16 2956/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 2957/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 2958#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8 2959#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8 2960#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8 2961#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12 2962 2963/* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */ 2964#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20 2965/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 2966/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 2967#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8 2968#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12 2969#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16 2970#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2 2971#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18 2972#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2 2973 2974/* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */ 2975#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44 2976/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 2977/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 2978#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8 2979#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16 2980#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24 2981#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16 2982#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40 2983#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2 2984#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42 2985#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2 2986 2987/* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */ 2988#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187 2989/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 2990/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 2991#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8 2992#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48 2993#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56 2994#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128 2995#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184 2996#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1 2997#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185 2998#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1 2999#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186 3000#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1 3001 3002/* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */ 3003#define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12 3004/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 3005/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 3006#define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8 3007#define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0 3008#define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1 3009#define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1 3010#define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1 3011 3012/* MC_CMD_WOL_FILTER_SET_OUT msgresponse */ 3013#define MC_CMD_WOL_FILTER_SET_OUT_LEN 4 3014#define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0 3015 3016 3017/***********************************/ 3018/* MC_CMD_WOL_FILTER_REMOVE 3019 * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS 3020 */ 3021#define MC_CMD_WOL_FILTER_REMOVE 0x33 3022 3023/* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */ 3024#define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4 3025#define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0 3026 3027/* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */ 3028#define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0 3029 3030 3031/***********************************/ 3032/* MC_CMD_WOL_FILTER_RESET 3033 * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0, 3034 * ENOSYS 3035 */ 3036#define MC_CMD_WOL_FILTER_RESET 0x34 3037 3038/* MC_CMD_WOL_FILTER_RESET_IN msgrequest */ 3039#define MC_CMD_WOL_FILTER_RESET_IN_LEN 4 3040#define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0 3041#define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */ 3042#define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */ 3043 3044/* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */ 3045#define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0 3046 3047 3048/***********************************/ 3049/* MC_CMD_SET_MCAST_HASH 3050 * Set the MCAST hash value without otherwise reconfiguring the MAC 3051 */ 3052#define MC_CMD_SET_MCAST_HASH 0x35 3053 3054/* MC_CMD_SET_MCAST_HASH_IN msgrequest */ 3055#define MC_CMD_SET_MCAST_HASH_IN_LEN 32 3056#define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0 3057#define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16 3058#define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16 3059#define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16 3060 3061/* MC_CMD_SET_MCAST_HASH_OUT msgresponse */ 3062#define MC_CMD_SET_MCAST_HASH_OUT_LEN 0 3063 3064 3065/***********************************/ 3066/* MC_CMD_NVRAM_TYPES 3067 * Return bitfield indicating available types of virtual NVRAM partitions. 3068 * Locks required: none. Returns: 0 3069 */ 3070#define MC_CMD_NVRAM_TYPES 0x36 3071 3072/* MC_CMD_NVRAM_TYPES_IN msgrequest */ 3073#define MC_CMD_NVRAM_TYPES_IN_LEN 0 3074 3075/* MC_CMD_NVRAM_TYPES_OUT msgresponse */ 3076#define MC_CMD_NVRAM_TYPES_OUT_LEN 4 3077/* Bit mask of supported types. */ 3078#define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0 3079/* enum: Disabled callisto. */ 3080#define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0 3081/* enum: MC firmware. */ 3082#define MC_CMD_NVRAM_TYPE_MC_FW 0x1 3083/* enum: MC backup firmware. */ 3084#define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2 3085/* enum: Static configuration Port0. */ 3086#define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3 3087/* enum: Static configuration Port1. */ 3088#define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4 3089/* enum: Dynamic configuration Port0. */ 3090#define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5 3091/* enum: Dynamic configuration Port1. */ 3092#define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6 3093/* enum: Expansion Rom. */ 3094#define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7 3095/* enum: Expansion Rom Configuration Port0. */ 3096#define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8 3097/* enum: Expansion Rom Configuration Port1. */ 3098#define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9 3099/* enum: Phy Configuration Port0. */ 3100#define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa 3101/* enum: Phy Configuration Port1. */ 3102#define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb 3103/* enum: Log. */ 3104#define MC_CMD_NVRAM_TYPE_LOG 0xc 3105/* enum: FPGA image. */ 3106#define MC_CMD_NVRAM_TYPE_FPGA 0xd 3107/* enum: FPGA backup image */ 3108#define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe 3109/* enum: FC firmware. */ 3110#define MC_CMD_NVRAM_TYPE_FC_FW 0xf 3111/* enum: FC backup firmware. */ 3112#define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10 3113/* enum: CPLD image. */ 3114#define MC_CMD_NVRAM_TYPE_CPLD 0x11 3115/* enum: Licensing information. */ 3116#define MC_CMD_NVRAM_TYPE_LICENSE 0x12 3117/* enum: FC Log. */ 3118#define MC_CMD_NVRAM_TYPE_FC_LOG 0x13 3119 3120 3121/***********************************/ 3122/* MC_CMD_NVRAM_INFO 3123 * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0, 3124 * EINVAL (bad type). 3125 */ 3126#define MC_CMD_NVRAM_INFO 0x37 3127 3128/* MC_CMD_NVRAM_INFO_IN msgrequest */ 3129#define MC_CMD_NVRAM_INFO_IN_LEN 4 3130#define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0 3131/* Enum values, see field(s): */ 3132/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3133 3134/* MC_CMD_NVRAM_INFO_OUT msgresponse */ 3135#define MC_CMD_NVRAM_INFO_OUT_LEN 24 3136#define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0 3137/* Enum values, see field(s): */ 3138/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3139#define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4 3140#define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8 3141#define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12 3142#define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0 3143#define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1 3144#define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1 3145#define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1 3146#define MC_CMD_NVRAM_INFO_OUT_A_B_LBN 7 3147#define MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1 3148#define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16 3149#define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20 3150 3151 3152/***********************************/ 3153/* MC_CMD_NVRAM_UPDATE_START 3154 * Start a group of update operations on a virtual NVRAM partition. Locks 3155 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if 3156 * PHY_LOCK required and not held). 3157 */ 3158#define MC_CMD_NVRAM_UPDATE_START 0x38 3159 3160/* MC_CMD_NVRAM_UPDATE_START_IN msgrequest */ 3161#define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4 3162#define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0 3163/* Enum values, see field(s): */ 3164/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3165 3166/* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */ 3167#define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0 3168 3169 3170/***********************************/ 3171/* MC_CMD_NVRAM_READ 3172 * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if 3173 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 3174 * PHY_LOCK required and not held) 3175 */ 3176#define MC_CMD_NVRAM_READ 0x39 3177 3178/* MC_CMD_NVRAM_READ_IN msgrequest */ 3179#define MC_CMD_NVRAM_READ_IN_LEN 12 3180#define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0 3181/* Enum values, see field(s): */ 3182/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3183#define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4 3184/* amount to read in bytes */ 3185#define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8 3186 3187/* MC_CMD_NVRAM_READ_OUT msgresponse */ 3188#define MC_CMD_NVRAM_READ_OUT_LENMIN 1 3189#define MC_CMD_NVRAM_READ_OUT_LENMAX 252 3190#define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num)) 3191#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0 3192#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1 3193#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1 3194#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252 3195 3196 3197/***********************************/ 3198/* MC_CMD_NVRAM_WRITE 3199 * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if 3200 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 3201 * PHY_LOCK required and not held) 3202 */ 3203#define MC_CMD_NVRAM_WRITE 0x3a 3204 3205/* MC_CMD_NVRAM_WRITE_IN msgrequest */ 3206#define MC_CMD_NVRAM_WRITE_IN_LENMIN 13 3207#define MC_CMD_NVRAM_WRITE_IN_LENMAX 252 3208#define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num)) 3209#define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0 3210/* Enum values, see field(s): */ 3211/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3212#define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4 3213#define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8 3214#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12 3215#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1 3216#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1 3217#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240 3218 3219/* MC_CMD_NVRAM_WRITE_OUT msgresponse */ 3220#define MC_CMD_NVRAM_WRITE_OUT_LEN 0 3221 3222 3223/***********************************/ 3224/* MC_CMD_NVRAM_ERASE 3225 * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if 3226 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 3227 * PHY_LOCK required and not held) 3228 */ 3229#define MC_CMD_NVRAM_ERASE 0x3b 3230 3231/* MC_CMD_NVRAM_ERASE_IN msgrequest */ 3232#define MC_CMD_NVRAM_ERASE_IN_LEN 12 3233#define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0 3234/* Enum values, see field(s): */ 3235/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3236#define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4 3237#define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8 3238 3239/* MC_CMD_NVRAM_ERASE_OUT msgresponse */ 3240#define MC_CMD_NVRAM_ERASE_OUT_LEN 0 3241 3242 3243/***********************************/ 3244/* MC_CMD_NVRAM_UPDATE_FINISH 3245 * Finish a group of update operations on a virtual NVRAM partition. Locks 3246 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad 3247 * type/offset/length), EACCES (if PHY_LOCK required and not held) 3248 */ 3249#define MC_CMD_NVRAM_UPDATE_FINISH 0x3c 3250 3251/* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest */ 3252#define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8 3253#define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0 3254/* Enum values, see field(s): */ 3255/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3256#define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4 3257 3258/* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse */ 3259#define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0 3260 3261 3262/***********************************/ 3263/* MC_CMD_REBOOT 3264 * Reboot the MC. 3265 * 3266 * The AFTER_ASSERTION flag is intended to be used when the driver notices an 3267 * assertion failure (at which point it is expected to perform a complete tear 3268 * down and reinitialise), to allow both ports to reset the MC once in an 3269 * atomic fashion. 3270 * 3271 * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1, 3272 * which means that they will automatically reboot out of the assertion 3273 * handler, so this is in practise an optional operation. It is still 3274 * recommended that drivers execute this to support custom firmwares with 3275 * REBOOT_ON_ASSERT=0. 3276 * 3277 * Locks required: NONE Returns: Nothing. You get back a response with ERR=1, 3278 * DATALEN=0 3279 */ 3280#define MC_CMD_REBOOT 0x3d 3281 3282/* MC_CMD_REBOOT_IN msgrequest */ 3283#define MC_CMD_REBOOT_IN_LEN 4 3284#define MC_CMD_REBOOT_IN_FLAGS_OFST 0 3285#define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */ 3286 3287/* MC_CMD_REBOOT_OUT msgresponse */ 3288#define MC_CMD_REBOOT_OUT_LEN 0 3289 3290 3291/***********************************/ 3292/* MC_CMD_SCHEDINFO 3293 * Request scheduler info. Locks required: NONE. Returns: An array of 3294 * (timeslice,maximum overrun), one for each thread, in ascending order of 3295 * thread address. 3296 */ 3297#define MC_CMD_SCHEDINFO 0x3e 3298 3299/* MC_CMD_SCHEDINFO_IN msgrequest */ 3300#define MC_CMD_SCHEDINFO_IN_LEN 0 3301 3302/* MC_CMD_SCHEDINFO_OUT msgresponse */ 3303#define MC_CMD_SCHEDINFO_OUT_LENMIN 4 3304#define MC_CMD_SCHEDINFO_OUT_LENMAX 252 3305#define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num)) 3306#define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0 3307#define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4 3308#define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1 3309#define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63 3310 3311 3312/***********************************/ 3313/* MC_CMD_REBOOT_MODE 3314 * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot 3315 * mode to the specified value. Returns the old mode. 3316 */ 3317#define MC_CMD_REBOOT_MODE 0x3f 3318 3319/* MC_CMD_REBOOT_MODE_IN msgrequest */ 3320#define MC_CMD_REBOOT_MODE_IN_LEN 4 3321#define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0 3322/* enum: Normal. */ 3323#define MC_CMD_REBOOT_MODE_NORMAL 0x0 3324/* enum: Power-on Reset. */ 3325#define MC_CMD_REBOOT_MODE_POR 0x2 3326/* enum: Snapper. */ 3327#define MC_CMD_REBOOT_MODE_SNAPPER 0x3 3328/* enum: snapper fake POR */ 3329#define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4 3330#define MC_CMD_REBOOT_MODE_IN_FAKE_LBN 7 3331#define MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1 3332 3333/* MC_CMD_REBOOT_MODE_OUT msgresponse */ 3334#define MC_CMD_REBOOT_MODE_OUT_LEN 4 3335#define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0 3336 3337 3338/***********************************/ 3339/* MC_CMD_SENSOR_INFO 3340 * Returns information about every available sensor. 3341 * 3342 * Each sensor has a single (16bit) value, and a corresponding state. The 3343 * mapping between value and state is nominally determined by the MC, but may 3344 * be implemented using up to 2 ranges per sensor. 3345 * 3346 * This call returns a mask (32bit) of the sensors that are supported by this 3347 * platform, then an array of sensor information structures, in order of sensor 3348 * type (but without gaps for unimplemented sensors). Each structure defines 3349 * the ranges for the corresponding sensor. An unused range is indicated by 3350 * equal limit values. If one range is used, a value outside that range results 3351 * in STATE_FATAL. If two ranges are used, a value outside the second range 3352 * results in STATE_FATAL while a value outside the first and inside the second 3353 * range results in STATE_WARNING. 3354 * 3355 * Sensor masks and sensor information arrays are organised into pages. For 3356 * backward compatibility, older host software can only use sensors in page 0. 3357 * Bit 32 in the sensor mask was previously unused, and is no reserved for use 3358 * as the next page flag. 3359 * 3360 * If the request does not contain a PAGE value then firmware will only return 3361 * page 0 of sensor information, with bit 31 in the sensor mask cleared. 3362 * 3363 * If the request contains a PAGE value then firmware responds with the sensor 3364 * mask and sensor information array for that page of sensors. In this case bit 3365 * 31 in the mask is set if another page exists. 3366 * 3367 * Locks required: None Returns: 0 3368 */ 3369#define MC_CMD_SENSOR_INFO 0x41 3370 3371/* MC_CMD_SENSOR_INFO_IN msgrequest */ 3372#define MC_CMD_SENSOR_INFO_IN_LEN 0 3373 3374/* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */ 3375#define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4 3376/* Which page of sensors to report. 3377 * 3378 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit). 3379 * 3380 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc. 3381 */ 3382#define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0 3383 3384/* MC_CMD_SENSOR_INFO_OUT msgresponse */ 3385#define MC_CMD_SENSOR_INFO_OUT_LENMIN 4 3386#define MC_CMD_SENSOR_INFO_OUT_LENMAX 252 3387#define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num)) 3388#define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0 3389/* enum: Controller temperature: degC */ 3390#define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0 3391/* enum: Phy common temperature: degC */ 3392#define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1 3393/* enum: Controller cooling: bool */ 3394#define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2 3395/* enum: Phy 0 temperature: degC */ 3396#define MC_CMD_SENSOR_PHY0_TEMP 0x3 3397/* enum: Phy 0 cooling: bool */ 3398#define MC_CMD_SENSOR_PHY0_COOLING 0x4 3399/* enum: Phy 1 temperature: degC */ 3400#define MC_CMD_SENSOR_PHY1_TEMP 0x5 3401/* enum: Phy 1 cooling: bool */ 3402#define MC_CMD_SENSOR_PHY1_COOLING 0x6 3403/* enum: 1.0v power: mV */ 3404#define MC_CMD_SENSOR_IN_1V0 0x7 3405/* enum: 1.2v power: mV */ 3406#define MC_CMD_SENSOR_IN_1V2 0x8 3407/* enum: 1.8v power: mV */ 3408#define MC_CMD_SENSOR_IN_1V8 0x9 3409/* enum: 2.5v power: mV */ 3410#define MC_CMD_SENSOR_IN_2V5 0xa 3411/* enum: 3.3v power: mV */ 3412#define MC_CMD_SENSOR_IN_3V3 0xb 3413/* enum: 12v power: mV */ 3414#define MC_CMD_SENSOR_IN_12V0 0xc 3415/* enum: 1.2v analogue power: mV */ 3416#define MC_CMD_SENSOR_IN_1V2A 0xd 3417/* enum: reference voltage: mV */ 3418#define MC_CMD_SENSOR_IN_VREF 0xe 3419/* enum: AOE FPGA power: mV */ 3420#define MC_CMD_SENSOR_OUT_VAOE 0xf 3421/* enum: AOE FPGA temperature: degC */ 3422#define MC_CMD_SENSOR_AOE_TEMP 0x10 3423/* enum: AOE FPGA PSU temperature: degC */ 3424#define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11 3425/* enum: AOE PSU temperature: degC */ 3426#define MC_CMD_SENSOR_PSU_TEMP 0x12 3427/* enum: Fan 0 speed: RPM */ 3428#define MC_CMD_SENSOR_FAN_0 0x13 3429/* enum: Fan 1 speed: RPM */ 3430#define MC_CMD_SENSOR_FAN_1 0x14 3431/* enum: Fan 2 speed: RPM */ 3432#define MC_CMD_SENSOR_FAN_2 0x15 3433/* enum: Fan 3 speed: RPM */ 3434#define MC_CMD_SENSOR_FAN_3 0x16 3435/* enum: Fan 4 speed: RPM */ 3436#define MC_CMD_SENSOR_FAN_4 0x17 3437/* enum: AOE FPGA input power: mV */ 3438#define MC_CMD_SENSOR_IN_VAOE 0x18 3439/* enum: AOE FPGA current: mA */ 3440#define MC_CMD_SENSOR_OUT_IAOE 0x19 3441/* enum: AOE FPGA input current: mA */ 3442#define MC_CMD_SENSOR_IN_IAOE 0x1a 3443/* enum: NIC power consumption: W */ 3444#define MC_CMD_SENSOR_NIC_POWER 0x1b 3445/* enum: 0.9v power voltage: mV */ 3446#define MC_CMD_SENSOR_IN_0V9 0x1c 3447/* enum: 0.9v power current: mA */ 3448#define MC_CMD_SENSOR_IN_I0V9 0x1d 3449/* enum: 1.2v power current: mA */ 3450#define MC_CMD_SENSOR_IN_I1V2 0x1e 3451/* enum: Not a sensor: reserved for the next page flag */ 3452#define MC_CMD_SENSOR_PAGE0_NEXT 0x1f 3453/* enum: 0.9v power voltage (at ADC): mV */ 3454#define MC_CMD_SENSOR_IN_0V9_ADC 0x20 3455/* enum: Controller temperature 2: degC */ 3456#define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21 3457/* enum: Voltage regulator internal temperature: degC */ 3458#define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22 3459/* enum: 0.9V voltage regulator temperature: degC */ 3460#define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23 3461/* enum: 1.2V voltage regulator temperature: degC */ 3462#define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24 3463/* enum: controller internal temperature sensor voltage (internal ADC): mV */ 3464#define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25 3465/* enum: controller internal temperature (internal ADC): degC */ 3466#define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26 3467/* enum: controller internal temperature sensor voltage (external ADC): mV */ 3468#define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27 3469/* enum: controller internal temperature (external ADC): degC */ 3470#define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28 3471/* enum: ambient temperature: degC */ 3472#define MC_CMD_SENSOR_AMBIENT_TEMP 0x29 3473/* enum: air flow: bool */ 3474#define MC_CMD_SENSOR_AIRFLOW 0x2a 3475/* enum: voltage between VSS08D and VSS08D at CSR: mV */ 3476#define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b 3477/* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */ 3478#define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c 3479/* enum: Hotpoint temperature: degC */ 3480#define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d 3481/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ 3482#define MC_CMD_SENSOR_ENTRY_OFST 4 3483#define MC_CMD_SENSOR_ENTRY_LEN 8 3484#define MC_CMD_SENSOR_ENTRY_LO_OFST 4 3485#define MC_CMD_SENSOR_ENTRY_HI_OFST 8 3486#define MC_CMD_SENSOR_ENTRY_MINNUM 0 3487#define MC_CMD_SENSOR_ENTRY_MAXNUM 31 3488 3489/* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */ 3490#define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4 3491#define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252 3492#define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num)) 3493#define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0 3494/* Enum values, see field(s): */ 3495/* MC_CMD_SENSOR_INFO_OUT */ 3496#define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31 3497#define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1 3498/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ 3499/* MC_CMD_SENSOR_ENTRY_OFST 4 */ 3500/* MC_CMD_SENSOR_ENTRY_LEN 8 */ 3501/* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */ 3502/* MC_CMD_SENSOR_ENTRY_HI_OFST 8 */ 3503/* MC_CMD_SENSOR_ENTRY_MINNUM 0 */ 3504/* MC_CMD_SENSOR_ENTRY_MAXNUM 31 */ 3505 3506/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */ 3507#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8 3508#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0 3509#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2 3510#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0 3511#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16 3512#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2 3513#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2 3514#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16 3515#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16 3516#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4 3517#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2 3518#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32 3519#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16 3520#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6 3521#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2 3522#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48 3523#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16 3524 3525 3526/***********************************/ 3527/* MC_CMD_READ_SENSORS 3528 * Returns the current reading from each sensor. DMAs an array of sensor 3529 * readings, in order of sensor type (but without gaps for unimplemented 3530 * sensors), into host memory. Each array element is a 3531 * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword. 3532 * 3533 * If the request does not contain the LENGTH field then only sensors 0 to 30 3534 * are reported, to avoid DMA buffer overflow in older host software. If the 3535 * sensor reading require more space than the LENGTH allows, then return 3536 * EINVAL. 3537 * 3538 * The MC will send a SENSOREVT event every time any sensor changes state. The 3539 * driver is responsible for ensuring that it doesn't miss any events. The 3540 * board will function normally if all sensors are in STATE_OK or 3541 * STATE_WARNING. Otherwise the board should not be expected to function. 3542 */ 3543#define MC_CMD_READ_SENSORS 0x42 3544 3545/* MC_CMD_READ_SENSORS_IN msgrequest */ 3546#define MC_CMD_READ_SENSORS_IN_LEN 8 3547/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */ 3548#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0 3549#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8 3550#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0 3551#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4 3552 3553/* MC_CMD_READ_SENSORS_EXT_IN msgrequest */ 3554#define MC_CMD_READ_SENSORS_EXT_IN_LEN 12 3555/* DMA address of host buffer for sensor readings */ 3556#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0 3557#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8 3558#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0 3559#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4 3560/* Size in bytes of host buffer. */ 3561#define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8 3562 3563/* MC_CMD_READ_SENSORS_OUT msgresponse */ 3564#define MC_CMD_READ_SENSORS_OUT_LEN 0 3565 3566/* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */ 3567#define MC_CMD_READ_SENSORS_EXT_OUT_LEN 0 3568 3569/* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */ 3570#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4 3571#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0 3572#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2 3573#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0 3574#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16 3575#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2 3576#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1 3577/* enum: Ok. */ 3578#define MC_CMD_SENSOR_STATE_OK 0x0 3579/* enum: Breached warning threshold. */ 3580#define MC_CMD_SENSOR_STATE_WARNING 0x1 3581/* enum: Breached fatal threshold. */ 3582#define MC_CMD_SENSOR_STATE_FATAL 0x2 3583/* enum: Fault with sensor. */ 3584#define MC_CMD_SENSOR_STATE_BROKEN 0x3 3585/* enum: Sensor is working but does not currently have a reading. */ 3586#define MC_CMD_SENSOR_STATE_NO_READING 0x4 3587#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16 3588#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8 3589#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 3 3590#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1 3591/* Enum values, see field(s): */ 3592/* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 3593#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 24 3594#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 8 3595 3596 3597/***********************************/ 3598/* MC_CMD_GET_PHY_STATE 3599 * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot 3600 * (e.g. due to missing or corrupted firmware). Locks required: None. Return 3601 * code: 0 3602 */ 3603#define MC_CMD_GET_PHY_STATE 0x43 3604 3605/* MC_CMD_GET_PHY_STATE_IN msgrequest */ 3606#define MC_CMD_GET_PHY_STATE_IN_LEN 0 3607 3608/* MC_CMD_GET_PHY_STATE_OUT msgresponse */ 3609#define MC_CMD_GET_PHY_STATE_OUT_LEN 4 3610#define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0 3611/* enum: Ok. */ 3612#define MC_CMD_PHY_STATE_OK 0x1 3613/* enum: Faulty. */ 3614#define MC_CMD_PHY_STATE_ZOMBIE 0x2 3615 3616 3617/***********************************/ 3618/* MC_CMD_SETUP_8021QBB 3619 * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to 3620 * disable 802.Qbb for a given priority. 3621 */ 3622#define MC_CMD_SETUP_8021QBB 0x44 3623 3624/* MC_CMD_SETUP_8021QBB_IN msgrequest */ 3625#define MC_CMD_SETUP_8021QBB_IN_LEN 32 3626#define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0 3627#define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32 3628 3629/* MC_CMD_SETUP_8021QBB_OUT msgresponse */ 3630#define MC_CMD_SETUP_8021QBB_OUT_LEN 0 3631 3632 3633/***********************************/ 3634/* MC_CMD_WOL_FILTER_GET 3635 * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS 3636 */ 3637#define MC_CMD_WOL_FILTER_GET 0x45 3638 3639/* MC_CMD_WOL_FILTER_GET_IN msgrequest */ 3640#define MC_CMD_WOL_FILTER_GET_IN_LEN 0 3641 3642/* MC_CMD_WOL_FILTER_GET_OUT msgresponse */ 3643#define MC_CMD_WOL_FILTER_GET_OUT_LEN 4 3644#define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0 3645 3646 3647/***********************************/ 3648/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD 3649 * Add a protocol offload to NIC for lights-out state. Locks required: None. 3650 * Returns: 0, ENOSYS 3651 */ 3652#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46 3653 3654/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */ 3655#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8 3656#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252 3657#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num)) 3658#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 3659#define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */ 3660#define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */ 3661#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4 3662#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4 3663#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1 3664#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62 3665 3666/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */ 3667#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14 3668/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 3669#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4 3670#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6 3671#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10 3672 3673/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */ 3674#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42 3675/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 3676#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4 3677#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6 3678#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10 3679#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16 3680#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26 3681#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16 3682 3683/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 3684#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4 3685#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0 3686 3687 3688/***********************************/ 3689/* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 3690 * Remove a protocol offload from NIC for lights-out state. Locks required: 3691 * None. Returns: 0, ENOSYS 3692 */ 3693#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47 3694 3695/* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */ 3696#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8 3697#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 3698#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4 3699 3700/* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 3701#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0 3702 3703 3704/***********************************/ 3705/* MC_CMD_MAC_RESET_RESTORE 3706 * Restore MAC after block reset. Locks required: None. Returns: 0. 3707 */ 3708#define MC_CMD_MAC_RESET_RESTORE 0x48 3709 3710/* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */ 3711#define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0 3712 3713/* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */ 3714#define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0 3715 3716 3717/***********************************/ 3718/* MC_CMD_TESTASSERT 3719 * Deliberately trigger an assert-detonation in the firmware for testing 3720 * purposes (i.e. to allow tests that the driver copes gracefully). Locks 3721 * required: None Returns: 0 3722 */ 3723#define MC_CMD_TESTASSERT 0x49 3724 3725/* MC_CMD_TESTASSERT_IN msgrequest */ 3726#define MC_CMD_TESTASSERT_IN_LEN 0 3727 3728/* MC_CMD_TESTASSERT_OUT msgresponse */ 3729#define MC_CMD_TESTASSERT_OUT_LEN 0 3730 3731 3732/***********************************/ 3733/* MC_CMD_WORKAROUND 3734 * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't 3735 * understand the given workaround number - which should not be treated as a 3736 * hard error by client code. This op does not imply any semantics about each 3737 * workaround, that's between the driver and the mcfw on a per-workaround 3738 * basis. Locks required: None. Returns: 0, EINVAL . 3739 */ 3740#define MC_CMD_WORKAROUND 0x4a 3741 3742/* MC_CMD_WORKAROUND_IN msgrequest */ 3743#define MC_CMD_WORKAROUND_IN_LEN 8 3744#define MC_CMD_WORKAROUND_IN_TYPE_OFST 0 3745/* enum: Bug 17230 work around. */ 3746#define MC_CMD_WORKAROUND_BUG17230 0x1 3747/* enum: Bug 35388 work around (unsafe EVQ writes). */ 3748#define MC_CMD_WORKAROUND_BUG35388 0x2 3749/* enum: Bug35017 workaround (A64 tables must be identity map) */ 3750#define MC_CMD_WORKAROUND_BUG35017 0x3 3751#define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4 3752 3753/* MC_CMD_WORKAROUND_OUT msgresponse */ 3754#define MC_CMD_WORKAROUND_OUT_LEN 0 3755 3756 3757/***********************************/ 3758/* MC_CMD_GET_PHY_MEDIA_INFO 3759 * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for 3760 * SFP+ PHYs). The 'media type' can be found via GET_PHY_CFG 3761 * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid 'page number' input values, and the 3762 * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 1 3763 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80. 3764 * Anything else: currently undefined. Locks required: None. Return code: 0. 3765 */ 3766#define MC_CMD_GET_PHY_MEDIA_INFO 0x4b 3767 3768/* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */ 3769#define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4 3770#define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0 3771 3772/* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */ 3773#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5 3774#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252 3775#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num)) 3776/* in bytes */ 3777#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0 3778#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4 3779#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1 3780#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1 3781#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248 3782 3783 3784/***********************************/ 3785/* MC_CMD_NVRAM_TEST 3786 * Test a particular NVRAM partition for valid contents (where "valid" depends 3787 * on the type of partition). 3788 */ 3789#define MC_CMD_NVRAM_TEST 0x4c 3790 3791/* MC_CMD_NVRAM_TEST_IN msgrequest */ 3792#define MC_CMD_NVRAM_TEST_IN_LEN 4 3793#define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0 3794/* Enum values, see field(s): */ 3795/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 3796 3797/* MC_CMD_NVRAM_TEST_OUT msgresponse */ 3798#define MC_CMD_NVRAM_TEST_OUT_LEN 4 3799#define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0 3800/* enum: Passed. */ 3801#define MC_CMD_NVRAM_TEST_PASS 0x0 3802/* enum: Failed. */ 3803#define MC_CMD_NVRAM_TEST_FAIL 0x1 3804/* enum: Not supported. */ 3805#define MC_CMD_NVRAM_TEST_NOTSUPP 0x2 3806 3807 3808/***********************************/ 3809/* MC_CMD_MRSFP_TWEAK 3810 * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds. 3811 * I2C I/O expander bits are always read; if equaliser parameters are supplied, 3812 * they are configured first. Locks required: None. Return code: 0, EINVAL. 3813 */ 3814#define MC_CMD_MRSFP_TWEAK 0x4d 3815 3816/* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */ 3817#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16 3818/* 0-6 low->high de-emph. */ 3819#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0 3820/* 0-8 low->high ref.V */ 3821#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4 3822/* 0-8 0-8 low->high boost */ 3823#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8 3824/* 0-8 low->high ref.V */ 3825#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12 3826 3827/* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */ 3828#define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0 3829 3830/* MC_CMD_MRSFP_TWEAK_OUT msgresponse */ 3831#define MC_CMD_MRSFP_TWEAK_OUT_LEN 12 3832/* input bits */ 3833#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0 3834/* output bits */ 3835#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4 3836/* direction */ 3837#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8 3838/* enum: Out. */ 3839#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0 3840/* enum: In. */ 3841#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1 3842 3843 3844/***********************************/ 3845/* MC_CMD_SENSOR_SET_LIMS 3846 * Adjusts the sensor limits. This is a warranty-voiding operation. Returns: 3847 * ENOENT if the sensor specified does not exist, EINVAL if the limits are out 3848 * of range. 3849 */ 3850#define MC_CMD_SENSOR_SET_LIMS 0x4e 3851 3852/* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */ 3853#define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20 3854#define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0 3855/* Enum values, see field(s): */ 3856/* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 3857/* interpretation is is sensor-specific. */ 3858#define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4 3859/* interpretation is is sensor-specific. */ 3860#define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8 3861/* interpretation is is sensor-specific. */ 3862#define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12 3863/* interpretation is is sensor-specific. */ 3864#define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16 3865 3866/* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */ 3867#define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0 3868 3869 3870/***********************************/ 3871/* MC_CMD_GET_RESOURCE_LIMITS 3872 */ 3873#define MC_CMD_GET_RESOURCE_LIMITS 0x4f 3874 3875/* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */ 3876#define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0 3877 3878/* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */ 3879#define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16 3880#define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0 3881#define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4 3882#define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8 3883#define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12 3884 3885 3886/***********************************/ 3887/* MC_CMD_NVRAM_PARTITIONS 3888 * Reads the list of available virtual NVRAM partition types. Locks required: 3889 * none. Returns: 0, EINVAL (bad type). 3890 */ 3891#define MC_CMD_NVRAM_PARTITIONS 0x51 3892 3893/* MC_CMD_NVRAM_PARTITIONS_IN msgrequest */ 3894#define MC_CMD_NVRAM_PARTITIONS_IN_LEN 0 3895 3896/* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */ 3897#define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4 3898#define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 252 3899#define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num)) 3900/* total number of partitions */ 3901#define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0 3902/* type ID code for each of NUM_PARTITIONS partitions */ 3903#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4 3904#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4 3905#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0 3906#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 62 3907 3908 3909/***********************************/ 3910/* MC_CMD_NVRAM_METADATA 3911 * Reads soft metadata for a virtual NVRAM partition type. Locks required: 3912 * none. Returns: 0, EINVAL (bad type). 3913 */ 3914#define MC_CMD_NVRAM_METADATA 0x52 3915 3916/* MC_CMD_NVRAM_METADATA_IN msgrequest */ 3917#define MC_CMD_NVRAM_METADATA_IN_LEN 4 3918/* Partition type ID code */ 3919#define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0 3920 3921/* MC_CMD_NVRAM_METADATA_OUT msgresponse */ 3922#define MC_CMD_NVRAM_METADATA_OUT_LENMIN 20 3923#define MC_CMD_NVRAM_METADATA_OUT_LENMAX 252 3924#define MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num)) 3925/* Partition type ID code */ 3926#define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0 3927#define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4 3928#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0 3929#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1 3930#define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1 3931#define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1 3932#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2 3933#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1 3934/* Subtype ID code for content of this partition */ 3935#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 8 3936/* 1st component of W.X.Y.Z version number for content of this partition */ 3937#define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 12 3938#define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 2 3939/* 2nd component of W.X.Y.Z version number for content of this partition */ 3940#define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 14 3941#define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 2 3942/* 3rd component of W.X.Y.Z version number for content of this partition */ 3943#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 16 3944#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 2 3945/* 4th component of W.X.Y.Z version number for content of this partition */ 3946#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 18 3947#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 2 3948/* Zero-terminated string describing the content of this partition */ 3949#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 20 3950#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1 3951#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0 3952#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232 3953 3954 3955/***********************************/ 3956/* MC_CMD_GET_MAC_ADDRESSES 3957 * Returns the base MAC, count and stride for the requestiong function 3958 */ 3959#define MC_CMD_GET_MAC_ADDRESSES 0x55 3960 3961/* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */ 3962#define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0 3963 3964/* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */ 3965#define MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 16 3966/* Base MAC address */ 3967#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0 3968#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 6 3969/* Padding */ 3970#define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 6 3971#define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2 3972/* Number of allocated MAC addresses */ 3973#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8 3974/* Spacing of allocated MAC addresses */ 3975#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12 3976 3977/* MC_CMD_RESOURCE_SPECIFIER enum */ 3978/* enum: Any */ 3979#define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff 3980/* enum: None */ 3981#define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe 3982 3983/* EVB_PORT_ID structuredef */ 3984#define EVB_PORT_ID_LEN 4 3985#define EVB_PORT_ID_PORT_ID_OFST 0 3986/* enum: An invalid port handle. */ 3987#define EVB_PORT_ID_NULL 0x0 3988/* enum: The port assigned to this function.. */ 3989#define EVB_PORT_ID_ASSIGNED 0x1000000 3990/* enum: External network port 0 */ 3991#define EVB_PORT_ID_MAC0 0x2000000 3992/* enum: External network port 1 */ 3993#define EVB_PORT_ID_MAC1 0x2000001 3994/* enum: External network port 2 */ 3995#define EVB_PORT_ID_MAC2 0x2000002 3996/* enum: External network port 3 */ 3997#define EVB_PORT_ID_MAC3 0x2000003 3998#define EVB_PORT_ID_PORT_ID_LBN 0 3999#define EVB_PORT_ID_PORT_ID_WIDTH 32 4000 4001/* EVB_VLAN_TAG structuredef */ 4002#define EVB_VLAN_TAG_LEN 2 4003/* The VLAN tag value */ 4004#define EVB_VLAN_TAG_VLAN_ID_LBN 0 4005#define EVB_VLAN_TAG_VLAN_ID_WIDTH 12 4006#define EVB_VLAN_TAG_MODE_LBN 12 4007#define EVB_VLAN_TAG_MODE_WIDTH 4 4008/* enum: Insert the VLAN. */ 4009#define EVB_VLAN_TAG_INSERT 0x0 4010/* enum: Replace the VLAN if already present. */ 4011#define EVB_VLAN_TAG_REPLACE 0x1 4012 4013/* BUFTBL_ENTRY structuredef */ 4014#define BUFTBL_ENTRY_LEN 12 4015/* the owner ID */ 4016#define BUFTBL_ENTRY_OID_OFST 0 4017#define BUFTBL_ENTRY_OID_LEN 2 4018#define BUFTBL_ENTRY_OID_LBN 0 4019#define BUFTBL_ENTRY_OID_WIDTH 16 4020/* the page parameter as one of ESE_DZ_SMC_PAGE_SIZE_ */ 4021#define BUFTBL_ENTRY_PGSZ_OFST 2 4022#define BUFTBL_ENTRY_PGSZ_LEN 2 4023#define BUFTBL_ENTRY_PGSZ_LBN 16 4024#define BUFTBL_ENTRY_PGSZ_WIDTH 16 4025/* the raw 64-bit address field from the SMC, not adjusted for page size */ 4026#define BUFTBL_ENTRY_RAWADDR_OFST 4 4027#define BUFTBL_ENTRY_RAWADDR_LEN 8 4028#define BUFTBL_ENTRY_RAWADDR_LO_OFST 4 4029#define BUFTBL_ENTRY_RAWADDR_HI_OFST 8 4030#define BUFTBL_ENTRY_RAWADDR_LBN 32 4031#define BUFTBL_ENTRY_RAWADDR_WIDTH 64 4032 4033/* NVRAM_PARTITION_TYPE structuredef */ 4034#define NVRAM_PARTITION_TYPE_LEN 2 4035#define NVRAM_PARTITION_TYPE_ID_OFST 0 4036#define NVRAM_PARTITION_TYPE_ID_LEN 2 4037/* enum: Primary MC firmware partition */ 4038#define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100 4039/* enum: Secondary MC firmware partition */ 4040#define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200 4041/* enum: Expansion ROM partition */ 4042#define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300 4043/* enum: Static configuration TLV partition */ 4044#define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400 4045/* enum: Dynamic configuration TLV partition */ 4046#define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500 4047/* enum: Expansion ROM configuration data for port 0 */ 4048#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600 4049/* enum: Expansion ROM configuration data for port 1 */ 4050#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601 4051/* enum: Expansion ROM configuration data for port 2 */ 4052#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602 4053/* enum: Expansion ROM configuration data for port 3 */ 4054#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603 4055/* enum: Non-volatile log output partition */ 4056#define NVRAM_PARTITION_TYPE_LOG 0x700 4057/* enum: Device state dump output partition */ 4058#define NVRAM_PARTITION_TYPE_DUMP 0x800 4059/* enum: Application license key storage partition */ 4060#define NVRAM_PARTITION_TYPE_LICENSE 0x900 4061/* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */ 4062#define NVRAM_PARTITION_TYPE_PHY_MIN 0xa00 4063/* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */ 4064#define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff 4065/* enum: Start of reserved value range (firmware may use for any purpose) */ 4066#define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00 4067/* enum: End of reserved value range (firmware may use for any purpose) */ 4068#define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd 4069/* enum: Recovery partition map (provided if real map is missing or corrupt) */ 4070#define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe 4071/* enum: Partition map (real map as stored in flash) */ 4072#define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff 4073#define NVRAM_PARTITION_TYPE_ID_LBN 0 4074#define NVRAM_PARTITION_TYPE_ID_WIDTH 16 4075 4076/* LICENSED_APP_ID structuredef */ 4077#define LICENSED_APP_ID_LEN 4 4078#define LICENSED_APP_ID_ID_OFST 0 4079/* enum: OpenOnload */ 4080#define LICENSED_APP_ID_ONLOAD 0x1 4081/* enum: PTP timestamping */ 4082#define LICENSED_APP_ID_PTP 0x2 4083/* enum: SolarCapture Pro */ 4084#define LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4 4085#define LICENSED_APP_ID_ID_LBN 0 4086#define LICENSED_APP_ID_ID_WIDTH 32 4087 4088 4089/***********************************/ 4090/* MC_CMD_READ_REGS 4091 * Get a dump of the MCPU registers 4092 */ 4093#define MC_CMD_READ_REGS 0x50 4094 4095/* MC_CMD_READ_REGS_IN msgrequest */ 4096#define MC_CMD_READ_REGS_IN_LEN 0 4097 4098/* MC_CMD_READ_REGS_OUT msgresponse */ 4099#define MC_CMD_READ_REGS_OUT_LEN 308 4100/* Whether the corresponding register entry contains a valid value */ 4101#define MC_CMD_READ_REGS_OUT_MASK_OFST 0 4102#define MC_CMD_READ_REGS_OUT_MASK_LEN 16 4103/* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr, 4104 * fir, fp) 4105 */ 4106#define MC_CMD_READ_REGS_OUT_REGS_OFST 16 4107#define MC_CMD_READ_REGS_OUT_REGS_LEN 4 4108#define MC_CMD_READ_REGS_OUT_REGS_NUM 73 4109 4110 4111/***********************************/ 4112/* MC_CMD_INIT_EVQ 4113 * Set up an event queue according to the supplied parameters. The IN arguments 4114 * end with an address for each 4k of host memory required to back the EVQ. 4115 */ 4116#define MC_CMD_INIT_EVQ 0x80 4117 4118/* MC_CMD_INIT_EVQ_IN msgrequest */ 4119#define MC_CMD_INIT_EVQ_IN_LENMIN 44 4120#define MC_CMD_INIT_EVQ_IN_LENMAX 548 4121#define MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num)) 4122/* Size, in entries */ 4123#define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0 4124/* Desired instance. Must be set to a specific instance, which is a function 4125 * local queue index. 4126 */ 4127#define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4 4128/* The initial timer value. The load value is ignored if the timer mode is DIS. 4129 */ 4130#define MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8 4131/* The reload value is ignored in one-shot modes */ 4132#define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12 4133/* tbd */ 4134#define MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16 4135#define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0 4136#define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1 4137#define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1 4138#define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1 4139#define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 2 4140#define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1 4141#define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 3 4142#define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1 4143#define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4 4144#define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1 4145#define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 5 4146#define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1 4147#define MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20 4148/* enum: Disabled */ 4149#define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0 4150/* enum: Immediate */ 4151#define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1 4152/* enum: Triggered */ 4153#define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2 4154/* enum: Hold-off */ 4155#define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3 4156/* Target EVQ for wakeups if in wakeup mode. */ 4157#define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24 4158/* Target interrupt if in interrupting mode (note union with target EVQ). Use 4159 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test 4160 * purposes. 4161 */ 4162#define MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24 4163/* Event Counter Mode. */ 4164#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 28 4165/* enum: Disabled */ 4166#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0 4167/* enum: Disabled */ 4168#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1 4169/* enum: Disabled */ 4170#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2 4171/* enum: Disabled */ 4172#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3 4173/* Event queue packet count threshold. */ 4174#define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 32 4175/* 64-bit address of 4k of 4k-aligned host memory buffer */ 4176#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36 4177#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8 4178#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36 4179#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40 4180#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1 4181#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64 4182 4183/* MC_CMD_INIT_EVQ_OUT msgresponse */ 4184#define MC_CMD_INIT_EVQ_OUT_LEN 4 4185/* Only valid if INTRFLAG was true */ 4186#define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0 4187 4188/* QUEUE_CRC_MODE structuredef */ 4189#define QUEUE_CRC_MODE_LEN 1 4190#define QUEUE_CRC_MODE_MODE_LBN 0 4191#define QUEUE_CRC_MODE_MODE_WIDTH 4 4192/* enum: No CRC. */ 4193#define QUEUE_CRC_MODE_NONE 0x0 4194/* enum: CRC Fiber channel over ethernet. */ 4195#define QUEUE_CRC_MODE_FCOE 0x1 4196/* enum: CRC (digest) iSCSI header only. */ 4197#define QUEUE_CRC_MODE_ISCSI_HDR 0x2 4198/* enum: CRC (digest) iSCSI header and payload. */ 4199#define QUEUE_CRC_MODE_ISCSI 0x3 4200/* enum: CRC Fiber channel over IP over ethernet. */ 4201#define QUEUE_CRC_MODE_FCOIPOE 0x4 4202/* enum: CRC MPA. */ 4203#define QUEUE_CRC_MODE_MPA 0x5 4204#define QUEUE_CRC_MODE_SPARE_LBN 4 4205#define QUEUE_CRC_MODE_SPARE_WIDTH 4 4206 4207 4208/***********************************/ 4209/* MC_CMD_INIT_RXQ 4210 * set up a receive queue according to the supplied parameters. The IN 4211 * arguments end with an address for each 4k of host memory required to back 4212 * the RXQ. 4213 */ 4214#define MC_CMD_INIT_RXQ 0x81 4215 4216/* MC_CMD_INIT_RXQ_IN msgrequest */ 4217#define MC_CMD_INIT_RXQ_IN_LENMIN 36 4218#define MC_CMD_INIT_RXQ_IN_LENMAX 252 4219#define MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num)) 4220/* Size, in entries */ 4221#define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0 4222/* The EVQ to send events to. This is an index originally specified to INIT_EVQ 4223 */ 4224#define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4 4225/* The value to put in the event data. Check hardware spec. for valid range. */ 4226#define MC_CMD_INIT_RXQ_IN_LABEL_OFST 8 4227/* Desired instance. Must be set to a specific instance, which is a function 4228 * local queue index. 4229 */ 4230#define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12 4231/* There will be more flags here. */ 4232#define MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16 4233#define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0 4234#define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1 4235#define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1 4236#define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1 4237#define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2 4238#define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1 4239#define MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3 4240#define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4 4241#define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7 4242#define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1 4243#define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8 4244#define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1 4245#define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 9 4246#define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1 4247/* Owner ID to use if in buffer mode (zero if physical) */ 4248#define MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20 4249/* The port ID associated with the v-adaptor which should contain this DMAQ. */ 4250#define MC_CMD_INIT_RXQ_IN_PORT_ID_OFST 24 4251/* 64-bit address of 4k of 4k-aligned host memory buffer */ 4252#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28 4253#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8 4254#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28 4255#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32 4256#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1 4257#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28 4258 4259/* MC_CMD_INIT_RXQ_OUT msgresponse */ 4260#define MC_CMD_INIT_RXQ_OUT_LEN 0 4261 4262 4263/***********************************/ 4264/* MC_CMD_INIT_TXQ 4265 */ 4266#define MC_CMD_INIT_TXQ 0x82 4267 4268/* MC_CMD_INIT_TXQ_IN msgrequest */ 4269#define MC_CMD_INIT_TXQ_IN_LENMIN 36 4270#define MC_CMD_INIT_TXQ_IN_LENMAX 252 4271#define MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num)) 4272/* Size, in entries */ 4273#define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0 4274/* The EVQ to send events to. This is an index originally specified to 4275 * INIT_EVQ. 4276 */ 4277#define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4 4278/* The value to put in the event data. Check hardware spec. for valid range. */ 4279#define MC_CMD_INIT_TXQ_IN_LABEL_OFST 8 4280/* Desired instance. Must be set to a specific instance, which is a function 4281 * local queue index. 4282 */ 4283#define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12 4284/* There will be more flags here. */ 4285#define MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16 4286#define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0 4287#define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1 4288#define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1 4289#define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1 4290#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2 4291#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 4292#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3 4293#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 4294#define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4 4295#define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4 4296#define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 8 4297#define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1 4298#define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 9 4299#define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1 4300/* Owner ID to use if in buffer mode (zero if physical) */ 4301#define MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20 4302/* The port ID associated with the v-adaptor which should contain this DMAQ. */ 4303#define MC_CMD_INIT_TXQ_IN_PORT_ID_OFST 24 4304/* 64-bit address of 4k of 4k-aligned host memory buffer */ 4305#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28 4306#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8 4307#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28 4308#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32 4309#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1 4310#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28 4311 4312/* MC_CMD_INIT_TXQ_OUT msgresponse */ 4313#define MC_CMD_INIT_TXQ_OUT_LEN 0 4314 4315 4316/***********************************/ 4317/* MC_CMD_FINI_EVQ 4318 * Teardown an EVQ. 4319 * 4320 * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first 4321 * or the operation will fail with EBUSY 4322 */ 4323#define MC_CMD_FINI_EVQ 0x83 4324 4325/* MC_CMD_FINI_EVQ_IN msgrequest */ 4326#define MC_CMD_FINI_EVQ_IN_LEN 4 4327/* Instance of EVQ to destroy. Should be the same instance as that previously 4328 * passed to INIT_EVQ 4329 */ 4330#define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0 4331 4332/* MC_CMD_FINI_EVQ_OUT msgresponse */ 4333#define MC_CMD_FINI_EVQ_OUT_LEN 0 4334 4335 4336/***********************************/ 4337/* MC_CMD_FINI_RXQ 4338 * Teardown a RXQ. 4339 */ 4340#define MC_CMD_FINI_RXQ 0x84 4341 4342/* MC_CMD_FINI_RXQ_IN msgrequest */ 4343#define MC_CMD_FINI_RXQ_IN_LEN 4 4344/* Instance of RXQ to destroy */ 4345#define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0 4346 4347/* MC_CMD_FINI_RXQ_OUT msgresponse */ 4348#define MC_CMD_FINI_RXQ_OUT_LEN 0 4349 4350 4351/***********************************/ 4352/* MC_CMD_FINI_TXQ 4353 * Teardown a TXQ. 4354 */ 4355#define MC_CMD_FINI_TXQ 0x85 4356 4357/* MC_CMD_FINI_TXQ_IN msgrequest */ 4358#define MC_CMD_FINI_TXQ_IN_LEN 4 4359/* Instance of TXQ to destroy */ 4360#define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0 4361 4362/* MC_CMD_FINI_TXQ_OUT msgresponse */ 4363#define MC_CMD_FINI_TXQ_OUT_LEN 0 4364 4365 4366/***********************************/ 4367/* MC_CMD_DRIVER_EVENT 4368 * Generate an event on an EVQ belonging to the function issuing the command. 4369 */ 4370#define MC_CMD_DRIVER_EVENT 0x86 4371 4372/* MC_CMD_DRIVER_EVENT_IN msgrequest */ 4373#define MC_CMD_DRIVER_EVENT_IN_LEN 12 4374/* Handle of target EVQ */ 4375#define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0 4376/* Bits 0 - 63 of event */ 4377#define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4 4378#define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8 4379#define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4 4380#define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8 4381 4382/* MC_CMD_DRIVER_EVENT_OUT msgresponse */ 4383#define MC_CMD_DRIVER_EVENT_OUT_LEN 0 4384 4385 4386/***********************************/ 4387/* MC_CMD_PROXY_CMD 4388 * Execute an arbitrary MCDI command on behalf of a different function, subject 4389 * to security restrictions. The command to be proxied follows immediately 4390 * afterward in the host buffer (or on the UART). This command supercedes 4391 * MC_CMD_SET_FUNC, which remains available for Siena but now deprecated. 4392 */ 4393#define MC_CMD_PROXY_CMD 0x5b 4394 4395/* MC_CMD_PROXY_CMD_IN msgrequest */ 4396#define MC_CMD_PROXY_CMD_IN_LEN 4 4397/* The handle of the target function. */ 4398#define MC_CMD_PROXY_CMD_IN_TARGET_OFST 0 4399#define MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0 4400#define MC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 16 4401#define MC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 16 4402#define MC_CMD_PROXY_CMD_IN_TARGET_VF_WIDTH 16 4403#define MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */ 4404 4405/* MC_CMD_PROXY_CMD_OUT msgresponse */ 4406#define MC_CMD_PROXY_CMD_OUT_LEN 0 4407 4408 4409/***********************************/ 4410/* MC_CMD_ALLOC_BUFTBL_CHUNK 4411 * Allocate a set of buffer table entries using the specified owner ID. This 4412 * operation allocates the required buffer table entries (and fails if it 4413 * cannot do so). The buffer table entries will initially be zeroed. 4414 */ 4415#define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87 4416 4417/* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */ 4418#define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8 4419/* Owner ID to use */ 4420#define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0 4421/* Size of buffer table pages to use, in bytes (note that only a few values are 4422 * legal on any specific hardware). 4423 */ 4424#define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4 4425 4426/* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */ 4427#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12 4428#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0 4429#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4 4430/* Buffer table IDs for use in DMA descriptors. */ 4431#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8 4432 4433 4434/***********************************/ 4435/* MC_CMD_PROGRAM_BUFTBL_ENTRIES 4436 * Reprogram a set of buffer table entries in the specified chunk. 4437 */ 4438#define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88 4439 4440/* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */ 4441#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20 4442#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 268 4443#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num)) 4444#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0 4445/* ID */ 4446#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4 4447/* Num entries */ 4448#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8 4449/* Buffer table entry address */ 4450#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12 4451#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8 4452#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12 4453#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16 4454#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1 4455#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 32 4456 4457/* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */ 4458#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0 4459 4460 4461/***********************************/ 4462/* MC_CMD_FREE_BUFTBL_CHUNK 4463 */ 4464#define MC_CMD_FREE_BUFTBL_CHUNK 0x89 4465 4466/* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */ 4467#define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4 4468#define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0 4469 4470/* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */ 4471#define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0 4472 4473 4474/***********************************/ 4475/* MC_CMD_FILTER_OP 4476 * Multiplexed MCDI call for filter operations 4477 */ 4478#define MC_CMD_FILTER_OP 0x8a 4479 4480/* MC_CMD_FILTER_OP_IN msgrequest */ 4481#define MC_CMD_FILTER_OP_IN_LEN 108 4482/* identifies the type of operation requested */ 4483#define MC_CMD_FILTER_OP_IN_OP_OFST 0 4484/* enum: single-recipient filter insert */ 4485#define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0 4486/* enum: single-recipient filter remove */ 4487#define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1 4488/* enum: multi-recipient filter subscribe */ 4489#define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2 4490/* enum: multi-recipient filter unsubscribe */ 4491#define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3 4492/* enum: replace one recipient with another (warning - the filter handle may 4493 * change) 4494 */ 4495#define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4 4496/* filter handle (for remove / unsubscribe operations) */ 4497#define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4 4498#define MC_CMD_FILTER_OP_IN_HANDLE_LEN 8 4499#define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4 4500#define MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8 4501/* The port ID associated with the v-adaptor which should contain this filter. 4502 */ 4503#define MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12 4504/* fields to include in match criteria */ 4505#define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16 4506#define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0 4507#define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1 4508#define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1 4509#define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1 4510#define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2 4511#define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1 4512#define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3 4513#define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1 4514#define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4 4515#define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1 4516#define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5 4517#define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1 4518#define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6 4519#define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1 4520#define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7 4521#define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1 4522#define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8 4523#define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1 4524#define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9 4525#define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1 4526#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10 4527#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1 4528#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11 4529#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1 4530#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 4531#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 4532#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 4533#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 4534/* receive destination */ 4535#define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 20 4536/* enum: drop packets */ 4537#define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0 4538/* enum: receive to host */ 4539#define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1 4540/* enum: receive to MC */ 4541#define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2 4542/* enum: loop back to port 0 TX MAC */ 4543#define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3 4544/* enum: loop back to port 1 TX MAC */ 4545#define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4 4546/* receive queue handle (for multiple queue modes, this is the base queue) */ 4547#define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24 4548/* receive mode */ 4549#define MC_CMD_FILTER_OP_IN_RX_MODE_OFST 28 4550/* enum: receive to just the specified queue */ 4551#define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0 4552/* enum: receive to multiple queues using RSS context */ 4553#define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1 4554/* enum: receive to multiple queues using .1p mapping */ 4555#define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2 4556/* enum: install a filter entry that will never match; for test purposes only 4557 */ 4558#define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 4559/* RSS context (for RX_MODE_RSS) or .1p mapping handle (for 4560 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or 4561 * MC_CMD_DOT1P_MAPPING_ALLOC. Note that these handles should be considered 4562 * opaque to the host, although a value of 0xFFFFFFFF is guaranteed never to be 4563 * a valid handle. 4564 */ 4565#define MC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 32 4566/* transmit domain (reserved; set to 0) */ 4567#define MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 36 4568/* transmit destination (either set the MAC and/or PM bits for explicit 4569 * control, or set this field to TX_DEST_DEFAULT for sensible default 4570 * behaviour) 4571 */ 4572#define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 40 4573/* enum: request default behaviour (based on filter type) */ 4574#define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff 4575#define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0 4576#define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1 4577#define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1 4578#define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1 4579/* source MAC address to match (as bytes in network order) */ 4580#define MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 44 4581#define MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6 4582/* source port to match (as bytes in network order) */ 4583#define MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 50 4584#define MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2 4585/* destination MAC address to match (as bytes in network order) */ 4586#define MC_CMD_FILTER_OP_IN_DST_MAC_OFST 52 4587#define MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6 4588/* destination port to match (as bytes in network order) */ 4589#define MC_CMD_FILTER_OP_IN_DST_PORT_OFST 58 4590#define MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2 4591/* Ethernet type to match (as bytes in network order) */ 4592#define MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 60 4593#define MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2 4594/* Inner VLAN tag to match (as bytes in network order) */ 4595#define MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 62 4596#define MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2 4597/* Outer VLAN tag to match (as bytes in network order) */ 4598#define MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 64 4599#define MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2 4600/* IP protocol to match (in low byte; set high byte to 0) */ 4601#define MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 66 4602#define MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2 4603/* Firmware defined register 0 to match (reserved; set to 0) */ 4604#define MC_CMD_FILTER_OP_IN_FWDEF0_OFST 68 4605/* Firmware defined register 1 to match (reserved; set to 0) */ 4606#define MC_CMD_FILTER_OP_IN_FWDEF1_OFST 72 4607/* source IP address to match (as bytes in network order; set last 12 bytes to 4608 * 0 for IPv4 address) 4609 */ 4610#define MC_CMD_FILTER_OP_IN_SRC_IP_OFST 76 4611#define MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16 4612/* destination IP address to match (as bytes in network order; set last 12 4613 * bytes to 0 for IPv4 address) 4614 */ 4615#define MC_CMD_FILTER_OP_IN_DST_IP_OFST 92 4616#define MC_CMD_FILTER_OP_IN_DST_IP_LEN 16 4617 4618/* MC_CMD_FILTER_OP_OUT msgresponse */ 4619#define MC_CMD_FILTER_OP_OUT_LEN 12 4620/* identifies the type of operation requested */ 4621#define MC_CMD_FILTER_OP_OUT_OP_OFST 0 4622/* Enum values, see field(s): */ 4623/* MC_CMD_FILTER_OP_IN/OP */ 4624/* Returned filter handle (for insert / subscribe operations). Note that these 4625 * handles should be considered opaque to the host, although a value of 4626 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. 4627 */ 4628#define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4 4629#define MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8 4630#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4 4631#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8 4632 4633 4634/***********************************/ 4635/* MC_CMD_GET_PARSER_DISP_INFO 4636 * Get information related to the parser-dispatcher subsystem 4637 */ 4638#define MC_CMD_GET_PARSER_DISP_INFO 0xe4 4639 4640/* MC_CMD_GET_PARSER_DISP_INFO_IN msgrequest */ 4641#define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4 4642/* identifies the type of operation requested */ 4643#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0 4644/* enum: read the list of supported RX filter matches */ 4645#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1 4646 4647/* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */ 4648#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8 4649#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 252 4650#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num)) 4651/* identifies the type of operation requested */ 4652#define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0 4653/* Enum values, see field(s): */ 4654/* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 4655/* number of supported match types */ 4656#define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4 4657/* array of supported match types (valid MATCH_FIELDS values for 4658 * MC_CMD_FILTER_OP) sorted in decreasing priority order 4659 */ 4660#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_OFST 8 4661#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4 4662#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0 4663#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 61 4664 4665 4666/***********************************/ 4667/* MC_CMD_PARSER_DISP_RW 4668 * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging 4669 */ 4670#define MC_CMD_PARSER_DISP_RW 0xe5 4671 4672/* MC_CMD_PARSER_DISP_RW_IN msgrequest */ 4673#define MC_CMD_PARSER_DISP_RW_IN_LEN 32 4674/* identifies the target of the operation */ 4675#define MC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0 4676/* enum: RX dispatcher CPU */ 4677#define MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x0 4678/* enum: TX dispatcher CPU */ 4679#define MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x1 4680/* enum: Lookup engine */ 4681#define MC_CMD_PARSER_DISP_RW_IN_LUE 0x2 4682/* identifies the type of operation requested */ 4683#define MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4 4684/* enum: read a word of DICPU DMEM or a LUE entry */ 4685#define MC_CMD_PARSER_DISP_RW_IN_READ 0x0 4686/* enum: write a word of DICPU DMEM or a LUE entry */ 4687#define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1 4688/* enum: read-modify-write a word of DICPU DMEM (not valid for LUE) */ 4689#define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2 4690/* data memory address or LUE index */ 4691#define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8 4692/* value to write (for DMEM writes) */ 4693#define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 12 4694/* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */ 4695#define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_OFST 12 4696/* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */ 4697#define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_OFST 16 4698/* value to write (for LUE writes) */ 4699#define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_OFST 12 4700#define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_LEN 20 4701 4702/* MC_CMD_PARSER_DISP_RW_OUT msgresponse */ 4703#define MC_CMD_PARSER_DISP_RW_OUT_LEN 52 4704/* value read (for DMEM reads) */ 4705#define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 0 4706/* value read (for LUE reads) */ 4707#define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 0 4708#define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_LEN 20 4709/* up to 8 32-bit words of additional soft state from the LUE manager (the 4710 * exact content is firmware-dependent and intended only for debug use) 4711 */ 4712#define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_OFST 20 4713#define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_LEN 32 4714 4715 4716/***********************************/ 4717/* MC_CMD_GET_PF_COUNT 4718 * Get number of PFs on the device. 4719 */ 4720#define MC_CMD_GET_PF_COUNT 0xb6 4721 4722/* MC_CMD_GET_PF_COUNT_IN msgrequest */ 4723#define MC_CMD_GET_PF_COUNT_IN_LEN 0 4724 4725/* MC_CMD_GET_PF_COUNT_OUT msgresponse */ 4726#define MC_CMD_GET_PF_COUNT_OUT_LEN 1 4727/* Identifies the number of PFs on the device. */ 4728#define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0 4729#define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1 4730 4731 4732/***********************************/ 4733/* MC_CMD_SET_PF_COUNT 4734 * Set number of PFs on the device. 4735 */ 4736#define MC_CMD_SET_PF_COUNT 0xb7 4737 4738/* MC_CMD_SET_PF_COUNT_IN msgrequest */ 4739#define MC_CMD_SET_PF_COUNT_IN_LEN 4 4740/* New number of PFs on the device. */ 4741#define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0 4742 4743/* MC_CMD_SET_PF_COUNT_OUT msgresponse */ 4744#define MC_CMD_SET_PF_COUNT_OUT_LEN 0 4745 4746 4747/***********************************/ 4748/* MC_CMD_GET_PORT_ASSIGNMENT 4749 * Get port assignment for current PCI function. 4750 */ 4751#define MC_CMD_GET_PORT_ASSIGNMENT 0xb8 4752 4753/* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */ 4754#define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0 4755 4756/* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */ 4757#define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4 4758/* Identifies the port assignment for this function. */ 4759#define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0 4760 4761 4762/***********************************/ 4763/* MC_CMD_SET_PORT_ASSIGNMENT 4764 * Set port assignment for current PCI function. 4765 */ 4766#define MC_CMD_SET_PORT_ASSIGNMENT 0xb9 4767 4768/* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */ 4769#define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4 4770/* Identifies the port assignment for this function. */ 4771#define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0 4772 4773/* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */ 4774#define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0 4775 4776 4777/***********************************/ 4778/* MC_CMD_ALLOC_VIS 4779 * Allocate VIs for current PCI function. 4780 */ 4781#define MC_CMD_ALLOC_VIS 0x8b 4782 4783/* MC_CMD_ALLOC_VIS_IN msgrequest */ 4784#define MC_CMD_ALLOC_VIS_IN_LEN 8 4785/* The minimum number of VIs that is acceptable */ 4786#define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0 4787/* The maximum number of VIs that would be useful */ 4788#define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4 4789 4790/* MC_CMD_ALLOC_VIS_OUT msgresponse */ 4791#define MC_CMD_ALLOC_VIS_OUT_LEN 8 4792/* The number of VIs allocated on this function */ 4793#define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0 4794/* The base absolute VI number allocated to this function. Required to 4795 * correctly interpret wakeup events. 4796 */ 4797#define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4 4798 4799 4800/***********************************/ 4801/* MC_CMD_FREE_VIS 4802 * Free VIs for current PCI function. Any linked PIO buffers will be unlinked, 4803 * but not freed. 4804 */ 4805#define MC_CMD_FREE_VIS 0x8c 4806 4807/* MC_CMD_FREE_VIS_IN msgrequest */ 4808#define MC_CMD_FREE_VIS_IN_LEN 0 4809 4810/* MC_CMD_FREE_VIS_OUT msgresponse */ 4811#define MC_CMD_FREE_VIS_OUT_LEN 0 4812 4813 4814/***********************************/ 4815/* MC_CMD_GET_SRIOV_CFG 4816 * Get SRIOV config for this PF. 4817 */ 4818#define MC_CMD_GET_SRIOV_CFG 0xba 4819 4820/* MC_CMD_GET_SRIOV_CFG_IN msgrequest */ 4821#define MC_CMD_GET_SRIOV_CFG_IN_LEN 0 4822 4823/* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */ 4824#define MC_CMD_GET_SRIOV_CFG_OUT_LEN 20 4825/* Number of VFs currently enabled. */ 4826#define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0 4827/* Max number of VFs before sriov stride and offset may need to be changed. */ 4828#define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4 4829#define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8 4830#define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0 4831#define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1 4832/* RID offset of first VF from PF. */ 4833#define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12 4834/* RID offset of each subsequent VF from the previous. */ 4835#define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16 4836 4837 4838/***********************************/ 4839/* MC_CMD_SET_SRIOV_CFG 4840 * Set SRIOV config for this PF. 4841 */ 4842#define MC_CMD_SET_SRIOV_CFG 0xbb 4843 4844/* MC_CMD_SET_SRIOV_CFG_IN msgrequest */ 4845#define MC_CMD_SET_SRIOV_CFG_IN_LEN 20 4846/* Number of VFs currently enabled. */ 4847#define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0 4848/* Max number of VFs before sriov stride and offset may need to be changed. */ 4849#define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4 4850#define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8 4851#define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0 4852#define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1 4853/* RID offset of first VF from PF, or 0 for no change, or 4854 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset. 4855 */ 4856#define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12 4857/* RID offset of each subsequent VF from the previous, 0 for no change, or 4858 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride. 4859 */ 4860#define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16 4861 4862/* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */ 4863#define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0 4864 4865 4866/***********************************/ 4867/* MC_CMD_GET_VI_ALLOC_INFO 4868 * Get information about number of VI's and base VI number allocated to this 4869 * function. 4870 */ 4871#define MC_CMD_GET_VI_ALLOC_INFO 0x8d 4872 4873/* MC_CMD_GET_VI_ALLOC_INFO_IN msgrequest */ 4874#define MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0 4875 4876/* MC_CMD_GET_VI_ALLOC_INFO_OUT msgresponse */ 4877#define MC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 8 4878/* The number of VIs allocated on this function */ 4879#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0 4880/* The base absolute VI number allocated to this function. Required to 4881 * correctly interpret wakeup events. 4882 */ 4883#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4 4884 4885 4886/***********************************/ 4887/* MC_CMD_DUMP_VI_STATE 4888 * For CmdClient use. Dump pertinent information on a specific absolute VI. 4889 */ 4890#define MC_CMD_DUMP_VI_STATE 0x8e 4891 4892/* MC_CMD_DUMP_VI_STATE_IN msgrequest */ 4893#define MC_CMD_DUMP_VI_STATE_IN_LEN 4 4894/* The VI number to query. */ 4895#define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0 4896 4897/* MC_CMD_DUMP_VI_STATE_OUT msgresponse */ 4898#define MC_CMD_DUMP_VI_STATE_OUT_LEN 96 4899/* The PF part of the function owning this VI. */ 4900#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0 4901#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2 4902/* The VF part of the function owning this VI. */ 4903#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_OFST 2 4904#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_LEN 2 4905/* Base of VIs allocated to this function. */ 4906#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4 4907#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_LEN 2 4908/* Count of VIs allocated to the owner function. */ 4909#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_OFST 6 4910#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_LEN 2 4911/* Base interrupt vector allocated to this function. */ 4912#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_OFST 8 4913#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_LEN 2 4914/* Number of interrupt vectors allocated to this function. */ 4915#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_OFST 10 4916#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_LEN 2 4917/* Raw evq ptr table data. */ 4918#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12 4919#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8 4920#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12 4921#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16 4922/* Raw evq timer table data. */ 4923#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20 4924#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8 4925#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20 4926#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24 4927/* Combined metadata field. */ 4928#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28 4929#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0 4930#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16 4931#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16 4932#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 8 4933#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 24 4934#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 8 4935/* TXDPCPU raw table data for queue. */ 4936#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32 4937#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8 4938#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32 4939#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36 4940/* TXDPCPU raw table data for queue. */ 4941#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40 4942#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8 4943#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40 4944#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44 4945/* TXDPCPU raw table data for queue. */ 4946#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48 4947#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8 4948#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48 4949#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52 4950/* Combined metadata field. */ 4951#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56 4952#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8 4953#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56 4954#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60 4955#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0 4956#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16 4957#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 16 4958#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 8 4959#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 24 4960#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 8 4961#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 32 4962#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 8 4963#define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 40 4964#define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 24 4965/* RXDPCPU raw table data for queue. */ 4966#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64 4967#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8 4968#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64 4969#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68 4970/* RXDPCPU raw table data for queue. */ 4971#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72 4972#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8 4973#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72 4974#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76 4975/* Reserved, currently 0. */ 4976#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80 4977#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8 4978#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80 4979#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84 4980/* Combined metadata field. */ 4981#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88 4982#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8 4983#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88 4984#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92 4985#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0 4986#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16 4987#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 16 4988#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 8 4989#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 24 4990#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 8 4991#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32 4992#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8 4993 4994 4995/***********************************/ 4996/* MC_CMD_ALLOC_PIOBUF 4997 * Allocate a push I/O buffer for later use with a tx queue. 4998 */ 4999#define MC_CMD_ALLOC_PIOBUF 0x8f 5000 5001/* MC_CMD_ALLOC_PIOBUF_IN msgrequest */ 5002#define MC_CMD_ALLOC_PIOBUF_IN_LEN 0 5003 5004/* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */ 5005#define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4 5006/* Handle for allocated push I/O buffer. */ 5007#define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0 5008 5009 5010/***********************************/ 5011/* MC_CMD_FREE_PIOBUF 5012 * Free a push I/O buffer. 5013 */ 5014#define MC_CMD_FREE_PIOBUF 0x90 5015 5016/* MC_CMD_FREE_PIOBUF_IN msgrequest */ 5017#define MC_CMD_FREE_PIOBUF_IN_LEN 4 5018/* Handle for allocated push I/O buffer. */ 5019#define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 5020 5021/* MC_CMD_FREE_PIOBUF_OUT msgresponse */ 5022#define MC_CMD_FREE_PIOBUF_OUT_LEN 0 5023 5024 5025/***********************************/ 5026/* MC_CMD_GET_VI_TLP_PROCESSING 5027 * Get TLP steering and ordering information for a VI. 5028 */ 5029#define MC_CMD_GET_VI_TLP_PROCESSING 0xb0 5030 5031/* MC_CMD_GET_VI_TLP_PROCESSING_IN msgrequest */ 5032#define MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4 5033/* VI number to get information for. */ 5034#define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 5035 5036/* MC_CMD_GET_VI_TLP_PROCESSING_OUT msgresponse */ 5037#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 4 5038/* Transaction processing steering hint 1 for use with the Rx Queue. */ 5039#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_OFST 0 5040#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_LEN 1 5041/* Transaction processing steering hint 2 for use with the Ev Queue. */ 5042#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_OFST 1 5043#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_LEN 1 5044/* Use Relaxed ordering model for TLPs on this VI. */ 5045#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_LBN 16 5046#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 1 5047/* Use ID based ordering for TLPs on this VI. */ 5048#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_LBN 17 5049#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 1 5050/* Set no snoop bit for TLPs on this VI. */ 5051#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_LBN 18 5052#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_WIDTH 1 5053/* Enable TPH for TLPs on this VI. */ 5054#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_LBN 19 5055#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1 5056#define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0 5057 5058 5059/***********************************/ 5060/* MC_CMD_SET_VI_TLP_PROCESSING 5061 * Set TLP steering and ordering information for a VI. 5062 */ 5063#define MC_CMD_SET_VI_TLP_PROCESSING 0xb1 5064 5065/* MC_CMD_SET_VI_TLP_PROCESSING_IN msgrequest */ 5066#define MC_CMD_SET_VI_TLP_PROCESSING_IN_LEN 8 5067/* VI number to set information for. */ 5068#define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 5069/* Transaction processing steering hint 1 for use with the Rx Queue. */ 5070#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 4 5071#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_LEN 1 5072/* Transaction processing steering hint 2 for use with the Ev Queue. */ 5073#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_OFST 5 5074#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_LEN 1 5075/* Use Relaxed ordering model for TLPs on this VI. */ 5076#define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_LBN 48 5077#define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 1 5078/* Use ID based ordering for TLPs on this VI. */ 5079#define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_LBN 49 5080#define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 1 5081/* Set the no snoop bit for TLPs on this VI. */ 5082#define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_LBN 50 5083#define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_WIDTH 1 5084/* Enable TPH for TLPs on this VI. */ 5085#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_LBN 51 5086#define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1 5087#define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4 5088 5089/* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */ 5090#define MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0 5091 5092 5093/***********************************/ 5094/* MC_CMD_GET_TLP_PROCESSING_GLOBALS 5095 * Get global PCIe steering and transaction processing configuration. 5096 */ 5097#define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc 5098 5099/* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN msgrequest */ 5100#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 4 5101#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 5102/* enum: MISC. */ 5103#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0 5104/* enum: IDO. */ 5105#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1 5106/* enum: RO. */ 5107#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2 5108/* enum: TPH Type. */ 5109#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3 5110 5111/* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ 5112#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 8 5113#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 0 5114/* Enum values, see field(s): */ 5115/* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ 5116/* Amalgamated TLP info word. */ 5117#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4 5118#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0 5119#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1 5120#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1 5121#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 31 5122#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0 5123#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1 5124#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 1 5125#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 1 5126#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_LBN 2 5127#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 1 5128#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 3 5129#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1 5130#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4 5131#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 28 5132#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0 5133#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1 5134#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 1 5135#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 1 5136#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 2 5137#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1 5138#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 3 5139#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 29 5140#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0 5141#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 5142#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_LBN 2 5143#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_WIDTH 2 5144#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4 5145#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_WIDTH 2 5146#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_LBN 6 5147#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_WIDTH 2 5148#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 8 5149#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 2 5150#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9 5151#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23 5152 5153 5154/***********************************/ 5155/* MC_CMD_SET_TLP_PROCESSING_GLOBALS 5156 * Set global PCIe steering and transaction processing configuration. 5157 */ 5158#define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd 5159 5160/* MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN msgrequest */ 5161#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_LEN 8 5162#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 5163/* Enum values, see field(s): */ 5164/* MC_CMD_GET_TLP_PROCESSING_GLOBALS/MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ 5165/* Amalgamated TLP info word. */ 5166#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4 5167#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0 5168#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1 5169#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0 5170#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 1 5171#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 1 5172#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 1 5173#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_LBN 2 5174#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 1 5175#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_LBN 3 5176#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 1 5177#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0 5178#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 1 5179#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 1 5180#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 1 5181#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_LBN 2 5182#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 1 5183#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0 5184#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 5185#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_LBN 2 5186#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_WIDTH 2 5187#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4 5188#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_WIDTH 2 5189#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_LBN 6 5190#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_WIDTH 2 5191#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 8 5192#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 2 5193#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 10 5194#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 22 5195 5196/* MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ 5197#define MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0 5198 5199 5200/***********************************/ 5201/* MC_CMD_SATELLITE_DOWNLOAD 5202 * Download a new set of images to the satellite CPUs from the host. 5203 */ 5204#define MC_CMD_SATELLITE_DOWNLOAD 0x91 5205 5206/* MC_CMD_SATELLITE_DOWNLOAD_IN msgrequest: The reset requirements for the CPUs 5207 * are subtle, and so downloads must proceed in a number of phases. 5208 * 5209 * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0. 5210 * 5211 * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download 5212 * may consist of multiple chunks. The final chunk (with CHUNK_ID_LAST) should 5213 * be a checksum (a simple 32-bit sum) of the transferred data. An individual 5214 * download may be aborted using CHUNK_ID_ABORT. 5215 * 5216 * 3) PHASE_VECTORS for each of the vector table targets (target IDs 12-15), 5217 * similar to PHASE_IMEMS. 5218 * 5219 * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0. 5220 * 5221 * After any error (a requested abort is not considered to be an error) the 5222 * sequence must be restarted from PHASE_RESET. 5223 */ 5224#define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMIN 20 5225#define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX 252 5226#define MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num)) 5227/* Download phase. (Note: the IDLE phase is used internally and is never valid 5228 * in a command from the host.) 5229 */ 5230#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0 5231#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */ 5232#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */ 5233#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */ 5234#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */ 5235#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */ 5236/* Target for download. (These match the blob numbers defined in 5237 * mc_flash_layout.h.) 5238 */ 5239#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4 5240/* enum: Valid in phase 2 (PHASE_IMEMS) only */ 5241#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x0 5242/* enum: Valid in phase 2 (PHASE_IMEMS) only */ 5243#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x1 5244/* enum: Valid in phase 2 (PHASE_IMEMS) only */ 5245#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x2 5246/* enum: Valid in phase 2 (PHASE_IMEMS) only */ 5247#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x3 5248/* enum: Valid in phase 2 (PHASE_IMEMS) only */ 5249#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x4 5250/* enum: Valid in phase 2 (PHASE_IMEMS) only */ 5251#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x5 5252/* enum: Valid in phase 2 (PHASE_IMEMS) only */ 5253#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x6 5254/* enum: Valid in phase 2 (PHASE_IMEMS) only */ 5255#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x7 5256/* enum: Valid in phase 2 (PHASE_IMEMS) only */ 5257#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x8 5258/* enum: Valid in phase 2 (PHASE_IMEMS) only */ 5259#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x9 5260/* enum: Valid in phase 2 (PHASE_IMEMS) only */ 5261#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa 5262/* enum: Valid in phase 2 (PHASE_IMEMS) only */ 5263#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb 5264/* enum: Valid in phase 3 (PHASE_VECTORS) only */ 5265#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc 5266/* enum: Valid in phase 3 (PHASE_VECTORS) only */ 5267#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd 5268/* enum: Valid in phase 3 (PHASE_VECTORS) only */ 5269#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe 5270/* enum: Valid in phase 3 (PHASE_VECTORS) only */ 5271#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf 5272/* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */ 5273#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff 5274/* Chunk ID, or CHUNK_ID_LAST or CHUNK_ID_ABORT */ 5275#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_OFST 8 5276/* enum: Last chunk, containing checksum rather than data */ 5277#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff 5278/* enum: Abort download of this item */ 5279#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe 5280/* Length of this chunk in bytes */ 5281#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_OFST 12 5282/* Data for this chunk */ 5283#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_OFST 16 5284#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4 5285#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MINNUM 1 5286#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM 59 5287 5288/* MC_CMD_SATELLITE_DOWNLOAD_OUT msgresponse */ 5289#define MC_CMD_SATELLITE_DOWNLOAD_OUT_LEN 8 5290/* Same as MC_CMD_ERR field, but included as 0 in success cases */ 5291#define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 0 5292/* Extra status information */ 5293#define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4 5294/* enum: Code download OK, completed. */ 5295#define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x0 5296/* enum: Code download aborted as requested. */ 5297#define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x1 5298/* enum: Code download OK so far, send next chunk. */ 5299#define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x2 5300/* enum: Download phases out of sequence */ 5301#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x100 5302/* enum: Bad target for this phase */ 5303#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x101 5304/* enum: Chunk ID out of sequence */ 5305#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x200 5306/* enum: Chunk length zero or too large */ 5307#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x201 5308/* enum: Checksum was incorrect */ 5309#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300 5310 5311 5312/***********************************/ 5313/* MC_CMD_GET_CAPABILITIES 5314 * Get device capabilities. 5315 * 5316 * This is supplementary to the MC_CMD_GET_BOARD_CFG command, and intended to 5317 * reference inherent device capabilities as opposed to current NVRAM config. 5318 */ 5319#define MC_CMD_GET_CAPABILITIES 0xbe 5320 5321/* MC_CMD_GET_CAPABILITIES_IN msgrequest */ 5322#define MC_CMD_GET_CAPABILITIES_IN_LEN 0 5323 5324/* MC_CMD_GET_CAPABILITIES_OUT msgresponse */ 5325#define MC_CMD_GET_CAPABILITIES_OUT_LEN 20 5326/* First word of flags. */ 5327#define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0 5328#define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 19 5329#define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1 5330#define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 20 5331#define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1 5332#define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 21 5333#define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1 5334#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 22 5335#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1 5336#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 23 5337#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1 5338#define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 24 5339#define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1 5340#define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 25 5341#define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1 5342#define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 26 5343#define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1 5344#define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN 27 5345#define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 5346/* RxDPCPU firmware id. */ 5347#define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4 5348#define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 2 5349/* enum: Standard RXDP firmware */ 5350#define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0 5351/* enum: Low latency RXDP firmware */ 5352#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1 5353/* enum: RXDP Test firmware image 1 */ 5354#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 5355/* enum: RXDP Test firmware image 2 */ 5356#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 5357/* enum: RXDP Test firmware image 3 */ 5358#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 5359/* enum: RXDP Test firmware image 4 */ 5360#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 5361/* enum: RXDP Test firmware image 5 */ 5362#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105 5363/* enum: RXDP Test firmware image 6 */ 5364#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 5365/* enum: RXDP Test firmware image 7 */ 5366#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 5367/* enum: RXDP Test firmware image 8 */ 5368#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 5369/* TxDPCPU firmware id. */ 5370#define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 6 5371#define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 2 5372/* enum: Standard TXDP firmware */ 5373#define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0 5374/* enum: Low latency TXDP firmware */ 5375#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1 5376/* enum: TXDP Test firmware image 1 */ 5377#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 5378/* enum: TXDP Test firmware image 2 */ 5379#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 5380#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 8 5381#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 2 5382#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0 5383#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 12 5384#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 12 5385#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 5386#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 /* enum */ 5387#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 /* enum */ 5388#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3 /* enum */ 5389#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 /* enum */ 5390#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 5391#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 10 5392#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 2 5393#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0 5394#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 12 5395#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 12 5396#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 5397#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 /* enum */ 5398#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 /* enum */ 5399#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3 /* enum */ 5400#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 /* enum */ 5401#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 5402/* Hardware capabilities of NIC */ 5403#define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 12 5404/* Licensed capabilities */ 5405#define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 16 5406 5407 5408/***********************************/ 5409/* MC_CMD_V2_EXTN 5410 * Encapsulation for a v2 extended command 5411 */ 5412#define MC_CMD_V2_EXTN 0x7f 5413 5414/* MC_CMD_V2_EXTN_IN msgrequest */ 5415#define MC_CMD_V2_EXTN_IN_LEN 4 5416/* the extended command number */ 5417#define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0 5418#define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15 5419#define MC_CMD_V2_EXTN_IN_UNUSED_LBN 15 5420#define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1 5421/* the actual length of the encapsulated command (which is not in the v1 5422 * header) 5423 */ 5424#define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16 5425#define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10 5426#define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26 5427#define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 6 5428 5429 5430/***********************************/ 5431/* MC_CMD_TCM_BUCKET_ALLOC 5432 * Allocate a pacer bucket (for qau rp or a snapper test) 5433 */ 5434#define MC_CMD_TCM_BUCKET_ALLOC 0xb2 5435 5436/* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */ 5437#define MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0 5438 5439/* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */ 5440#define MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4 5441/* the bucket id */ 5442#define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0 5443 5444 5445/***********************************/ 5446/* MC_CMD_TCM_BUCKET_FREE 5447 * Free a pacer bucket 5448 */ 5449#define MC_CMD_TCM_BUCKET_FREE 0xb3 5450 5451/* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */ 5452#define MC_CMD_TCM_BUCKET_FREE_IN_LEN 4 5453/* the bucket id */ 5454#define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0 5455 5456/* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */ 5457#define MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0 5458 5459 5460/***********************************/ 5461/* MC_CMD_TCM_BUCKET_INIT 5462 * Initialise pacer bucket with a given rate 5463 */ 5464#define MC_CMD_TCM_BUCKET_INIT 0xb4 5465 5466/* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */ 5467#define MC_CMD_TCM_BUCKET_INIT_IN_LEN 8 5468/* the bucket id */ 5469#define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0 5470/* the rate in mbps */ 5471#define MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4 5472 5473/* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */ 5474#define MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0 5475 5476 5477/***********************************/ 5478/* MC_CMD_TCM_TXQ_INIT 5479 * Initialise txq in pacer with given options or set options 5480 */ 5481#define MC_CMD_TCM_TXQ_INIT 0xb5 5482 5483/* MC_CMD_TCM_TXQ_INIT_IN msgrequest */ 5484#define MC_CMD_TCM_TXQ_INIT_IN_LEN 28 5485/* the txq id */ 5486#define MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0 5487/* the static priority associated with the txq */ 5488#define MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4 5489/* bitmask of the priority queues this txq is inserted into */ 5490#define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8 5491/* the reaction point (RP) bucket */ 5492#define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12 5493/* an already reserved bucket (typically set to bucket associated with outer 5494 * vswitch) 5495 */ 5496#define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16 5497/* an already reserved bucket (typically set to bucket associated with inner 5498 * vswitch) 5499 */ 5500#define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20 5501/* the min bucket (typically for ETS/minimum bandwidth) */ 5502#define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24 5503 5504/* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */ 5505#define MC_CMD_TCM_TXQ_INIT_OUT_LEN 0 5506 5507 5508/***********************************/ 5509/* MC_CMD_LINK_PIOBUF 5510 * Link a push I/O buffer to a TxQ 5511 */ 5512#define MC_CMD_LINK_PIOBUF 0x92 5513 5514/* MC_CMD_LINK_PIOBUF_IN msgrequest */ 5515#define MC_CMD_LINK_PIOBUF_IN_LEN 8 5516/* Handle for allocated push I/O buffer. */ 5517#define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 5518/* Function Local Instance (VI) number. */ 5519#define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4 5520 5521/* MC_CMD_LINK_PIOBUF_OUT msgresponse */ 5522#define MC_CMD_LINK_PIOBUF_OUT_LEN 0 5523 5524 5525/***********************************/ 5526/* MC_CMD_UNLINK_PIOBUF 5527 * Unlink a push I/O buffer from a TxQ 5528 */ 5529#define MC_CMD_UNLINK_PIOBUF 0x93 5530 5531/* MC_CMD_UNLINK_PIOBUF_IN msgrequest */ 5532#define MC_CMD_UNLINK_PIOBUF_IN_LEN 4 5533/* Function Local Instance (VI) number. */ 5534#define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0 5535 5536/* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */ 5537#define MC_CMD_UNLINK_PIOBUF_OUT_LEN 0 5538 5539 5540/***********************************/ 5541/* MC_CMD_VSWITCH_ALLOC 5542 * allocate and initialise a v-switch. 5543 */ 5544#define MC_CMD_VSWITCH_ALLOC 0x94 5545 5546/* MC_CMD_VSWITCH_ALLOC_IN msgrequest */ 5547#define MC_CMD_VSWITCH_ALLOC_IN_LEN 16 5548/* The port to connect to the v-switch's upstream port. */ 5549#define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 5550/* The type of v-switch to create. */ 5551#define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4 5552/* enum: VLAN */ 5553#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1 5554/* enum: VEB */ 5555#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2 5556/* enum: VEPA */ 5557#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3 5558/* Flags controlling v-port creation */ 5559#define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8 5560#define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 5561#define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 5562/* The number of VLAN tags to support. */ 5563#define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 5564 5565/* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */ 5566#define MC_CMD_VSWITCH_ALLOC_OUT_LEN 0 5567 5568 5569/***********************************/ 5570/* MC_CMD_VSWITCH_FREE 5571 * de-allocate a v-switch. 5572 */ 5573#define MC_CMD_VSWITCH_FREE 0x95 5574 5575/* MC_CMD_VSWITCH_FREE_IN msgrequest */ 5576#define MC_CMD_VSWITCH_FREE_IN_LEN 4 5577/* The port to which the v-switch is connected. */ 5578#define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0 5579 5580/* MC_CMD_VSWITCH_FREE_OUT msgresponse */ 5581#define MC_CMD_VSWITCH_FREE_OUT_LEN 0 5582 5583 5584/***********************************/ 5585/* MC_CMD_VPORT_ALLOC 5586 * allocate a v-port. 5587 */ 5588#define MC_CMD_VPORT_ALLOC 0x96 5589 5590/* MC_CMD_VPORT_ALLOC_IN msgrequest */ 5591#define MC_CMD_VPORT_ALLOC_IN_LEN 20 5592/* The port to which the v-switch is connected. */ 5593#define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 5594/* The type of the new v-port. */ 5595#define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4 5596/* enum: VLAN (obsolete) */ 5597#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1 5598/* enum: VEB (obsolete) */ 5599#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2 5600/* enum: VEPA (obsolete) */ 5601#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3 5602/* enum: A normal v-port receives packets which match a specified MAC and/or 5603 * VLAN. 5604 */ 5605#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4 5606/* enum: An expansion v-port packets traffic which don't match any other 5607 * v-port. 5608 */ 5609#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5 5610/* enum: An test v-port receives packets which match any filters installed by 5611 * its downstream components. 5612 */ 5613#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6 5614/* Flags controlling v-port creation */ 5615#define MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8 5616#define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 5617#define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 5618/* The number of VLAN tags to insert/remove. */ 5619#define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 5620/* The actual VLAN tags to insert/remove */ 5621#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 16 5622#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0 5623#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 16 5624#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 16 5625#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 16 5626 5627/* MC_CMD_VPORT_ALLOC_OUT msgresponse */ 5628#define MC_CMD_VPORT_ALLOC_OUT_LEN 4 5629/* The handle of the new v-port */ 5630#define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0 5631 5632 5633/***********************************/ 5634/* MC_CMD_VPORT_FREE 5635 * de-allocate a v-port. 5636 */ 5637#define MC_CMD_VPORT_FREE 0x97 5638 5639/* MC_CMD_VPORT_FREE_IN msgrequest */ 5640#define MC_CMD_VPORT_FREE_IN_LEN 4 5641/* The handle of the v-port */ 5642#define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0 5643 5644/* MC_CMD_VPORT_FREE_OUT msgresponse */ 5645#define MC_CMD_VPORT_FREE_OUT_LEN 0 5646 5647 5648/***********************************/ 5649/* MC_CMD_VADAPTOR_ALLOC 5650 * allocate a v-adaptor. 5651 */ 5652#define MC_CMD_VADAPTOR_ALLOC 0x98 5653 5654/* MC_CMD_VADAPTOR_ALLOC_IN msgrequest */ 5655#define MC_CMD_VADAPTOR_ALLOC_IN_LEN 16 5656/* The port to connect to the v-adaptor's port. */ 5657#define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 5658/* Flags controlling v-adaptor creation */ 5659#define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8 5660#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0 5661#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1 5662/* The number of VLAN tags to strip on receive */ 5663#define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 12 5664 5665/* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */ 5666#define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0 5667 5668 5669/***********************************/ 5670/* MC_CMD_VADAPTOR_FREE 5671 * de-allocate a v-adaptor. 5672 */ 5673#define MC_CMD_VADAPTOR_FREE 0x99 5674 5675/* MC_CMD_VADAPTOR_FREE_IN msgrequest */ 5676#define MC_CMD_VADAPTOR_FREE_IN_LEN 4 5677/* The port to which the v-adaptor is connected. */ 5678#define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0 5679 5680/* MC_CMD_VADAPTOR_FREE_OUT msgresponse */ 5681#define MC_CMD_VADAPTOR_FREE_OUT_LEN 0 5682 5683 5684/***********************************/ 5685/* MC_CMD_EVB_PORT_ASSIGN 5686 * assign a port to a PCI function. 5687 */ 5688#define MC_CMD_EVB_PORT_ASSIGN 0x9a 5689 5690/* MC_CMD_EVB_PORT_ASSIGN_IN msgrequest */ 5691#define MC_CMD_EVB_PORT_ASSIGN_IN_LEN 8 5692/* The port to assign. */ 5693#define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0 5694/* The target function to modify. */ 5695#define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4 5696#define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0 5697#define MC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 16 5698#define MC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 16 5699#define MC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 16 5700 5701/* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */ 5702#define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0 5703 5704 5705/***********************************/ 5706/* MC_CMD_RDWR_A64_REGIONS 5707 * Assign the 64 bit region addresses. 5708 */ 5709#define MC_CMD_RDWR_A64_REGIONS 0x9b 5710 5711/* MC_CMD_RDWR_A64_REGIONS_IN msgrequest */ 5712#define MC_CMD_RDWR_A64_REGIONS_IN_LEN 17 5713#define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0 5714#define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4 5715#define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_OFST 8 5716#define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_OFST 12 5717/* Write enable bits 0-3, set to write, clear to read. */ 5718#define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_LBN 128 5719#define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4 5720#define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_OFST 16 5721#define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 1 5722 5723/* MC_CMD_RDWR_A64_REGIONS_OUT msgresponse: This data always included 5724 * regardless of state of write bits in the request. 5725 */ 5726#define MC_CMD_RDWR_A64_REGIONS_OUT_LEN 16 5727#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0 5728#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4 5729#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_OFST 8 5730#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 12 5731 5732 5733/***********************************/ 5734/* MC_CMD_ONLOAD_STACK_ALLOC 5735 * Allocate an Onload stack ID. 5736 */ 5737#define MC_CMD_ONLOAD_STACK_ALLOC 0x9c 5738 5739/* MC_CMD_ONLOAD_STACK_ALLOC_IN msgrequest */ 5740#define MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4 5741/* The handle of the owning upstream port */ 5742#define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 5743 5744/* MC_CMD_ONLOAD_STACK_ALLOC_OUT msgresponse */ 5745#define MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4 5746/* The handle of the new Onload stack */ 5747#define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0 5748 5749 5750/***********************************/ 5751/* MC_CMD_ONLOAD_STACK_FREE 5752 * Free an Onload stack ID. 5753 */ 5754#define MC_CMD_ONLOAD_STACK_FREE 0x9d 5755 5756/* MC_CMD_ONLOAD_STACK_FREE_IN msgrequest */ 5757#define MC_CMD_ONLOAD_STACK_FREE_IN_LEN 4 5758/* The handle of the Onload stack */ 5759#define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0 5760 5761/* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */ 5762#define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0 5763 5764 5765/***********************************/ 5766/* MC_CMD_RSS_CONTEXT_ALLOC 5767 * Allocate an RSS context. 5768 */ 5769#define MC_CMD_RSS_CONTEXT_ALLOC 0x9e 5770 5771/* MC_CMD_RSS_CONTEXT_ALLOC_IN msgrequest */ 5772#define MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN 12 5773/* The handle of the owning upstream port */ 5774#define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 5775/* The type of context to allocate */ 5776#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4 5777/* enum: Allocate a context for exclusive use. The key and indirection table 5778 * must be explicitly configured. 5779 */ 5780#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0 5781/* enum: Allocate a context for shared use; this will spread across a range of 5782 * queues, but the key and indirection table are pre-configured and may not be 5783 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64. 5784 */ 5785#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1 5786/* Number of queues spanned by this context, in the range 1-64; valid offsets 5787 * in the indirection table will be in the range 0 to NUM_QUEUES-1. 5788 */ 5789#define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 8 5790 5791/* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */ 5792#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4 5793/* The handle of the new RSS context */ 5794#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0 5795 5796 5797/***********************************/ 5798/* MC_CMD_RSS_CONTEXT_FREE 5799 * Free an RSS context. 5800 */ 5801#define MC_CMD_RSS_CONTEXT_FREE 0x9f 5802 5803/* MC_CMD_RSS_CONTEXT_FREE_IN msgrequest */ 5804#define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4 5805/* The handle of the RSS context */ 5806#define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0 5807 5808/* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */ 5809#define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0 5810 5811 5812/***********************************/ 5813/* MC_CMD_RSS_CONTEXT_SET_KEY 5814 * Set the Toeplitz hash key for an RSS context. 5815 */ 5816#define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0 5817 5818/* MC_CMD_RSS_CONTEXT_SET_KEY_IN msgrequest */ 5819#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN 44 5820/* The handle of the RSS context */ 5821#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0 5822/* The 40-byte Toeplitz hash key (TBD endianness issues?) */ 5823#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4 5824#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN 40 5825 5826/* MC_CMD_RSS_CONTEXT_SET_KEY_OUT msgresponse */ 5827#define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0 5828 5829 5830/***********************************/ 5831/* MC_CMD_RSS_CONTEXT_GET_KEY 5832 * Get the Toeplitz hash key for an RSS context. 5833 */ 5834#define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1 5835 5836/* MC_CMD_RSS_CONTEXT_GET_KEY_IN msgrequest */ 5837#define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4 5838/* The handle of the RSS context */ 5839#define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0 5840 5841/* MC_CMD_RSS_CONTEXT_GET_KEY_OUT msgresponse */ 5842#define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN 44 5843/* The 40-byte Toeplitz hash key (TBD endianness issues?) */ 5844#define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4 5845#define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_LEN 40 5846 5847 5848/***********************************/ 5849/* MC_CMD_RSS_CONTEXT_SET_TABLE 5850 * Set the indirection table for an RSS context. 5851 */ 5852#define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2 5853 5854/* MC_CMD_RSS_CONTEXT_SET_TABLE_IN msgrequest */ 5855#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN 132 5856/* The handle of the RSS context */ 5857#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 5858/* The 128-byte indirection table (1 byte per entry) */ 5859#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4 5860#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN 128 5861 5862/* MC_CMD_RSS_CONTEXT_SET_TABLE_OUT msgresponse */ 5863#define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0 5864 5865 5866/***********************************/ 5867/* MC_CMD_RSS_CONTEXT_GET_TABLE 5868 * Get the indirection table for an RSS context. 5869 */ 5870#define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3 5871 5872/* MC_CMD_RSS_CONTEXT_GET_TABLE_IN msgrequest */ 5873#define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4 5874/* The handle of the RSS context */ 5875#define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 5876 5877/* MC_CMD_RSS_CONTEXT_GET_TABLE_OUT msgresponse */ 5878#define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN 132 5879/* The 128-byte indirection table (1 byte per entry) */ 5880#define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4 5881#define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 128 5882 5883 5884/***********************************/ 5885/* MC_CMD_RSS_CONTEXT_SET_FLAGS 5886 * Set various control flags for an RSS context. 5887 */ 5888#define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1 5889 5890/* MC_CMD_RSS_CONTEXT_SET_FLAGS_IN msgrequest */ 5891#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 8 5892/* The handle of the RSS context */ 5893#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 5894/* Hash control flags */ 5895#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4 5896#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0 5897#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1 5898#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1 5899#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1 5900#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 2 5901#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1 5902#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 3 5903#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1 5904 5905/* MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT msgresponse */ 5906#define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0 5907 5908 5909/***********************************/ 5910/* MC_CMD_RSS_CONTEXT_GET_FLAGS 5911 * Get various control flags for an RSS context. 5912 */ 5913#define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2 5914 5915/* MC_CMD_RSS_CONTEXT_GET_FLAGS_IN msgrequest */ 5916#define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4 5917/* The handle of the RSS context */ 5918#define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 5919 5920/* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */ 5921#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 8 5922/* Hash control flags */ 5923#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4 5924#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0 5925#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1 5926#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1 5927#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1 5928#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN 2 5929#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1 5930#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN 3 5931#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1 5932 5933 5934/***********************************/ 5935/* MC_CMD_DOT1P_MAPPING_ALLOC 5936 * Allocate a .1p mapping. 5937 */ 5938#define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4 5939 5940/* MC_CMD_DOT1P_MAPPING_ALLOC_IN msgrequest */ 5941#define MC_CMD_DOT1P_MAPPING_ALLOC_IN_LEN 8 5942/* The handle of the owning upstream port */ 5943#define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 5944/* Number of queues spanned by this mapping, in the range 1-64; valid fixed 5945 * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and 5946 * referenced RSS contexts must span no more than this number. 5947 */ 5948#define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_OFST 4 5949 5950/* MC_CMD_DOT1P_MAPPING_ALLOC_OUT msgresponse */ 5951#define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_LEN 4 5952/* The handle of the new .1p mapping */ 5953#define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0 5954 5955 5956/***********************************/ 5957/* MC_CMD_DOT1P_MAPPING_FREE 5958 * Free a .1p mapping. 5959 */ 5960#define MC_CMD_DOT1P_MAPPING_FREE 0xa5 5961 5962/* MC_CMD_DOT1P_MAPPING_FREE_IN msgrequest */ 5963#define MC_CMD_DOT1P_MAPPING_FREE_IN_LEN 4 5964/* The handle of the .1p mapping */ 5965#define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_OFST 0 5966 5967/* MC_CMD_DOT1P_MAPPING_FREE_OUT msgresponse */ 5968#define MC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0 5969 5970 5971/***********************************/ 5972/* MC_CMD_DOT1P_MAPPING_SET_TABLE 5973 * Set the mapping table for a .1p mapping. 5974 */ 5975#define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6 5976 5977/* MC_CMD_DOT1P_MAPPING_SET_TABLE_IN msgrequest */ 5978#define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_LEN 36 5979/* The handle of the .1p mapping */ 5980#define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 5981/* Per-priority mappings (1 32-bit word per entry - an offset or RSS context 5982 * handle) 5983 */ 5984#define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_OFST 4 5985#define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_LEN 32 5986 5987/* MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT msgresponse */ 5988#define MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT_LEN 0 5989 5990 5991/***********************************/ 5992/* MC_CMD_DOT1P_MAPPING_GET_TABLE 5993 * Get the mapping table for a .1p mapping. 5994 */ 5995#define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7 5996 5997/* MC_CMD_DOT1P_MAPPING_GET_TABLE_IN msgrequest */ 5998#define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_LEN 4 5999/* The handle of the .1p mapping */ 6000#define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 6001 6002/* MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT msgresponse */ 6003#define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_LEN 36 6004/* Per-priority mappings (1 32-bit word per entry - an offset or RSS context 6005 * handle) 6006 */ 6007#define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_OFST 4 6008#define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_LEN 32 6009 6010 6011/***********************************/ 6012/* MC_CMD_GET_VECTOR_CFG 6013 * Get Interrupt Vector config for this PF. 6014 */ 6015#define MC_CMD_GET_VECTOR_CFG 0xbf 6016 6017/* MC_CMD_GET_VECTOR_CFG_IN msgrequest */ 6018#define MC_CMD_GET_VECTOR_CFG_IN_LEN 0 6019 6020/* MC_CMD_GET_VECTOR_CFG_OUT msgresponse */ 6021#define MC_CMD_GET_VECTOR_CFG_OUT_LEN 12 6022/* Base absolute interrupt vector number. */ 6023#define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0 6024/* Number of interrupt vectors allocate to this PF. */ 6025#define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4 6026/* Number of interrupt vectors to allocate per VF. */ 6027#define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8 6028 6029 6030/***********************************/ 6031/* MC_CMD_SET_VECTOR_CFG 6032 * Set Interrupt Vector config for this PF. 6033 */ 6034#define MC_CMD_SET_VECTOR_CFG 0xc0 6035 6036/* MC_CMD_SET_VECTOR_CFG_IN msgrequest */ 6037#define MC_CMD_SET_VECTOR_CFG_IN_LEN 12 6038/* Base absolute interrupt vector number, or MC_CMD_RESOURCE_INSTANCE_ANY to 6039 * let the system find a suitable base. 6040 */ 6041#define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0 6042/* Number of interrupt vectors allocate to this PF. */ 6043#define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4 6044/* Number of interrupt vectors to allocate per VF. */ 6045#define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8 6046 6047/* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */ 6048#define MC_CMD_SET_VECTOR_CFG_OUT_LEN 0 6049 6050 6051/***********************************/ 6052/* MC_CMD_RMON_RX_CLASS_STATS 6053 * Retrieve rmon rx class statistics 6054 */ 6055#define MC_CMD_RMON_RX_CLASS_STATS 0xc3 6056 6057/* MC_CMD_RMON_RX_CLASS_STATS_IN msgrequest */ 6058#define MC_CMD_RMON_RX_CLASS_STATS_IN_LEN 4 6059/* flags */ 6060#define MC_CMD_RMON_RX_CLASS_STATS_IN_FLAGS_OFST 0 6061#define MC_CMD_RMON_RX_CLASS_STATS_IN_CLASS_LBN 0 6062#define MC_CMD_RMON_RX_CLASS_STATS_IN_CLASS_WIDTH 8 6063#define MC_CMD_RMON_RX_CLASS_STATS_IN_RST_LBN 8 6064#define MC_CMD_RMON_RX_CLASS_STATS_IN_RST_WIDTH 1 6065 6066/* MC_CMD_RMON_RX_CLASS_STATS_OUT msgresponse */ 6067#define MC_CMD_RMON_RX_CLASS_STATS_OUT_LENMIN 4 6068#define MC_CMD_RMON_RX_CLASS_STATS_OUT_LENMAX 252 6069#define MC_CMD_RMON_RX_CLASS_STATS_OUT_LEN(num) (0+4*(num)) 6070/* Array of stats */ 6071#define MC_CMD_RMON_RX_CLASS_STATS_OUT_BUFFER_OFST 0 6072#define MC_CMD_RMON_RX_CLASS_STATS_OUT_BUFFER_LEN 4 6073#define MC_CMD_RMON_RX_CLASS_STATS_OUT_BUFFER_MINNUM 1 6074#define MC_CMD_RMON_RX_CLASS_STATS_OUT_BUFFER_MAXNUM 63 6075 6076 6077/***********************************/ 6078/* MC_CMD_RMON_TX_CLASS_STATS 6079 * Retrieve rmon tx class statistics 6080 */ 6081#define MC_CMD_RMON_TX_CLASS_STATS 0xc4 6082 6083/* MC_CMD_RMON_TX_CLASS_STATS_IN msgrequest */ 6084#define MC_CMD_RMON_TX_CLASS_STATS_IN_LEN 4 6085/* flags */ 6086#define MC_CMD_RMON_TX_CLASS_STATS_IN_FLAGS_OFST 0 6087#define MC_CMD_RMON_TX_CLASS_STATS_IN_CLASS_LBN 0 6088#define MC_CMD_RMON_TX_CLASS_STATS_IN_CLASS_WIDTH 8 6089#define MC_CMD_RMON_TX_CLASS_STATS_IN_RST_LBN 8 6090#define MC_CMD_RMON_TX_CLASS_STATS_IN_RST_WIDTH 1 6091 6092/* MC_CMD_RMON_TX_CLASS_STATS_OUT msgresponse */ 6093#define MC_CMD_RMON_TX_CLASS_STATS_OUT_LENMIN 4 6094#define MC_CMD_RMON_TX_CLASS_STATS_OUT_LENMAX 252 6095#define MC_CMD_RMON_TX_CLASS_STATS_OUT_LEN(num) (0+4*(num)) 6096/* Array of stats */ 6097#define MC_CMD_RMON_TX_CLASS_STATS_OUT_BUFFER_OFST 0 6098#define MC_CMD_RMON_TX_CLASS_STATS_OUT_BUFFER_LEN 4 6099#define MC_CMD_RMON_TX_CLASS_STATS_OUT_BUFFER_MINNUM 1 6100#define MC_CMD_RMON_TX_CLASS_STATS_OUT_BUFFER_MAXNUM 63 6101 6102 6103/***********************************/ 6104/* MC_CMD_RMON_RX_SUPER_CLASS_STATS 6105 * Retrieve rmon rx super_class statistics 6106 */ 6107#define MC_CMD_RMON_RX_SUPER_CLASS_STATS 0xc5 6108 6109/* MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN msgrequest */ 6110#define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_LEN 4 6111/* flags */ 6112#define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_FLAGS_OFST 0 6113#define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_SUPER_CLASS_LBN 0 6114#define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_SUPER_CLASS_WIDTH 4 6115#define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_RST_LBN 4 6116#define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_RST_WIDTH 1 6117 6118/* MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT msgresponse */ 6119#define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_LENMIN 4 6120#define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_LENMAX 252 6121#define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_LEN(num) (0+4*(num)) 6122/* Array of stats */ 6123#define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_BUFFER_OFST 0 6124#define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_BUFFER_LEN 4 6125#define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_BUFFER_MINNUM 1 6126#define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_BUFFER_MAXNUM 63 6127 6128 6129/***********************************/ 6130/* MC_CMD_RMON_TX_SUPER_CLASS_STATS 6131 * Retrieve rmon tx super_class statistics 6132 */ 6133#define MC_CMD_RMON_TX_SUPER_CLASS_STATS 0xc6 6134 6135/* MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN msgrequest */ 6136#define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_LEN 4 6137/* flags */ 6138#define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_FLAGS_OFST 0 6139#define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_SUPER_CLASS_LBN 0 6140#define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_SUPER_CLASS_WIDTH 4 6141#define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_RST_LBN 4 6142#define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_RST_WIDTH 1 6143 6144/* MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT msgresponse */ 6145#define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_LENMIN 4 6146#define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_LENMAX 252 6147#define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_LEN(num) (0+4*(num)) 6148/* Array of stats */ 6149#define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_BUFFER_OFST 0 6150#define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_BUFFER_LEN 4 6151#define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_BUFFER_MINNUM 1 6152#define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_BUFFER_MAXNUM 63 6153 6154 6155/***********************************/ 6156/* MC_CMD_RMON_RX_ADD_QID_TO_CLASS 6157 * Add qid to class for statistics collection 6158 */ 6159#define MC_CMD_RMON_RX_ADD_QID_TO_CLASS 0xc7 6160 6161/* MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN msgrequest */ 6162#define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_LEN 12 6163/* class */ 6164#define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_CLASS_OFST 0 6165/* qid */ 6166#define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_QID_OFST 4 6167/* flags */ 6168#define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_FLAGS_OFST 8 6169#define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_SUPER_CLASS_LBN 0 6170#define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_SUPER_CLASS_WIDTH 4 6171#define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_PE_DELTA_LBN 4 6172#define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_PE_DELTA_WIDTH 4 6173#define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_MTU_LBN 8 6174#define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_MTU_WIDTH 14 6175 6176/* MC_CMD_RMON_RX_ADD_QID_TO_CLASS_OUT msgresponse */ 6177#define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_OUT_LEN 0 6178 6179 6180/***********************************/ 6181/* MC_CMD_RMON_TX_ADD_QID_TO_CLASS 6182 * Add qid to class for statistics collection 6183 */ 6184#define MC_CMD_RMON_TX_ADD_QID_TO_CLASS 0xc8 6185 6186/* MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN msgrequest */ 6187#define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_LEN 12 6188/* class */ 6189#define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_CLASS_OFST 0 6190/* qid */ 6191#define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_QID_OFST 4 6192/* flags */ 6193#define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_FLAGS_OFST 8 6194#define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_SUPER_CLASS_LBN 0 6195#define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_SUPER_CLASS_WIDTH 4 6196#define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_PE_DELTA_LBN 4 6197#define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_PE_DELTA_WIDTH 4 6198#define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_MTU_LBN 8 6199#define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_MTU_WIDTH 14 6200 6201/* MC_CMD_RMON_TX_ADD_QID_TO_CLASS_OUT msgresponse */ 6202#define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_OUT_LEN 0 6203 6204 6205/***********************************/ 6206/* MC_CMD_RMON_MC_ADD_QID_TO_CLASS 6207 * Add qid to class for statistics collection 6208 */ 6209#define MC_CMD_RMON_MC_ADD_QID_TO_CLASS 0xc9 6210 6211/* MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN msgrequest */ 6212#define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_LEN 12 6213/* class */ 6214#define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_CLASS_OFST 0 6215/* qid */ 6216#define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_QID_OFST 4 6217/* flags */ 6218#define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_FLAGS_OFST 8 6219#define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_SUPER_CLASS_LBN 0 6220#define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_SUPER_CLASS_WIDTH 4 6221#define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_PE_DELTA_LBN 4 6222#define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_PE_DELTA_WIDTH 4 6223#define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_MTU_LBN 8 6224#define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_MTU_WIDTH 14 6225 6226/* MC_CMD_RMON_MC_ADD_QID_TO_CLASS_OUT msgresponse */ 6227#define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_OUT_LEN 0 6228 6229 6230/***********************************/ 6231/* MC_CMD_RMON_ALLOC_CLASS 6232 * Allocate an rmon class 6233 */ 6234#define MC_CMD_RMON_ALLOC_CLASS 0xca 6235 6236/* MC_CMD_RMON_ALLOC_CLASS_IN msgrequest */ 6237#define MC_CMD_RMON_ALLOC_CLASS_IN_LEN 0 6238 6239/* MC_CMD_RMON_ALLOC_CLASS_OUT msgresponse */ 6240#define MC_CMD_RMON_ALLOC_CLASS_OUT_LEN 4 6241/* class */ 6242#define MC_CMD_RMON_ALLOC_CLASS_OUT_CLASS_OFST 0 6243 6244 6245/***********************************/ 6246/* MC_CMD_RMON_DEALLOC_CLASS 6247 * Deallocate an rmon class 6248 */ 6249#define MC_CMD_RMON_DEALLOC_CLASS 0xcb 6250 6251/* MC_CMD_RMON_DEALLOC_CLASS_IN msgrequest */ 6252#define MC_CMD_RMON_DEALLOC_CLASS_IN_LEN 4 6253/* class */ 6254#define MC_CMD_RMON_DEALLOC_CLASS_IN_CLASS_OFST 0 6255 6256/* MC_CMD_RMON_DEALLOC_CLASS_OUT msgresponse */ 6257#define MC_CMD_RMON_DEALLOC_CLASS_OUT_LEN 0 6258 6259 6260/***********************************/ 6261/* MC_CMD_RMON_ALLOC_SUPER_CLASS 6262 * Allocate an rmon super_class 6263 */ 6264#define MC_CMD_RMON_ALLOC_SUPER_CLASS 0xcc 6265 6266/* MC_CMD_RMON_ALLOC_SUPER_CLASS_IN msgrequest */ 6267#define MC_CMD_RMON_ALLOC_SUPER_CLASS_IN_LEN 0 6268 6269/* MC_CMD_RMON_ALLOC_SUPER_CLASS_OUT msgresponse */ 6270#define MC_CMD_RMON_ALLOC_SUPER_CLASS_OUT_LEN 4 6271/* super_class */ 6272#define MC_CMD_RMON_ALLOC_SUPER_CLASS_OUT_SUPER_CLASS_OFST 0 6273 6274 6275/***********************************/ 6276/* MC_CMD_RMON_DEALLOC_SUPER_CLASS 6277 * Deallocate an rmon tx super_class 6278 */ 6279#define MC_CMD_RMON_DEALLOC_SUPER_CLASS 0xcd 6280 6281/* MC_CMD_RMON_DEALLOC_SUPER_CLASS_IN msgrequest */ 6282#define MC_CMD_RMON_DEALLOC_SUPER_CLASS_IN_LEN 4 6283/* super_class */ 6284#define MC_CMD_RMON_DEALLOC_SUPER_CLASS_IN_SUPER_CLASS_OFST 0 6285 6286/* MC_CMD_RMON_DEALLOC_SUPER_CLASS_OUT msgresponse */ 6287#define MC_CMD_RMON_DEALLOC_SUPER_CLASS_OUT_LEN 0 6288 6289 6290/***********************************/ 6291/* MC_CMD_RMON_RX_UP_CONV_STATS 6292 * Retrieve up converter statistics 6293 */ 6294#define MC_CMD_RMON_RX_UP_CONV_STATS 0xce 6295 6296/* MC_CMD_RMON_RX_UP_CONV_STATS_IN msgrequest */ 6297#define MC_CMD_RMON_RX_UP_CONV_STATS_IN_LEN 4 6298/* flags */ 6299#define MC_CMD_RMON_RX_UP_CONV_STATS_IN_FLAGS_OFST 0 6300#define MC_CMD_RMON_RX_UP_CONV_STATS_IN_PORT_LBN 0 6301#define MC_CMD_RMON_RX_UP_CONV_STATS_IN_PORT_WIDTH 2 6302#define MC_CMD_RMON_RX_UP_CONV_STATS_IN_RST_LBN 2 6303#define MC_CMD_RMON_RX_UP_CONV_STATS_IN_RST_WIDTH 1 6304 6305/* MC_CMD_RMON_RX_UP_CONV_STATS_OUT msgresponse */ 6306#define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_LENMIN 4 6307#define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_LENMAX 252 6308#define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_LEN(num) (0+4*(num)) 6309/* Array of stats */ 6310#define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_BUFFER_OFST 0 6311#define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_BUFFER_LEN 4 6312#define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_BUFFER_MINNUM 1 6313#define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_BUFFER_MAXNUM 63 6314 6315 6316/***********************************/ 6317/* MC_CMD_RMON_RX_IPI_STATS 6318 * Retrieve rx ipi stats 6319 */ 6320#define MC_CMD_RMON_RX_IPI_STATS 0xcf 6321 6322/* MC_CMD_RMON_RX_IPI_STATS_IN msgrequest */ 6323#define MC_CMD_RMON_RX_IPI_STATS_IN_LEN 4 6324/* flags */ 6325#define MC_CMD_RMON_RX_IPI_STATS_IN_FLAGS_OFST 0 6326#define MC_CMD_RMON_RX_IPI_STATS_IN_VFIFO_LBN 0 6327#define MC_CMD_RMON_RX_IPI_STATS_IN_VFIFO_WIDTH 5 6328#define MC_CMD_RMON_RX_IPI_STATS_IN_RST_LBN 5 6329#define MC_CMD_RMON_RX_IPI_STATS_IN_RST_WIDTH 1 6330 6331/* MC_CMD_RMON_RX_IPI_STATS_OUT msgresponse */ 6332#define MC_CMD_RMON_RX_IPI_STATS_OUT_LENMIN 4 6333#define MC_CMD_RMON_RX_IPI_STATS_OUT_LENMAX 252 6334#define MC_CMD_RMON_RX_IPI_STATS_OUT_LEN(num) (0+4*(num)) 6335/* Array of stats */ 6336#define MC_CMD_RMON_RX_IPI_STATS_OUT_BUFFER_OFST 0 6337#define MC_CMD_RMON_RX_IPI_STATS_OUT_BUFFER_LEN 4 6338#define MC_CMD_RMON_RX_IPI_STATS_OUT_BUFFER_MINNUM 1 6339#define MC_CMD_RMON_RX_IPI_STATS_OUT_BUFFER_MAXNUM 63 6340 6341 6342/***********************************/ 6343/* MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS 6344 * Retrieve rx ipsec cntxt_ptr indexed stats 6345 */ 6346#define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS 0xd0 6347 6348/* MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN msgrequest */ 6349#define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_LEN 4 6350/* flags */ 6351#define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_FLAGS_OFST 0 6352#define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_CNTXT_PTR_LBN 0 6353#define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_CNTXT_PTR_WIDTH 9 6354#define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_RST_LBN 9 6355#define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_RST_WIDTH 1 6356 6357/* MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT msgresponse */ 6358#define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_LENMIN 4 6359#define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_LENMAX 252 6360#define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_LEN(num) (0+4*(num)) 6361/* Array of stats */ 6362#define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_OFST 0 6363#define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_LEN 4 6364#define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_MINNUM 1 6365#define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_MAXNUM 63 6366 6367 6368/***********************************/ 6369/* MC_CMD_RMON_RX_IPSEC_PORT_STATS 6370 * Retrieve rx ipsec port indexed stats 6371 */ 6372#define MC_CMD_RMON_RX_IPSEC_PORT_STATS 0xd1 6373 6374/* MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN msgrequest */ 6375#define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_LEN 4 6376/* flags */ 6377#define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_FLAGS_OFST 0 6378#define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_PORT_LBN 0 6379#define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_PORT_WIDTH 2 6380#define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_RST_LBN 2 6381#define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_RST_WIDTH 1 6382 6383/* MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT msgresponse */ 6384#define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_LENMIN 4 6385#define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_LENMAX 252 6386#define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_LEN(num) (0+4*(num)) 6387/* Array of stats */ 6388#define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_BUFFER_OFST 0 6389#define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_BUFFER_LEN 4 6390#define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_BUFFER_MINNUM 1 6391#define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_BUFFER_MAXNUM 63 6392 6393 6394/***********************************/ 6395/* MC_CMD_RMON_RX_IPSEC_OFLOW_STATS 6396 * Retrieve tx ipsec overflow 6397 */ 6398#define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS 0xd2 6399 6400/* MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN msgrequest */ 6401#define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_LEN 4 6402/* flags */ 6403#define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_FLAGS_OFST 0 6404#define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_PORT_LBN 0 6405#define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_PORT_WIDTH 2 6406#define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_RST_LBN 2 6407#define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_RST_WIDTH 1 6408 6409/* MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT msgresponse */ 6410#define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_LENMIN 4 6411#define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_LENMAX 252 6412#define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_LEN(num) (0+4*(num)) 6413/* Array of stats */ 6414#define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_BUFFER_OFST 0 6415#define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_BUFFER_LEN 4 6416#define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_BUFFER_MINNUM 1 6417#define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_BUFFER_MAXNUM 63 6418 6419 6420/***********************************/ 6421/* MC_CMD_VPORT_ADD_MAC_ADDRESS 6422 * Add a MAC address to a v-port 6423 */ 6424#define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8 6425 6426/* MC_CMD_VPORT_ADD_MAC_ADDRESS_IN msgrequest */ 6427#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN 10 6428/* The handle of the v-port */ 6429#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0 6430/* MAC address to add */ 6431#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4 6432#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_LEN 6 6433 6434/* MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT msgresponse */ 6435#define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0 6436 6437 6438/***********************************/ 6439/* MC_CMD_VPORT_DEL_MAC_ADDRESS 6440 * Delete a MAC address from a v-port 6441 */ 6442#define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9 6443 6444/* MC_CMD_VPORT_DEL_MAC_ADDRESS_IN msgrequest */ 6445#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN 10 6446/* The handle of the v-port */ 6447#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0 6448/* MAC address to add */ 6449#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4 6450#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_LEN 6 6451 6452/* MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT msgresponse */ 6453#define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0 6454 6455 6456/***********************************/ 6457/* MC_CMD_VPORT_GET_MAC_ADDRESSES 6458 * Delete a MAC address from a v-port 6459 */ 6460#define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa 6461 6462/* MC_CMD_VPORT_GET_MAC_ADDRESSES_IN msgrequest */ 6463#define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4 6464/* The handle of the v-port */ 6465#define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0 6466 6467/* MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT msgresponse */ 6468#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4 6469#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX 250 6470#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num)) 6471/* The number of MAC addresses returned */ 6472#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0 6473/* Array of MAC addresses */ 6474#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4 6475#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_LEN 6 6476#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0 6477#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM 41 6478 6479 6480/***********************************/ 6481/* MC_CMD_DUMP_BUFTBL_ENTRIES 6482 * Dump buffer table entries, mainly for command client debug use. Dumps 6483 * absolute entries, and does not use chunk handles. All entries must be in 6484 * range, and used for q page mapping, Although the latter restriction may be 6485 * lifted in future. 6486 */ 6487#define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab 6488 6489/* MC_CMD_DUMP_BUFTBL_ENTRIES_IN msgrequest */ 6490#define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_LEN 8 6491/* Index of the first buffer table entry. */ 6492#define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_OFST 0 6493/* Number of buffer table entries to dump. */ 6494#define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 4 6495 6496/* MC_CMD_DUMP_BUFTBL_ENTRIES_OUT msgresponse */ 6497#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMIN 12 6498#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX 252 6499#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num)) 6500/* Raw buffer table entries, laid out as BUFTBL_ENTRY. */ 6501#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0 6502#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_LEN 12 6503#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1 6504#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM 21 6505 6506 6507/***********************************/ 6508/* MC_CMD_SET_RXDP_CONFIG 6509 * Set global RXDP configuration settings 6510 */ 6511#define MC_CMD_SET_RXDP_CONFIG 0xc1 6512 6513/* MC_CMD_SET_RXDP_CONFIG_IN msgrequest */ 6514#define MC_CMD_SET_RXDP_CONFIG_IN_LEN 4 6515#define MC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0 6516#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0 6517#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1 6518 6519/* MC_CMD_SET_RXDP_CONFIG_OUT msgresponse */ 6520#define MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0 6521 6522 6523/***********************************/ 6524/* MC_CMD_GET_RXDP_CONFIG 6525 * Get global RXDP configuration settings 6526 */ 6527#define MC_CMD_GET_RXDP_CONFIG 0xc2 6528 6529/* MC_CMD_GET_RXDP_CONFIG_IN msgrequest */ 6530#define MC_CMD_GET_RXDP_CONFIG_IN_LEN 0 6531 6532/* MC_CMD_GET_RXDP_CONFIG_OUT msgresponse */ 6533#define MC_CMD_GET_RXDP_CONFIG_OUT_LEN 4 6534#define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0 6535#define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0 6536#define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1 6537 6538 6539/***********************************/ 6540/* MC_CMD_RMON_RX_CLASS_DROPS_STATS 6541 * Retrieve rx class drop stats 6542 */ 6543#define MC_CMD_RMON_RX_CLASS_DROPS_STATS 0xd3 6544 6545/* MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN msgrequest */ 6546#define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_LEN 4 6547/* flags */ 6548#define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_FLAGS_OFST 0 6549#define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_CLASS_LBN 0 6550#define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_CLASS_WIDTH 8 6551#define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_RST_LBN 8 6552#define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_RST_WIDTH 1 6553 6554/* MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT msgresponse */ 6555#define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_LENMIN 4 6556#define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_LENMAX 252 6557#define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_LEN(num) (0+4*(num)) 6558/* Array of stats */ 6559#define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_BUFFER_OFST 0 6560#define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_BUFFER_LEN 4 6561#define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_BUFFER_MINNUM 1 6562#define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_BUFFER_MAXNUM 63 6563 6564 6565/***********************************/ 6566/* MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS 6567 * Retrieve rx super class drop stats 6568 */ 6569#define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS 0xd4 6570 6571/* MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN msgrequest */ 6572#define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_LEN 4 6573/* flags */ 6574#define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_FLAGS_OFST 0 6575#define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_SUPER_CLASS_LBN 0 6576#define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_SUPER_CLASS_WIDTH 4 6577#define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_RST_LBN 4 6578#define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_RST_WIDTH 1 6579 6580/* MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT msgresponse */ 6581#define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_LENMIN 4 6582#define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_LENMAX 252 6583#define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_LEN(num) (0+4*(num)) 6584/* Array of stats */ 6585#define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_BUFFER_OFST 0 6586#define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_BUFFER_LEN 4 6587#define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_BUFFER_MINNUM 1 6588#define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_BUFFER_MAXNUM 63 6589 6590 6591/***********************************/ 6592/* MC_CMD_RMON_RX_ERRORS_STATS 6593 * Retrieve rxdp errors 6594 */ 6595#define MC_CMD_RMON_RX_ERRORS_STATS 0xd5 6596 6597/* MC_CMD_RMON_RX_ERRORS_STATS_IN msgrequest */ 6598#define MC_CMD_RMON_RX_ERRORS_STATS_IN_LEN 4 6599/* flags */ 6600#define MC_CMD_RMON_RX_ERRORS_STATS_IN_FLAGS_OFST 0 6601#define MC_CMD_RMON_RX_ERRORS_STATS_IN_QID_LBN 0 6602#define MC_CMD_RMON_RX_ERRORS_STATS_IN_QID_WIDTH 11 6603#define MC_CMD_RMON_RX_ERRORS_STATS_IN_RST_LBN 11 6604#define MC_CMD_RMON_RX_ERRORS_STATS_IN_RST_WIDTH 1 6605 6606/* MC_CMD_RMON_RX_ERRORS_STATS_OUT msgresponse */ 6607#define MC_CMD_RMON_RX_ERRORS_STATS_OUT_LENMIN 4 6608#define MC_CMD_RMON_RX_ERRORS_STATS_OUT_LENMAX 252 6609#define MC_CMD_RMON_RX_ERRORS_STATS_OUT_LEN(num) (0+4*(num)) 6610/* Array of stats */ 6611#define MC_CMD_RMON_RX_ERRORS_STATS_OUT_BUFFER_OFST 0 6612#define MC_CMD_RMON_RX_ERRORS_STATS_OUT_BUFFER_LEN 4 6613#define MC_CMD_RMON_RX_ERRORS_STATS_OUT_BUFFER_MINNUM 1 6614#define MC_CMD_RMON_RX_ERRORS_STATS_OUT_BUFFER_MAXNUM 63 6615 6616 6617/***********************************/ 6618/* MC_CMD_RMON_RX_OVERFLOW_STATS 6619 * Retrieve rxdp overflow 6620 */ 6621#define MC_CMD_RMON_RX_OVERFLOW_STATS 0xd6 6622 6623/* MC_CMD_RMON_RX_OVERFLOW_STATS_IN msgrequest */ 6624#define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_LEN 4 6625/* flags */ 6626#define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_FLAGS_OFST 0 6627#define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_CLASS_LBN 0 6628#define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_CLASS_WIDTH 8 6629#define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_RST_LBN 8 6630#define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_RST_WIDTH 1 6631 6632/* MC_CMD_RMON_RX_OVERFLOW_STATS_OUT msgresponse */ 6633#define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_LENMIN 4 6634#define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_LENMAX 252 6635#define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_LEN(num) (0+4*(num)) 6636/* Array of stats */ 6637#define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_BUFFER_OFST 0 6638#define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_BUFFER_LEN 4 6639#define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_BUFFER_MINNUM 1 6640#define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_BUFFER_MAXNUM 63 6641 6642 6643/***********************************/ 6644/* MC_CMD_RMON_TX_IPI_STATS 6645 * Retrieve tx ipi stats 6646 */ 6647#define MC_CMD_RMON_TX_IPI_STATS 0xd7 6648 6649/* MC_CMD_RMON_TX_IPI_STATS_IN msgrequest */ 6650#define MC_CMD_RMON_TX_IPI_STATS_IN_LEN 4 6651/* flags */ 6652#define MC_CMD_RMON_TX_IPI_STATS_IN_FLAGS_OFST 0 6653#define MC_CMD_RMON_TX_IPI_STATS_IN_VFIFO_LBN 0 6654#define MC_CMD_RMON_TX_IPI_STATS_IN_VFIFO_WIDTH 5 6655#define MC_CMD_RMON_TX_IPI_STATS_IN_RST_LBN 5 6656#define MC_CMD_RMON_TX_IPI_STATS_IN_RST_WIDTH 1 6657 6658/* MC_CMD_RMON_TX_IPI_STATS_OUT msgresponse */ 6659#define MC_CMD_RMON_TX_IPI_STATS_OUT_LENMIN 4 6660#define MC_CMD_RMON_TX_IPI_STATS_OUT_LENMAX 252 6661#define MC_CMD_RMON_TX_IPI_STATS_OUT_LEN(num) (0+4*(num)) 6662/* Array of stats */ 6663#define MC_CMD_RMON_TX_IPI_STATS_OUT_BUFFER_OFST 0 6664#define MC_CMD_RMON_TX_IPI_STATS_OUT_BUFFER_LEN 4 6665#define MC_CMD_RMON_TX_IPI_STATS_OUT_BUFFER_MINNUM 1 6666#define MC_CMD_RMON_TX_IPI_STATS_OUT_BUFFER_MAXNUM 63 6667 6668 6669/***********************************/ 6670/* MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS 6671 * Retrieve tx ipsec counters by cntxt_ptr 6672 */ 6673#define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS 0xd8 6674 6675/* MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN msgrequest */ 6676#define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_LEN 4 6677/* flags */ 6678#define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_FLAGS_OFST 0 6679#define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_CNTXT_PTR_LBN 0 6680#define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_CNTXT_PTR_WIDTH 9 6681#define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_RST_LBN 9 6682#define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_RST_WIDTH 1 6683 6684/* MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT msgresponse */ 6685#define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_LENMIN 4 6686#define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_LENMAX 252 6687#define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_LEN(num) (0+4*(num)) 6688/* Array of stats */ 6689#define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_OFST 0 6690#define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_LEN 4 6691#define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_MINNUM 1 6692#define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_MAXNUM 63 6693 6694 6695/***********************************/ 6696/* MC_CMD_RMON_TX_IPSEC_PORT_STATS 6697 * Retrieve tx ipsec counters by port 6698 */ 6699#define MC_CMD_RMON_TX_IPSEC_PORT_STATS 0xd9 6700 6701/* MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN msgrequest */ 6702#define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_LEN 4 6703/* flags */ 6704#define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_FLAGS_OFST 0 6705#define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_PORT_LBN 0 6706#define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_PORT_WIDTH 2 6707#define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_RST_LBN 2 6708#define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_RST_WIDTH 1 6709 6710/* MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT msgresponse */ 6711#define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_LENMIN 4 6712#define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_LENMAX 252 6713#define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_LEN(num) (0+4*(num)) 6714/* Array of stats */ 6715#define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_BUFFER_OFST 0 6716#define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_BUFFER_LEN 4 6717#define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_BUFFER_MINNUM 1 6718#define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_BUFFER_MAXNUM 63 6719 6720 6721/***********************************/ 6722/* MC_CMD_RMON_TX_IPSEC_OFLOW_STATS 6723 * Retrieve tx ipsec overflow 6724 */ 6725#define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS 0xda 6726 6727/* MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN msgrequest */ 6728#define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_LEN 4 6729/* flags */ 6730#define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_FLAGS_OFST 0 6731#define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_PORT_LBN 0 6732#define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_PORT_WIDTH 2 6733#define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_RST_LBN 2 6734#define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_RST_WIDTH 1 6735 6736/* MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT msgresponse */ 6737#define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_LENMIN 4 6738#define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_LENMAX 252 6739#define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_LEN(num) (0+4*(num)) 6740/* Array of stats */ 6741#define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_BUFFER_OFST 0 6742#define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_BUFFER_LEN 4 6743#define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_BUFFER_MINNUM 1 6744#define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_BUFFER_MAXNUM 63 6745 6746 6747/***********************************/ 6748/* MC_CMD_RMON_TX_NOWHERE_STATS 6749 * Retrieve tx nowhere stats 6750 */ 6751#define MC_CMD_RMON_TX_NOWHERE_STATS 0xdb 6752 6753/* MC_CMD_RMON_TX_NOWHERE_STATS_IN msgrequest */ 6754#define MC_CMD_RMON_TX_NOWHERE_STATS_IN_LEN 4 6755/* flags */ 6756#define MC_CMD_RMON_TX_NOWHERE_STATS_IN_FLAGS_OFST 0 6757#define MC_CMD_RMON_TX_NOWHERE_STATS_IN_CLASS_LBN 0 6758#define MC_CMD_RMON_TX_NOWHERE_STATS_IN_CLASS_WIDTH 8 6759#define MC_CMD_RMON_TX_NOWHERE_STATS_IN_RST_LBN 8 6760#define MC_CMD_RMON_TX_NOWHERE_STATS_IN_RST_WIDTH 1 6761 6762/* MC_CMD_RMON_TX_NOWHERE_STATS_OUT msgresponse */ 6763#define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_LENMIN 4 6764#define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_LENMAX 252 6765#define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_LEN(num) (0+4*(num)) 6766/* Array of stats */ 6767#define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_BUFFER_OFST 0 6768#define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_BUFFER_LEN 4 6769#define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_BUFFER_MINNUM 1 6770#define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_BUFFER_MAXNUM 63 6771 6772 6773/***********************************/ 6774/* MC_CMD_RMON_TX_NOWHERE_QBB_STATS 6775 * Retrieve tx nowhere qbb stats 6776 */ 6777#define MC_CMD_RMON_TX_NOWHERE_QBB_STATS 0xdc 6778 6779/* MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN msgrequest */ 6780#define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_LEN 4 6781/* flags */ 6782#define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_FLAGS_OFST 0 6783#define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_PRIORITY_LBN 0 6784#define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_PRIORITY_WIDTH 3 6785#define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_RST_LBN 3 6786#define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_RST_WIDTH 1 6787 6788/* MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT msgresponse */ 6789#define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_LENMIN 4 6790#define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_LENMAX 252 6791#define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_LEN(num) (0+4*(num)) 6792/* Array of stats */ 6793#define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_BUFFER_OFST 0 6794#define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_BUFFER_LEN 4 6795#define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_BUFFER_MINNUM 1 6796#define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_BUFFER_MAXNUM 63 6797 6798 6799/***********************************/ 6800/* MC_CMD_RMON_TX_ERRORS_STATS 6801 * Retrieve rxdp errors 6802 */ 6803#define MC_CMD_RMON_TX_ERRORS_STATS 0xdd 6804 6805/* MC_CMD_RMON_TX_ERRORS_STATS_IN msgrequest */ 6806#define MC_CMD_RMON_TX_ERRORS_STATS_IN_LEN 4 6807/* flags */ 6808#define MC_CMD_RMON_TX_ERRORS_STATS_IN_FLAGS_OFST 0 6809#define MC_CMD_RMON_TX_ERRORS_STATS_IN_QID_LBN 0 6810#define MC_CMD_RMON_TX_ERRORS_STATS_IN_QID_WIDTH 11 6811#define MC_CMD_RMON_TX_ERRORS_STATS_IN_RST_LBN 11 6812#define MC_CMD_RMON_TX_ERRORS_STATS_IN_RST_WIDTH 1 6813 6814/* MC_CMD_RMON_TX_ERRORS_STATS_OUT msgresponse */ 6815#define MC_CMD_RMON_TX_ERRORS_STATS_OUT_LENMIN 4 6816#define MC_CMD_RMON_TX_ERRORS_STATS_OUT_LENMAX 252 6817#define MC_CMD_RMON_TX_ERRORS_STATS_OUT_LEN(num) (0+4*(num)) 6818/* Array of stats */ 6819#define MC_CMD_RMON_TX_ERRORS_STATS_OUT_BUFFER_OFST 0 6820#define MC_CMD_RMON_TX_ERRORS_STATS_OUT_BUFFER_LEN 4 6821#define MC_CMD_RMON_TX_ERRORS_STATS_OUT_BUFFER_MINNUM 1 6822#define MC_CMD_RMON_TX_ERRORS_STATS_OUT_BUFFER_MAXNUM 63 6823 6824 6825/***********************************/ 6826/* MC_CMD_RMON_TX_OVERFLOW_STATS 6827 * Retrieve rxdp overflow 6828 */ 6829#define MC_CMD_RMON_TX_OVERFLOW_STATS 0xde 6830 6831/* MC_CMD_RMON_TX_OVERFLOW_STATS_IN msgrequest */ 6832#define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_LEN 4 6833/* flags */ 6834#define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_FLAGS_OFST 0 6835#define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_CLASS_LBN 0 6836#define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_CLASS_WIDTH 8 6837#define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_RST_LBN 8 6838#define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_RST_WIDTH 1 6839 6840/* MC_CMD_RMON_TX_OVERFLOW_STATS_OUT msgresponse */ 6841#define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_LENMIN 4 6842#define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_LENMAX 252 6843#define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_LEN(num) (0+4*(num)) 6844/* Array of stats */ 6845#define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_BUFFER_OFST 0 6846#define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_BUFFER_LEN 4 6847#define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_BUFFER_MINNUM 1 6848#define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_BUFFER_MAXNUM 63 6849 6850 6851/***********************************/ 6852/* MC_CMD_RMON_COLLECT_CLASS_STATS 6853 * Explicitly collect class stats at the specified evb port 6854 */ 6855#define MC_CMD_RMON_COLLECT_CLASS_STATS 0xdf 6856 6857/* MC_CMD_RMON_COLLECT_CLASS_STATS_IN msgrequest */ 6858#define MC_CMD_RMON_COLLECT_CLASS_STATS_IN_LEN 4 6859/* The port id associated with the vport/pport at which to collect class stats 6860 */ 6861#define MC_CMD_RMON_COLLECT_CLASS_STATS_IN_PORT_ID_OFST 0 6862 6863/* MC_CMD_RMON_COLLECT_CLASS_STATS_OUT msgresponse */ 6864#define MC_CMD_RMON_COLLECT_CLASS_STATS_OUT_LEN 4 6865/* class */ 6866#define MC_CMD_RMON_COLLECT_CLASS_STATS_OUT_CLASS_OFST 0 6867 6868 6869/***********************************/ 6870/* MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS 6871 * Explicitly collect class stats at the specified evb port 6872 */ 6873#define MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS 0xe0 6874 6875/* MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_IN msgrequest */ 6876#define MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_IN_LEN 4 6877/* The port id associated with the vport/pport at which to collect class stats 6878 */ 6879#define MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_IN_PORT_ID_OFST 0 6880 6881/* MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_OUT msgresponse */ 6882#define MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_OUT_LEN 4 6883/* super_class */ 6884#define MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_OUT_SUPER_CLASS_OFST 0 6885 6886 6887/***********************************/ 6888/* MC_CMD_GET_CLOCK 6889 * Return the system and PDCPU clock frequencies. 6890 */ 6891#define MC_CMD_GET_CLOCK 0xac 6892 6893/* MC_CMD_GET_CLOCK_IN msgrequest */ 6894#define MC_CMD_GET_CLOCK_IN_LEN 0 6895 6896/* MC_CMD_GET_CLOCK_OUT msgresponse */ 6897#define MC_CMD_GET_CLOCK_OUT_LEN 8 6898/* System frequency, MHz */ 6899#define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0 6900/* DPCPU frequency, MHz */ 6901#define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4 6902 6903 6904/***********************************/ 6905/* MC_CMD_SET_CLOCK 6906 * Control the system and DPCPU clock frequencies. Changes are lost reboot. 6907 */ 6908#define MC_CMD_SET_CLOCK 0xad 6909 6910/* MC_CMD_SET_CLOCK_IN msgrequest */ 6911#define MC_CMD_SET_CLOCK_IN_LEN 12 6912/* Requested system frequency in MHz; 0 leaves unchanged. */ 6913#define MC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0 6914/* Requested inter-core frequency in MHz; 0 leaves unchanged. */ 6915#define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4 6916/* Request DPCPU frequency in MHz; 0 leaves unchanged. */ 6917#define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_OFST 8 6918 6919/* MC_CMD_SET_CLOCK_OUT msgresponse */ 6920#define MC_CMD_SET_CLOCK_OUT_LEN 12 6921/* Resulting system frequency in MHz */ 6922#define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0 6923/* Resulting inter-core frequency in MHz */ 6924#define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4 6925/* Resulting DPCPU frequency in MHz */ 6926#define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_OFST 8 6927 6928 6929/***********************************/ 6930/* MC_CMD_DPCPU_RPC 6931 * Send an arbitrary DPCPU message. 6932 */ 6933#define MC_CMD_DPCPU_RPC 0xae 6934 6935/* MC_CMD_DPCPU_RPC_IN msgrequest */ 6936#define MC_CMD_DPCPU_RPC_IN_LEN 36 6937#define MC_CMD_DPCPU_RPC_IN_CPU_OFST 0 6938/* enum: RxDPCPU */ 6939#define MC_CMD_DPCPU_RPC_IN_DPCPU_RX 0x0 6940/* enum: TxDPCPU0 */ 6941#define MC_CMD_DPCPU_RPC_IN_DPCPU_TX0 0x1 6942/* enum: TxDPCPU1 */ 6943#define MC_CMD_DPCPU_RPC_IN_DPCPU_TX1 0x2 6944/* First 8 bits [39:32] of DATA are consumed by MC-DPCPU protocol and must be 6945 * initialised to zero 6946 */ 6947#define MC_CMD_DPCPU_RPC_IN_DATA_OFST 4 6948#define MC_CMD_DPCPU_RPC_IN_DATA_LEN 32 6949#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_LBN 8 6950#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_WIDTH 8 6951#define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */ 6952#define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */ 6953#define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */ 6954#define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */ 6955#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */ 6956#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */ 6957#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */ 6958#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */ 6959#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */ 6960#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_LBN 16 6961#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_WIDTH 16 6962#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_LBN 16 6963#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_WIDTH 16 6964#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_LBN 48 6965#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_WIDTH 16 6966#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_LBN 16 6967#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_WIDTH 240 6968#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_LBN 16 6969#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_WIDTH 16 6970#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */ 6971#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */ 6972#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */ 6973#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */ 6974#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */ 6975#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_LBN 48 6976#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_WIDTH 16 6977#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_LBN 64 6978#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_WIDTH 16 6979#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_LBN 80 6980#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_WIDTH 16 6981#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_LBN 16 6982#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_WIDTH 16 6983#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */ 6984#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */ 6985#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */ 6986#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_LBN 64 6987#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_WIDTH 16 6988#define MC_CMD_DPCPU_RPC_IN_WDATA_OFST 12 6989#define MC_CMD_DPCPU_RPC_IN_WDATA_LEN 24 6990/* Register data to write. Only valid in write/write-read. */ 6991#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_OFST 16 6992/* Register address. */ 6993#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_OFST 20 6994 6995/* MC_CMD_DPCPU_RPC_OUT msgresponse */ 6996#define MC_CMD_DPCPU_RPC_OUT_LEN 36 6997#define MC_CMD_DPCPU_RPC_OUT_RC_OFST 0 6998/* DATA */ 6999#define MC_CMD_DPCPU_RPC_OUT_DATA_OFST 4 7000#define MC_CMD_DPCPU_RPC_OUT_DATA_LEN 32 7001#define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_LBN 32 7002#define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_WIDTH 16 7003#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_LBN 48 7004#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_WIDTH 16 7005#define MC_CMD_DPCPU_RPC_OUT_RDATA_OFST 12 7006#define MC_CMD_DPCPU_RPC_OUT_RDATA_LEN 24 7007#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_OFST 12 7008#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_OFST 16 7009#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_OFST 20 7010#define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_OFST 24 7011 7012 7013/***********************************/ 7014/* MC_CMD_TRIGGER_INTERRUPT 7015 * Trigger an interrupt by prodding the BIU. 7016 */ 7017#define MC_CMD_TRIGGER_INTERRUPT 0xe3 7018 7019/* MC_CMD_TRIGGER_INTERRUPT_IN msgrequest */ 7020#define MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4 7021/* Interrupt level relative to base for function. */ 7022#define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0 7023 7024/* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */ 7025#define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0 7026 7027 7028/***********************************/ 7029/* MC_CMD_CAP_BLK_READ 7030 * Read multiple 64bit words from capture block memory 7031 */ 7032#define MC_CMD_CAP_BLK_READ 0xe7 7033 7034/* MC_CMD_CAP_BLK_READ_IN msgrequest */ 7035#define MC_CMD_CAP_BLK_READ_IN_LEN 12 7036#define MC_CMD_CAP_BLK_READ_IN_CAP_REG_OFST 0 7037#define MC_CMD_CAP_BLK_READ_IN_ADDR_OFST 4 7038#define MC_CMD_CAP_BLK_READ_IN_COUNT_OFST 8 7039 7040/* MC_CMD_CAP_BLK_READ_OUT msgresponse */ 7041#define MC_CMD_CAP_BLK_READ_OUT_LENMIN 8 7042#define MC_CMD_CAP_BLK_READ_OUT_LENMAX 248 7043#define MC_CMD_CAP_BLK_READ_OUT_LEN(num) (0+8*(num)) 7044#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0 7045#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LEN 8 7046#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0 7047#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4 7048#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1 7049#define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM 31 7050 7051 7052/***********************************/ 7053/* MC_CMD_DUMP_DO 7054 * Take a dump of the DUT state 7055 */ 7056#define MC_CMD_DUMP_DO 0xe8 7057 7058/* MC_CMD_DUMP_DO_IN msgrequest */ 7059#define MC_CMD_DUMP_DO_IN_LEN 52 7060#define MC_CMD_DUMP_DO_IN_PADDING_OFST 0 7061#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4 7062#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */ 7063#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */ 7064#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 7065#define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */ 7066#define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */ 7067#define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */ 7068#define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */ 7069#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 7070#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 7071#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 7072#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 7073#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 7074#define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */ 7075#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 7076#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 7077#define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */ 7078#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 7079/* enum: The uart port this command was received over (if using a uart 7080 * transport) 7081 */ 7082#define MC_CMD_DUMP_DO_IN_UART_PORT_SRC 0xff 7083#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 7084#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_OFST 28 7085#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */ 7086#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */ 7087#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 7088/* Enum values, see field(s): */ 7089/* MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 7090#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 7091#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 7092#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 7093#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 7094#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 7095#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 7096#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 7097#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 7098#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 7099 7100/* MC_CMD_DUMP_DO_OUT msgresponse */ 7101#define MC_CMD_DUMP_DO_OUT_LEN 4 7102#define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0 7103 7104 7105/***********************************/ 7106/* MC_CMD_DUMP_CONFIGURE_UNSOLICITED 7107 * Configure unsolicited dumps 7108 */ 7109#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9 7110 7111/* MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN msgrequest */ 7112#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_LEN 52 7113#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0 7114#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4 7115/* Enum values, see field(s): */ 7116/* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC */ 7117#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 7118/* Enum values, see field(s): */ 7119/* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 7120#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 7121#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 7122#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 7123#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 7124#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 7125#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 7126#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 7127#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 7128#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 7129#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_OFST 28 7130/* Enum values, see field(s): */ 7131/* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPFILE_DST */ 7132#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 7133/* Enum values, see field(s): */ 7134/* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 7135#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 7136#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 7137#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 7138#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 7139#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 7140#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 7141#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 7142#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 7143#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 7144 7145 7146/***********************************/ 7147/* MC_CMD_SET_PSU 7148 * Adjusts power supply parameters. This is a warranty-voiding operation. 7149 * Returns: ENOENT if the parameter or rail specified does not exist, EINVAL if 7150 * the parameter is out of range. 7151 */ 7152#define MC_CMD_SET_PSU 0xea 7153 7154/* MC_CMD_SET_PSU_IN msgrequest */ 7155#define MC_CMD_SET_PSU_IN_LEN 12 7156#define MC_CMD_SET_PSU_IN_PARAM_OFST 0 7157#define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */ 7158#define MC_CMD_SET_PSU_IN_RAIL_OFST 4 7159#define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */ 7160#define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */ 7161/* desired value, eg voltage in mV */ 7162#define MC_CMD_SET_PSU_IN_VALUE_OFST 8 7163 7164/* MC_CMD_SET_PSU_OUT msgresponse */ 7165#define MC_CMD_SET_PSU_OUT_LEN 0 7166 7167 7168/***********************************/ 7169/* MC_CMD_GET_FUNCTION_INFO 7170 * Get function information. PF and VF number. 7171 */ 7172#define MC_CMD_GET_FUNCTION_INFO 0xec 7173 7174/* MC_CMD_GET_FUNCTION_INFO_IN msgrequest */ 7175#define MC_CMD_GET_FUNCTION_INFO_IN_LEN 0 7176 7177/* MC_CMD_GET_FUNCTION_INFO_OUT msgresponse */ 7178#define MC_CMD_GET_FUNCTION_INFO_OUT_LEN 8 7179#define MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0 7180#define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4 7181 7182 7183/***********************************/ 7184/* MC_CMD_ENABLE_OFFLINE_BIST 7185 * Enters offline BIST mode. All queues are torn down, chip enters quiescent 7186 * mode, calling function gets exclusive MCDI ownership. The only way out is 7187 * reboot. 7188 */ 7189#define MC_CMD_ENABLE_OFFLINE_BIST 0xed 7190 7191/* MC_CMD_ENABLE_OFFLINE_BIST_IN msgrequest */ 7192#define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0 7193 7194/* MC_CMD_ENABLE_OFFLINE_BIST_OUT msgresponse */ 7195#define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0 7196 7197 7198/***********************************/ 7199/* MC_CMD_UART_SEND_DATA 7200 * Send checksummed[sic] block of data over the uart. Response is a placeholder 7201 * should we wish to make this reliable; currently requests are fire-and- 7202 * forget. 7203 */ 7204#define MC_CMD_UART_SEND_DATA 0xee 7205 7206/* MC_CMD_UART_SEND_DATA_OUT msgrequest */ 7207#define MC_CMD_UART_SEND_DATA_OUT_LENMIN 16 7208#define MC_CMD_UART_SEND_DATA_OUT_LENMAX 252 7209#define MC_CMD_UART_SEND_DATA_OUT_LEN(num) (16+1*(num)) 7210/* CRC32 over OFFSET, LENGTH, RESERVED, DATA */ 7211#define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_OFST 0 7212/* Offset at which to write the data */ 7213#define MC_CMD_UART_SEND_DATA_OUT_OFFSET_OFST 4 7214/* Length of data */ 7215#define MC_CMD_UART_SEND_DATA_OUT_LENGTH_OFST 8 7216/* Reserved for future use */ 7217#define MC_CMD_UART_SEND_DATA_OUT_RESERVED_OFST 12 7218#define MC_CMD_UART_SEND_DATA_OUT_DATA_OFST 16 7219#define MC_CMD_UART_SEND_DATA_OUT_DATA_LEN 1 7220#define MC_CMD_UART_SEND_DATA_OUT_DATA_MINNUM 0 7221#define MC_CMD_UART_SEND_DATA_OUT_DATA_MAXNUM 236 7222 7223/* MC_CMD_UART_SEND_DATA_IN msgresponse */ 7224#define MC_CMD_UART_SEND_DATA_IN_LEN 0 7225 7226 7227/***********************************/ 7228/* MC_CMD_UART_RECV_DATA 7229 * Request checksummed[sic] block of data over the uart. Only a placeholder, 7230 * subject to change and not currently implemented. 7231 */ 7232#define MC_CMD_UART_RECV_DATA 0xef 7233 7234/* MC_CMD_UART_RECV_DATA_OUT msgrequest */ 7235#define MC_CMD_UART_RECV_DATA_OUT_LEN 16 7236/* CRC32 over OFFSET, LENGTH, RESERVED */ 7237#define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_OFST 0 7238/* Offset from which to read the data */ 7239#define MC_CMD_UART_RECV_DATA_OUT_OFFSET_OFST 4 7240/* Length of data */ 7241#define MC_CMD_UART_RECV_DATA_OUT_LENGTH_OFST 8 7242/* Reserved for future use */ 7243#define MC_CMD_UART_RECV_DATA_OUT_RESERVED_OFST 12 7244 7245/* MC_CMD_UART_RECV_DATA_IN msgresponse */ 7246#define MC_CMD_UART_RECV_DATA_IN_LENMIN 16 7247#define MC_CMD_UART_RECV_DATA_IN_LENMAX 252 7248#define MC_CMD_UART_RECV_DATA_IN_LEN(num) (16+1*(num)) 7249/* CRC32 over RESERVED1, RESERVED2, RESERVED3, DATA */ 7250#define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_OFST 0 7251/* Offset at which to write the data */ 7252#define MC_CMD_UART_RECV_DATA_IN_RESERVED1_OFST 4 7253/* Length of data */ 7254#define MC_CMD_UART_RECV_DATA_IN_RESERVED2_OFST 8 7255/* Reserved for future use */ 7256#define MC_CMD_UART_RECV_DATA_IN_RESERVED3_OFST 12 7257#define MC_CMD_UART_RECV_DATA_IN_DATA_OFST 16 7258#define MC_CMD_UART_RECV_DATA_IN_DATA_LEN 1 7259#define MC_CMD_UART_RECV_DATA_IN_DATA_MINNUM 0 7260#define MC_CMD_UART_RECV_DATA_IN_DATA_MAXNUM 236 7261 7262 7263/***********************************/ 7264/* MC_CMD_READ_FUSES 7265 * Read data programmed into the device One-Time-Programmable (OTP) Fuses 7266 */ 7267#define MC_CMD_READ_FUSES 0xf0 7268 7269/* MC_CMD_READ_FUSES_IN msgrequest */ 7270#define MC_CMD_READ_FUSES_IN_LEN 8 7271/* Offset in OTP to read */ 7272#define MC_CMD_READ_FUSES_IN_OFFSET_OFST 0 7273/* Length of data to read in bytes */ 7274#define MC_CMD_READ_FUSES_IN_LENGTH_OFST 4 7275 7276/* MC_CMD_READ_FUSES_OUT msgresponse */ 7277#define MC_CMD_READ_FUSES_OUT_LENMIN 4 7278#define MC_CMD_READ_FUSES_OUT_LENMAX 252 7279#define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num)) 7280/* Length of returned OTP data in bytes */ 7281#define MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0 7282/* Returned data */ 7283#define MC_CMD_READ_FUSES_OUT_DATA_OFST 4 7284#define MC_CMD_READ_FUSES_OUT_DATA_LEN 1 7285#define MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0 7286#define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM 248 7287 7288 7289/***********************************/ 7290/* MC_CMD_KR_TUNE 7291 * Get or set KR Serdes RXEQ and TX Driver settings 7292 */ 7293#define MC_CMD_KR_TUNE 0xf1 7294 7295/* MC_CMD_KR_TUNE_IN msgrequest */ 7296#define MC_CMD_KR_TUNE_IN_LENMIN 4 7297#define MC_CMD_KR_TUNE_IN_LENMAX 252 7298#define MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num)) 7299/* Requested operation */ 7300#define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0 7301#define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1 7302/* enum: Get current RXEQ settings */ 7303#define MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0 7304/* enum: Override RXEQ settings */ 7305#define MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1 7306/* enum: Get current TX Driver settings */ 7307#define MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2 7308/* enum: Override TX Driver settings */ 7309#define MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3 7310/* enum: Force KR Serdes reset / recalibration */ 7311#define MC_CMD_KR_TUNE_IN_RECAL 0x4 7312/* enum: Start KR Serdes Eye diagram plot on a given lane. Lane must have valid 7313 * signal. 7314 */ 7315#define MC_CMD_KR_TUNE_IN_START_EYE_PLOT 0x5 7316/* enum: Poll KR Serdes Eye diagram plot. Returns one row of BER data. The 7317 * caller should call this command repeatedly after starting eye plot, until no 7318 * more data is returned. 7319 */ 7320#define MC_CMD_KR_TUNE_IN_POLL_EYE_PLOT 0x6 7321/* Align the arguments to 32 bits */ 7322#define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1 7323#define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_LEN 3 7324/* Arguments specific to the operation */ 7325#define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_OFST 4 7326#define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4 7327#define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0 7328#define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM 62 7329 7330/* MC_CMD_KR_TUNE_OUT msgresponse */ 7331#define MC_CMD_KR_TUNE_OUT_LEN 0 7332 7333/* MC_CMD_KR_TUNE_RXEQ_GET_IN msgrequest */ 7334#define MC_CMD_KR_TUNE_RXEQ_GET_IN_LEN 4 7335/* Requested operation */ 7336#define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_OFST 0 7337#define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_LEN 1 7338/* Align the arguments to 32 bits */ 7339#define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 7340#define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 7341 7342/* MC_CMD_KR_TUNE_RXEQ_GET_OUT msgresponse */ 7343#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4 7344#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX 252 7345#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) 7346/* RXEQ Parameter */ 7347#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 7348#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 7349#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 7350#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 7351#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 7352#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 7353/* enum: Attenuation (0-15) */ 7354#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0 7355/* enum: CTLE Boost (0-15) */ 7356#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1 7357/* enum: Edge DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */ 7358#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2 7359/* enum: Edge DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */ 7360#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3 7361/* enum: Edge DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */ 7362#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4 7363/* enum: Edge DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */ 7364#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5 7365/* enum: Edge DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */ 7366#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6 7367#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 7368#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3 7369#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ 7370#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ 7371#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ 7372#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ 7373#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ 7374#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 11 7375#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 7376#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12 7377#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4 7378#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_LBN 16 7379#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 7380#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 7381#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 7382 7383/* MC_CMD_KR_TUNE_RXEQ_SET_IN msgrequest */ 7384#define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMIN 8 7385#define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX 252 7386#define MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) 7387/* Requested operation */ 7388#define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0 7389#define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_LEN 1 7390/* Align the arguments to 32 bits */ 7391#define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 7392#define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 7393/* RXEQ Parameter */ 7394#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_OFST 4 7395#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4 7396#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 7397#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 7398#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 7399#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 7400/* Enum values, see field(s): */ 7401/* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_ID */ 7402#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 7403#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 3 7404/* Enum values, see field(s): */ 7405/* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 7406#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 11 7407#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 7408#define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_LBN 12 7409#define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4 7410#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 7411#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 7412#define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 7413#define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 7414 7415/* MC_CMD_KR_TUNE_RXEQ_SET_OUT msgresponse */ 7416#define MC_CMD_KR_TUNE_RXEQ_SET_OUT_LEN 0 7417 7418/* MC_CMD_KR_TUNE_TXEQ_GET_IN msgrequest */ 7419#define MC_CMD_KR_TUNE_TXEQ_GET_IN_LEN 4 7420/* Requested operation */ 7421#define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_OFST 0 7422#define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_LEN 1 7423/* Align the arguments to 32 bits */ 7424#define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 7425#define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 7426 7427/* MC_CMD_KR_TUNE_TXEQ_GET_OUT msgresponse */ 7428#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMIN 4 7429#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMAX 252 7430#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) 7431/* TXEQ Parameter */ 7432#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 7433#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 7434#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 7435#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 7436#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 7437#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 7438/* enum: TX Amplitude */ 7439#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV 0x0 7440/* enum: De-Emphasis Tap1 Magnitude (0-7) */ 7441#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE 0x1 7442/* enum: De-Emphasis Tap1 Fine */ 7443#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV 0x2 7444/* enum: De-Emphasis Tap2 Magnitude (0-6) */ 7445#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2 0x3 7446/* enum: De-Emphasis Tap2 Fine */ 7447#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV 0x4 7448/* enum: Pre-Emphasis Magnitude */ 7449#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E 0x5 7450/* enum: Pre-Emphasis Fine */ 7451#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV 0x6 7452/* enum: TX Slew Rate Coarse control */ 7453#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY 0x7 7454/* enum: TX Slew Rate Fine control */ 7455#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET 0x8 7456#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 7457#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 3 7458#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */ 7459#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_1 0x1 /* enum */ 7460#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */ 7461#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */ 7462#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ 7463#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_LBN 11 7464#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 5 7465#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_LBN 16 7466#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 7467#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_LBN 24 7468#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_WIDTH 8 7469 7470/* MC_CMD_KR_TUNE_TXEQ_SET_IN msgrequest */ 7471#define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMIN 8 7472#define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMAX 252 7473#define MC_CMD_KR_TUNE_TXEQ_SET_IN_LEN(num) (4+4*(num)) 7474/* Requested operation */ 7475#define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_OFST 0 7476#define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_LEN 1 7477/* Align the arguments to 32 bits */ 7478#define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 7479#define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 7480/* TXEQ Parameter */ 7481#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_OFST 4 7482#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LEN 4 7483#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MINNUM 1 7484#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MAXNUM 62 7485#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_LBN 0 7486#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_WIDTH 8 7487/* Enum values, see field(s): */ 7488/* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_ID */ 7489#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_LBN 8 7490#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_WIDTH 3 7491/* Enum values, see field(s): */ 7492/* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_LANE */ 7493#define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_LBN 11 7494#define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_WIDTH 5 7495#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_LBN 16 7496#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 7497#define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_LBN 24 7498#define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_WIDTH 8 7499 7500/* MC_CMD_KR_TUNE_TXEQ_SET_OUT msgresponse */ 7501#define MC_CMD_KR_TUNE_TXEQ_SET_OUT_LEN 0 7502 7503/* MC_CMD_KR_TUNE_RECAL_IN msgrequest */ 7504#define MC_CMD_KR_TUNE_RECAL_IN_LEN 4 7505/* Requested operation */ 7506#define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_OFST 0 7507#define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_LEN 1 7508/* Align the arguments to 32 bits */ 7509#define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_OFST 1 7510#define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_LEN 3 7511 7512/* MC_CMD_KR_TUNE_RECAL_OUT msgresponse */ 7513#define MC_CMD_KR_TUNE_RECAL_OUT_LEN 0 7514 7515/* MC_CMD_KR_TUNE_START_EYE_PLOT_IN msgrequest */ 7516#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LEN 8 7517/* Requested operation */ 7518#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 7519#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 7520/* Align the arguments to 32 bits */ 7521#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 7522#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 7523#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 7524 7525/* MC_CMD_KR_TUNE_START_EYE_PLOT_OUT msgresponse */ 7526#define MC_CMD_KR_TUNE_START_EYE_PLOT_OUT_LEN 0 7527 7528/* MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN msgrequest */ 7529#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_LEN 4 7530/* Requested operation */ 7531#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 7532#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 7533/* Align the arguments to 32 bits */ 7534#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 7535#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 7536 7537/* MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT msgresponse */ 7538#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 7539#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 7540#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) 7541#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 7542#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 7543#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 7544#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 7545 7546 7547/***********************************/ 7548/* MC_CMD_PCIE_TUNE 7549 * Get or set PCIE Serdes RXEQ and TX Driver settings 7550 */ 7551#define MC_CMD_PCIE_TUNE 0xf2 7552 7553/* MC_CMD_PCIE_TUNE_IN msgrequest */ 7554#define MC_CMD_PCIE_TUNE_IN_LENMIN 4 7555#define MC_CMD_PCIE_TUNE_IN_LENMAX 252 7556#define MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num)) 7557/* Requested operation */ 7558#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0 7559#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1 7560/* enum: Get current RXEQ settings */ 7561#define MC_CMD_PCIE_TUNE_IN_RXEQ_GET 0x0 7562/* enum: Override RXEQ settings */ 7563#define MC_CMD_PCIE_TUNE_IN_RXEQ_SET 0x1 7564/* enum: Get current TX Driver settings */ 7565#define MC_CMD_PCIE_TUNE_IN_TXEQ_GET 0x2 7566/* enum: Override TX Driver settings */ 7567#define MC_CMD_PCIE_TUNE_IN_TXEQ_SET 0x3 7568/* enum: Start PCIe Serdes Eye diagram plot on a given lane. */ 7569#define MC_CMD_PCIE_TUNE_IN_START_EYE_PLOT 0x5 7570/* enum: Poll PCIe Serdes Eye diagram plot. Returns one row of BER data. The 7571 * caller should call this command repeatedly after starting eye plot, until no 7572 * more data is returned. 7573 */ 7574#define MC_CMD_PCIE_TUNE_IN_POLL_EYE_PLOT 0x6 7575/* Align the arguments to 32 bits */ 7576#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_OFST 1 7577#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_LEN 3 7578/* Arguments specific to the operation */ 7579#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_OFST 4 7580#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_LEN 4 7581#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MINNUM 0 7582#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM 62 7583 7584/* MC_CMD_PCIE_TUNE_OUT msgresponse */ 7585#define MC_CMD_PCIE_TUNE_OUT_LEN 0 7586 7587/* MC_CMD_PCIE_TUNE_RXEQ_GET_IN msgrequest */ 7588#define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_LEN 4 7589/* Requested operation */ 7590#define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 7591#define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 7592/* Align the arguments to 32 bits */ 7593#define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 7594#define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 7595 7596/* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT msgresponse */ 7597#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMIN 4 7598#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX 252 7599#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) 7600/* RXEQ Parameter */ 7601#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 7602#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 7603#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 7604#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 7605#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 7606#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 7607/* enum: Attenuation (0-15) */ 7608#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT 0x0 7609/* enum: CTLE Boost (0-15) */ 7610#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST 0x1 7611/* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */ 7612#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1 0x2 7613/* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */ 7614#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x3 7615/* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */ 7616#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x4 7617/* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */ 7618#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5 7619/* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */ 7620#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6 7621#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 7622#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 4 7623#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ 7624#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ 7625#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ 7626#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ 7627#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */ 7628#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */ 7629#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */ 7630#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */ 7631#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x8 /* enum */ 7632#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12 7633#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 12 7634#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 7635#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 7636 7637/* MC_CMD_PCIE_TUNE_TXEQ_GET_IN msgrequest */ 7638#define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4 7639/* Requested operation */ 7640#define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 7641#define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 7642/* Align the arguments to 32 bits */ 7643#define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 7644#define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 7645 7646/* MC_CMD_PCIE_TUNE_TXEQ_GET_OUT msgresponse */ 7647#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMIN 4 7648#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX 252 7649#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) 7650/* RXEQ Parameter */ 7651#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 7652#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 7653#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 7654#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 7655#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 7656#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 7657/* enum: TxMargin (PIPE) */ 7658#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN 0x0 7659/* enum: TxSwing (PIPE) */ 7660#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING 0x1 7661/* enum: De-emphasis coefficient C(-1) (PIPE) */ 7662#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1 0x2 7663/* enum: De-emphasis coefficient C(0) (PIPE) */ 7664#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3 7665/* enum: De-emphasis coefficient C(+1) (PIPE) */ 7666#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4 7667#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 7668#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4 7669/* Enum values, see field(s): */ 7670/* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 7671#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_LBN 12 7672#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 12 7673#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_LBN 24 7674#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 7675 7676/* MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN msgrequest */ 7677#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LEN 8 7678/* Requested operation */ 7679#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 7680#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 7681/* Align the arguments to 32 bits */ 7682#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 7683#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 7684#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 7685 7686/* MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT msgresponse */ 7687#define MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT_LEN 0 7688 7689/* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN msgrequest */ 7690#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_LEN 4 7691/* Requested operation */ 7692#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 7693#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 7694/* Align the arguments to 32 bits */ 7695#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 7696#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 7697 7698/* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT msgresponse */ 7699#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 7700#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 7701#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) 7702#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 7703#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 7704#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 7705#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 7706 7707 7708/***********************************/ 7709/* MC_CMD_LICENSING 7710 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition 7711 */ 7712#define MC_CMD_LICENSING 0xf3 7713 7714/* MC_CMD_LICENSING_IN msgrequest */ 7715#define MC_CMD_LICENSING_IN_LEN 4 7716/* identifies the type of operation requested */ 7717#define MC_CMD_LICENSING_IN_OP_OFST 0 7718/* enum: re-read and apply licenses after a license key partition update; note 7719 * that this operation returns a zero-length response 7720 */ 7721#define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0 7722/* enum: report counts of installed licenses */ 7723#define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1 7724 7725/* MC_CMD_LICENSING_OUT msgresponse */ 7726#define MC_CMD_LICENSING_OUT_LEN 28 7727/* count of application keys which are valid */ 7728#define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0 7729/* sum of UNVERIFIABLE_APP_KEYS + WRONG_NODE_APP_KEYS (for compatibility with 7730 * MC_CMD_FC_OP_LICENSE) 7731 */ 7732#define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4 7733/* count of application keys which are invalid due to being blacklisted */ 7734#define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_OFST 8 7735/* count of application keys which are invalid due to being unverifiable */ 7736#define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_OFST 12 7737/* count of application keys which are invalid due to being for the wrong node 7738 */ 7739#define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_OFST 16 7740/* licensing state (for diagnostics; the exact meaning of the bits in this 7741 * field are private to the firmware) 7742 */ 7743#define MC_CMD_LICENSING_OUT_LICENSING_STATE_OFST 20 7744/* licensing subsystem self-test report (for manftest) */ 7745#define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_OFST 24 7746/* enum: licensing subsystem self-test failed */ 7747#define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0 7748/* enum: licensing subsystem self-test passed */ 7749#define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1 7750 7751 7752/***********************************/ 7753/* MC_CMD_MC2MC_PROXY 7754 * Execute an arbitrary MCDI command on the slave MC of a dual-core device. 7755 * This will fail on a single-core system. 7756 */ 7757#define MC_CMD_MC2MC_PROXY 0xf4 7758 7759/* MC_CMD_MC2MC_PROXY_IN msgrequest */ 7760#define MC_CMD_MC2MC_PROXY_IN_LEN 0 7761 7762/* MC_CMD_MC2MC_PROXY_OUT msgresponse */ 7763#define MC_CMD_MC2MC_PROXY_OUT_LEN 0 7764 7765 7766/***********************************/ 7767/* MC_CMD_GET_LICENSED_APP_STATE 7768 * Query the state of an individual licensed application. (Note that the actual 7769 * state may be invalidated by the MC_CMD_LICENSING OP_UPDATE_LICENSE operation 7770 * or a reboot of the MC.) 7771 */ 7772#define MC_CMD_GET_LICENSED_APP_STATE 0xf5 7773 7774/* MC_CMD_GET_LICENSED_APP_STATE_IN msgrequest */ 7775#define MC_CMD_GET_LICENSED_APP_STATE_IN_LEN 4 7776/* application ID to query (LICENSED_APP_ID_xxx) */ 7777#define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 0 7778 7779/* MC_CMD_GET_LICENSED_APP_STATE_OUT msgresponse */ 7780#define MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 4 7781/* state of this application */ 7782#define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0 7783/* enum: no (or invalid) license is present for the application */ 7784#define MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0 7785/* enum: a valid license is present for the application */ 7786#define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1 7787 7788 7789/***********************************/ 7790/* MC_CMD_LICENSED_APP_OP 7791 * Perform an action for an individual licensed application. 7792 */ 7793#define MC_CMD_LICENSED_APP_OP 0xf6 7794 7795/* MC_CMD_LICENSED_APP_OP_IN msgrequest */ 7796#define MC_CMD_LICENSED_APP_OP_IN_LENMIN 8 7797#define MC_CMD_LICENSED_APP_OP_IN_LENMAX 252 7798#define MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num)) 7799/* application ID */ 7800#define MC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0 7801/* the type of operation requested */ 7802#define MC_CMD_LICENSED_APP_OP_IN_OP_OFST 4 7803/* enum: validate application */ 7804#define MC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE 0x0 7805/* arguments specific to this particular operation */ 7806#define MC_CMD_LICENSED_APP_OP_IN_ARGS_OFST 8 7807#define MC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 4 7808#define MC_CMD_LICENSED_APP_OP_IN_ARGS_MINNUM 0 7809#define MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM 61 7810 7811/* MC_CMD_LICENSED_APP_OP_OUT msgresponse */ 7812#define MC_CMD_LICENSED_APP_OP_OUT_LENMIN 0 7813#define MC_CMD_LICENSED_APP_OP_OUT_LENMAX 252 7814#define MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num)) 7815/* result specific to this particular operation */ 7816#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 0 7817#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 4 7818#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MINNUM 0 7819#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM 63 7820 7821/* MC_CMD_LICENSED_APP_OP_VALIDATE_IN msgrequest */ 7822#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_LEN 72 7823/* application ID */ 7824#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_OFST 0 7825/* the type of operation requested */ 7826#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_OFST 4 7827/* validation challenge */ 7828#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_OFST 8 7829#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_LEN 64 7830 7831/* MC_CMD_LICENSED_APP_OP_VALIDATE_OUT msgresponse */ 7832#define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_LEN 68 7833/* feature expiry (time_t) */ 7834#define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_OFST 0 7835/* validation response */ 7836#define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_OFST 4 7837#define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_LEN 64 7838 7839 7840/***********************************/ 7841/* MC_CMD_SET_PORT_SNIFF_CONFIG 7842 * Configure port sniffing for the physical port associated with the calling 7843 * function. Only a privileged function may change the port sniffing 7844 * configuration. A copy of all traffic delivered to the host (non-promiscuous 7845 * mode) or all traffic arriving at the port (promiscuous mode) may be 7846 * delivered to a specific queue, or a set of queues with RSS. 7847 */ 7848#define MC_CMD_SET_PORT_SNIFF_CONFIG 0xf7 7849 7850/* MC_CMD_SET_PORT_SNIFF_CONFIG_IN msgrequest */ 7851#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_LEN 16 7852/* configuration flags */ 7853#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 7854#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 7855#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 7856#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_LBN 1 7857#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_WIDTH 1 7858/* receive queue handle (for RSS mode, this is the base queue) */ 7859#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 7860/* receive mode */ 7861#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 7862/* enum: receive to just the specified queue */ 7863#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 7864/* enum: receive to multiple queues using RSS context */ 7865#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 7866/* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note 7867 * that these handles should be considered opaque to the host, although a value 7868 * of 0xFFFFFFFF is guaranteed never to be a valid handle. 7869 */ 7870#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 7871 7872/* MC_CMD_SET_PORT_SNIFF_CONFIG_OUT msgresponse */ 7873#define MC_CMD_SET_PORT_SNIFF_CONFIG_OUT_LEN 0 7874 7875 7876/***********************************/ 7877/* MC_CMD_GET_PORT_SNIFF_CONFIG 7878 * Obtain the current port sniffing configuration for the physical port 7879 * associated with the calling function. Only a privileged function may read 7880 * the configuration. 7881 */ 7882#define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8 7883 7884/* MC_CMD_GET_PORT_SNIFF_CONFIG_IN msgrequest */ 7885#define MC_CMD_GET_PORT_SNIFF_CONFIG_IN_LEN 0 7886 7887/* MC_CMD_GET_PORT_SNIFF_CONFIG_OUT msgresponse */ 7888#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_LEN 16 7889/* configuration flags */ 7890#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 7891#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 7892#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 7893#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_LBN 1 7894#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_WIDTH 1 7895/* receiving queue handle (for RSS mode, this is the base queue) */ 7896#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 7897/* receive mode */ 7898#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 7899/* enum: receiving to just the specified queue */ 7900#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 7901/* enum: receiving to multiple queues using RSS context */ 7902#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 7903/* RSS context (for RX_MODE_RSS) */ 7904#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 7905 7906 7907#endif /* MCDI_PCOL_H */ 7908