1/**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2005-2006 Fen Systems Ltd. 4 * Copyright 2005-2013 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11/* Common definitions for all Efx net driver code */ 12 13#ifndef EFX_NET_DRIVER_H 14#define EFX_NET_DRIVER_H 15 16#include <linux/netdevice.h> 17#include <linux/etherdevice.h> 18#include <linux/ethtool.h> 19#include <linux/if_vlan.h> 20#include <linux/timer.h> 21#include <linux/mdio.h> 22#include <linux/list.h> 23#include <linux/pci.h> 24#include <linux/device.h> 25#include <linux/highmem.h> 26#include <linux/workqueue.h> 27#include <linux/mutex.h> 28#include <linux/vmalloc.h> 29#include <linux/i2c.h> 30#include <linux/mtd/mtd.h> 31#include <net/busy_poll.h> 32 33#include "enum.h" 34#include "bitfield.h" 35#include "filter.h" 36 37/************************************************************************** 38 * 39 * Build definitions 40 * 41 **************************************************************************/ 42 43#define EFX_DRIVER_VERSION "4.0" 44 45#ifdef DEBUG 46#define EFX_BUG_ON_PARANOID(x) BUG_ON(x) 47#define EFX_WARN_ON_PARANOID(x) WARN_ON(x) 48#else 49#define EFX_BUG_ON_PARANOID(x) do {} while (0) 50#define EFX_WARN_ON_PARANOID(x) do {} while (0) 51#endif 52 53/************************************************************************** 54 * 55 * Efx data structures 56 * 57 **************************************************************************/ 58 59#define EFX_MAX_CHANNELS 32U 60#define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS 61#define EFX_EXTRA_CHANNEL_IOV 0 62#define EFX_EXTRA_CHANNEL_PTP 1 63#define EFX_MAX_EXTRA_CHANNELS 2U 64 65/* Checksum generation is a per-queue option in hardware, so each 66 * queue visible to the networking core is backed by two hardware TX 67 * queues. */ 68#define EFX_MAX_TX_TC 2 69#define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS) 70#define EFX_TXQ_TYPE_OFFLOAD 1 /* flag */ 71#define EFX_TXQ_TYPE_HIGHPRI 2 /* flag */ 72#define EFX_TXQ_TYPES 4 73#define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CHANNELS) 74 75/* Maximum possible MTU the driver supports */ 76#define EFX_MAX_MTU (9 * 1024) 77 78/* Size of an RX scatter buffer. Small enough to pack 2 into a 4K page, 79 * and should be a multiple of the cache line size. 80 */ 81#define EFX_RX_USR_BUF_SIZE (2048 - 256) 82 83/* If possible, we should ensure cache line alignment at start and end 84 * of every buffer. Otherwise, we just need to ensure 4-byte 85 * alignment of the network header. 86 */ 87#if NET_IP_ALIGN == 0 88#define EFX_RX_BUF_ALIGNMENT L1_CACHE_BYTES 89#else 90#define EFX_RX_BUF_ALIGNMENT 4 91#endif 92 93/* Forward declare Precision Time Protocol (PTP) support structure. */ 94struct efx_ptp_data; 95struct hwtstamp_config; 96 97struct efx_self_tests; 98 99/** 100 * struct efx_buffer - A general-purpose DMA buffer 101 * @addr: host base address of the buffer 102 * @dma_addr: DMA base address of the buffer 103 * @len: Buffer length, in bytes 104 * 105 * The NIC uses these buffers for its interrupt status registers and 106 * MAC stats dumps. 107 */ 108struct efx_buffer { 109 void *addr; 110 dma_addr_t dma_addr; 111 unsigned int len; 112}; 113 114/** 115 * struct efx_special_buffer - DMA buffer entered into buffer table 116 * @buf: Standard &struct efx_buffer 117 * @index: Buffer index within controller;s buffer table 118 * @entries: Number of buffer table entries 119 * 120 * The NIC has a buffer table that maps buffers of size %EFX_BUF_SIZE. 121 * Event and descriptor rings are addressed via one or more buffer 122 * table entries (and so can be physically non-contiguous, although we 123 * currently do not take advantage of that). On Falcon and Siena we 124 * have to take care of allocating and initialising the entries 125 * ourselves. On later hardware this is managed by the firmware and 126 * @index and @entries are left as 0. 127 */ 128struct efx_special_buffer { 129 struct efx_buffer buf; 130 unsigned int index; 131 unsigned int entries; 132}; 133 134/** 135 * struct efx_tx_buffer - buffer state for a TX descriptor 136 * @skb: When @flags & %EFX_TX_BUF_SKB, the associated socket buffer to be 137 * freed when descriptor completes 138 * @heap_buf: When @flags & %EFX_TX_BUF_HEAP, the associated heap buffer to be 139 * freed when descriptor completes. 140 * @option: When @flags & %EFX_TX_BUF_OPTION, a NIC-specific option descriptor. 141 * @dma_addr: DMA address of the fragment. 142 * @flags: Flags for allocation and DMA mapping type 143 * @len: Length of this fragment. 144 * This field is zero when the queue slot is empty. 145 * @unmap_len: Length of this fragment to unmap 146 * @dma_offset: Offset of @dma_addr from the address of the backing DMA mapping. 147 * Only valid if @unmap_len != 0. 148 */ 149struct efx_tx_buffer { 150 union { 151 const struct sk_buff *skb; 152 void *heap_buf; 153 }; 154 union { 155 efx_qword_t option; 156 dma_addr_t dma_addr; 157 }; 158 unsigned short flags; 159 unsigned short len; 160 unsigned short unmap_len; 161 unsigned short dma_offset; 162}; 163#define EFX_TX_BUF_CONT 1 /* not last descriptor of packet */ 164#define EFX_TX_BUF_SKB 2 /* buffer is last part of skb */ 165#define EFX_TX_BUF_HEAP 4 /* buffer was allocated with kmalloc() */ 166#define EFX_TX_BUF_MAP_SINGLE 8 /* buffer was mapped with dma_map_single() */ 167#define EFX_TX_BUF_OPTION 0x10 /* empty buffer for option descriptor */ 168 169/** 170 * struct efx_tx_queue - An Efx TX queue 171 * 172 * This is a ring buffer of TX fragments. 173 * Since the TX completion path always executes on the same 174 * CPU and the xmit path can operate on different CPUs, 175 * performance is increased by ensuring that the completion 176 * path and the xmit path operate on different cache lines. 177 * This is particularly important if the xmit path is always 178 * executing on one CPU which is different from the completion 179 * path. There is also a cache line for members which are 180 * read but not written on the fast path. 181 * 182 * @efx: The associated Efx NIC 183 * @queue: DMA queue number 184 * @channel: The associated channel 185 * @core_txq: The networking core TX queue structure 186 * @buffer: The software buffer ring 187 * @tsoh_page: Array of pages of TSO header buffers 188 * @txd: The hardware descriptor ring 189 * @ptr_mask: The size of the ring minus 1. 190 * @piobuf: PIO buffer region for this TX queue (shared with its partner). 191 * Size of the region is efx_piobuf_size. 192 * @piobuf_offset: Buffer offset to be specified in PIO descriptors 193 * @initialised: Has hardware queue been initialised? 194 * @read_count: Current read pointer. 195 * This is the number of buffers that have been removed from both rings. 196 * @old_write_count: The value of @write_count when last checked. 197 * This is here for performance reasons. The xmit path will 198 * only get the up-to-date value of @write_count if this 199 * variable indicates that the queue is empty. This is to 200 * avoid cache-line ping-pong between the xmit path and the 201 * completion path. 202 * @merge_events: Number of TX merged completion events 203 * @insert_count: Current insert pointer 204 * This is the number of buffers that have been added to the 205 * software ring. 206 * @write_count: Current write pointer 207 * This is the number of buffers that have been added to the 208 * hardware ring. 209 * @old_read_count: The value of read_count when last checked. 210 * This is here for performance reasons. The xmit path will 211 * only get the up-to-date value of read_count if this 212 * variable indicates that the queue is full. This is to 213 * avoid cache-line ping-pong between the xmit path and the 214 * completion path. 215 * @tso_bursts: Number of times TSO xmit invoked by kernel 216 * @tso_long_headers: Number of packets with headers too long for standard 217 * blocks 218 * @tso_packets: Number of packets via the TSO xmit path 219 * @pushes: Number of times the TX push feature has been used 220 * @pio_packets: Number of times the TX PIO feature has been used 221 * @xmit_more_available: Are any packets waiting to be pushed to the NIC 222 * @empty_read_count: If the completion path has seen the queue as empty 223 * and the transmission path has not yet checked this, the value of 224 * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0. 225 */ 226struct efx_tx_queue { 227 /* Members which don't change on the fast path */ 228 struct efx_nic *efx ____cacheline_aligned_in_smp; 229 unsigned queue; 230 struct efx_channel *channel; 231 struct netdev_queue *core_txq; 232 struct efx_tx_buffer *buffer; 233 struct efx_buffer *tsoh_page; 234 struct efx_special_buffer txd; 235 unsigned int ptr_mask; 236 void __iomem *piobuf; 237 unsigned int piobuf_offset; 238 bool initialised; 239 240 /* Members used mainly on the completion path */ 241 unsigned int read_count ____cacheline_aligned_in_smp; 242 unsigned int old_write_count; 243 unsigned int merge_events; 244 245 /* Members used only on the xmit path */ 246 unsigned int insert_count ____cacheline_aligned_in_smp; 247 unsigned int write_count; 248 unsigned int old_read_count; 249 unsigned int tso_bursts; 250 unsigned int tso_long_headers; 251 unsigned int tso_packets; 252 unsigned int pushes; 253 unsigned int pio_packets; 254 bool xmit_more_available; 255 /* Statistics to supplement MAC stats */ 256 unsigned long tx_packets; 257 258 /* Members shared between paths and sometimes updated */ 259 unsigned int empty_read_count ____cacheline_aligned_in_smp; 260#define EFX_EMPTY_COUNT_VALID 0x80000000 261 atomic_t flush_outstanding; 262}; 263 264/** 265 * struct efx_rx_buffer - An Efx RX data buffer 266 * @dma_addr: DMA base address of the buffer 267 * @page: The associated page buffer. 268 * Will be %NULL if the buffer slot is currently free. 269 * @page_offset: If pending: offset in @page of DMA base address. 270 * If completed: offset in @page of Ethernet header. 271 * @len: If pending: length for DMA descriptor. 272 * If completed: received length, excluding hash prefix. 273 * @flags: Flags for buffer and packet state. These are only set on the 274 * first buffer of a scattered packet. 275 */ 276struct efx_rx_buffer { 277 dma_addr_t dma_addr; 278 struct page *page; 279 u16 page_offset; 280 u16 len; 281 u16 flags; 282}; 283#define EFX_RX_BUF_LAST_IN_PAGE 0x0001 284#define EFX_RX_PKT_CSUMMED 0x0002 285#define EFX_RX_PKT_DISCARD 0x0004 286#define EFX_RX_PKT_TCP 0x0040 287#define EFX_RX_PKT_PREFIX_LEN 0x0080 /* length is in prefix only */ 288 289/** 290 * struct efx_rx_page_state - Page-based rx buffer state 291 * 292 * Inserted at the start of every page allocated for receive buffers. 293 * Used to facilitate sharing dma mappings between recycled rx buffers 294 * and those passed up to the kernel. 295 * 296 * @dma_addr: The dma address of this page. 297 */ 298struct efx_rx_page_state { 299 dma_addr_t dma_addr; 300 301 unsigned int __pad[0] ____cacheline_aligned; 302}; 303 304/** 305 * struct efx_rx_queue - An Efx RX queue 306 * @efx: The associated Efx NIC 307 * @core_index: Index of network core RX queue. Will be >= 0 iff this 308 * is associated with a real RX queue. 309 * @buffer: The software buffer ring 310 * @rxd: The hardware descriptor ring 311 * @ptr_mask: The size of the ring minus 1. 312 * @refill_enabled: Enable refill whenever fill level is low 313 * @flush_pending: Set when a RX flush is pending. Has the same lifetime as 314 * @rxq_flush_pending. 315 * @added_count: Number of buffers added to the receive queue. 316 * @notified_count: Number of buffers given to NIC (<= @added_count). 317 * @removed_count: Number of buffers removed from the receive queue. 318 * @scatter_n: Used by NIC specific receive code. 319 * @scatter_len: Used by NIC specific receive code. 320 * @page_ring: The ring to store DMA mapped pages for reuse. 321 * @page_add: Counter to calculate the write pointer for the recycle ring. 322 * @page_remove: Counter to calculate the read pointer for the recycle ring. 323 * @page_recycle_count: The number of pages that have been recycled. 324 * @page_recycle_failed: The number of pages that couldn't be recycled because 325 * the kernel still held a reference to them. 326 * @page_recycle_full: The number of pages that were released because the 327 * recycle ring was full. 328 * @page_ptr_mask: The number of pages in the RX recycle ring minus 1. 329 * @max_fill: RX descriptor maximum fill level (<= ring size) 330 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill 331 * (<= @max_fill) 332 * @min_fill: RX descriptor minimum non-zero fill level. 333 * This records the minimum fill level observed when a ring 334 * refill was triggered. 335 * @recycle_count: RX buffer recycle counter. 336 * @slow_fill: Timer used to defer efx_nic_generate_fill_event(). 337 */ 338struct efx_rx_queue { 339 struct efx_nic *efx; 340 int core_index; 341 struct efx_rx_buffer *buffer; 342 struct efx_special_buffer rxd; 343 unsigned int ptr_mask; 344 bool refill_enabled; 345 bool flush_pending; 346 347 unsigned int added_count; 348 unsigned int notified_count; 349 unsigned int removed_count; 350 unsigned int scatter_n; 351 unsigned int scatter_len; 352 struct page **page_ring; 353 unsigned int page_add; 354 unsigned int page_remove; 355 unsigned int page_recycle_count; 356 unsigned int page_recycle_failed; 357 unsigned int page_recycle_full; 358 unsigned int page_ptr_mask; 359 unsigned int max_fill; 360 unsigned int fast_fill_trigger; 361 unsigned int min_fill; 362 unsigned int min_overfill; 363 unsigned int recycle_count; 364 struct timer_list slow_fill; 365 unsigned int slow_fill_count; 366 /* Statistics to supplement MAC stats */ 367 unsigned long rx_packets; 368}; 369 370enum efx_sync_events_state { 371 SYNC_EVENTS_DISABLED = 0, 372 SYNC_EVENTS_QUIESCENT, 373 SYNC_EVENTS_REQUESTED, 374 SYNC_EVENTS_VALID, 375}; 376 377/** 378 * struct efx_channel - An Efx channel 379 * 380 * A channel comprises an event queue, at least one TX queue, at least 381 * one RX queue, and an associated tasklet for processing the event 382 * queue. 383 * 384 * @efx: Associated Efx NIC 385 * @channel: Channel instance number 386 * @type: Channel type definition 387 * @eventq_init: Event queue initialised flag 388 * @enabled: Channel enabled indicator 389 * @irq: IRQ number (MSI and MSI-X only) 390 * @irq_moderation: IRQ moderation value (in hardware ticks) 391 * @napi_dev: Net device used with NAPI 392 * @napi_str: NAPI control structure 393 * @state: state for NAPI vs busy polling 394 * @state_lock: lock protecting @state 395 * @eventq: Event queue buffer 396 * @eventq_mask: Event queue pointer mask 397 * @eventq_read_ptr: Event queue read pointer 398 * @event_test_cpu: Last CPU to handle interrupt or test event for this channel 399 * @irq_count: Number of IRQs since last adaptive moderation decision 400 * @irq_mod_score: IRQ moderation score 401 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors 402 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors 403 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors 404 * @n_rx_mcast_mismatch: Count of unmatched multicast frames 405 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors 406 * @n_rx_overlength: Count of RX_OVERLENGTH errors 407 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun 408 * @n_rx_nodesc_trunc: Number of RX packets truncated and then dropped due to 409 * lack of descriptors 410 * @n_rx_merge_events: Number of RX merged completion events 411 * @n_rx_merge_packets: Number of RX packets completed by merged events 412 * @rx_pkt_n_frags: Number of fragments in next packet to be delivered by 413 * __efx_rx_packet(), or zero if there is none 414 * @rx_pkt_index: Ring index of first buffer for next packet to be delivered 415 * by __efx_rx_packet(), if @rx_pkt_n_frags != 0 416 * @rx_queue: RX queue for this channel 417 * @tx_queue: TX queues for this channel 418 * @sync_events_state: Current state of sync events on this channel 419 * @sync_timestamp_major: Major part of the last ptp sync event 420 * @sync_timestamp_minor: Minor part of the last ptp sync event 421 */ 422struct efx_channel { 423 struct efx_nic *efx; 424 int channel; 425 const struct efx_channel_type *type; 426 bool eventq_init; 427 bool enabled; 428 int irq; 429 unsigned int irq_moderation; 430 struct net_device *napi_dev; 431 struct napi_struct napi_str; 432#ifdef CONFIG_NET_RX_BUSY_POLL 433 unsigned int state; 434 spinlock_t state_lock; 435#define EFX_CHANNEL_STATE_IDLE 0 436#define EFX_CHANNEL_STATE_NAPI (1 << 0) /* NAPI owns this channel */ 437#define EFX_CHANNEL_STATE_POLL (1 << 1) /* poll owns this channel */ 438#define EFX_CHANNEL_STATE_DISABLED (1 << 2) /* channel is disabled */ 439#define EFX_CHANNEL_STATE_NAPI_YIELD (1 << 3) /* NAPI yielded this channel */ 440#define EFX_CHANNEL_STATE_POLL_YIELD (1 << 4) /* poll yielded this channel */ 441#define EFX_CHANNEL_OWNED \ 442 (EFX_CHANNEL_STATE_NAPI | EFX_CHANNEL_STATE_POLL) 443#define EFX_CHANNEL_LOCKED \ 444 (EFX_CHANNEL_OWNED | EFX_CHANNEL_STATE_DISABLED) 445#define EFX_CHANNEL_USER_PEND \ 446 (EFX_CHANNEL_STATE_POLL | EFX_CHANNEL_STATE_POLL_YIELD) 447#endif /* CONFIG_NET_RX_BUSY_POLL */ 448 struct efx_special_buffer eventq; 449 unsigned int eventq_mask; 450 unsigned int eventq_read_ptr; 451 int event_test_cpu; 452 453 unsigned int irq_count; 454 unsigned int irq_mod_score; 455#ifdef CONFIG_RFS_ACCEL 456 unsigned int rfs_filters_added; 457#endif 458 459 unsigned n_rx_tobe_disc; 460 unsigned n_rx_ip_hdr_chksum_err; 461 unsigned n_rx_tcp_udp_chksum_err; 462 unsigned n_rx_mcast_mismatch; 463 unsigned n_rx_frm_trunc; 464 unsigned n_rx_overlength; 465 unsigned n_skbuff_leaks; 466 unsigned int n_rx_nodesc_trunc; 467 unsigned int n_rx_merge_events; 468 unsigned int n_rx_merge_packets; 469 470 unsigned int rx_pkt_n_frags; 471 unsigned int rx_pkt_index; 472 473 struct efx_rx_queue rx_queue; 474 struct efx_tx_queue tx_queue[EFX_TXQ_TYPES]; 475 476 enum efx_sync_events_state sync_events_state; 477 u32 sync_timestamp_major; 478 u32 sync_timestamp_minor; 479}; 480 481#ifdef CONFIG_NET_RX_BUSY_POLL 482static inline void efx_channel_init_lock(struct efx_channel *channel) 483{ 484 spin_lock_init(&channel->state_lock); 485} 486 487/* Called from the device poll routine to get ownership of a channel. */ 488static inline bool efx_channel_lock_napi(struct efx_channel *channel) 489{ 490 bool rc = true; 491 492 spin_lock_bh(&channel->state_lock); 493 if (channel->state & EFX_CHANNEL_LOCKED) { 494 WARN_ON(channel->state & EFX_CHANNEL_STATE_NAPI); 495 channel->state |= EFX_CHANNEL_STATE_NAPI_YIELD; 496 rc = false; 497 } else { 498 /* we don't care if someone yielded */ 499 channel->state = EFX_CHANNEL_STATE_NAPI; 500 } 501 spin_unlock_bh(&channel->state_lock); 502 return rc; 503} 504 505static inline void efx_channel_unlock_napi(struct efx_channel *channel) 506{ 507 spin_lock_bh(&channel->state_lock); 508 WARN_ON(channel->state & 509 (EFX_CHANNEL_STATE_POLL | EFX_CHANNEL_STATE_NAPI_YIELD)); 510 511 channel->state &= EFX_CHANNEL_STATE_DISABLED; 512 spin_unlock_bh(&channel->state_lock); 513} 514 515/* Called from efx_busy_poll(). */ 516static inline bool efx_channel_lock_poll(struct efx_channel *channel) 517{ 518 bool rc = true; 519 520 spin_lock_bh(&channel->state_lock); 521 if ((channel->state & EFX_CHANNEL_LOCKED)) { 522 channel->state |= EFX_CHANNEL_STATE_POLL_YIELD; 523 rc = false; 524 } else { 525 /* preserve yield marks */ 526 channel->state |= EFX_CHANNEL_STATE_POLL; 527 } 528 spin_unlock_bh(&channel->state_lock); 529 return rc; 530} 531 532/* Returns true if NAPI tried to get the channel while it was locked. */ 533static inline void efx_channel_unlock_poll(struct efx_channel *channel) 534{ 535 spin_lock_bh(&channel->state_lock); 536 WARN_ON(channel->state & EFX_CHANNEL_STATE_NAPI); 537 538 /* will reset state to idle, unless channel is disabled */ 539 channel->state &= EFX_CHANNEL_STATE_DISABLED; 540 spin_unlock_bh(&channel->state_lock); 541} 542 543/* True if a socket is polling, even if it did not get the lock. */ 544static inline bool efx_channel_busy_polling(struct efx_channel *channel) 545{ 546 WARN_ON(!(channel->state & EFX_CHANNEL_OWNED)); 547 return channel->state & EFX_CHANNEL_USER_PEND; 548} 549 550static inline void efx_channel_enable(struct efx_channel *channel) 551{ 552 spin_lock_bh(&channel->state_lock); 553 channel->state = EFX_CHANNEL_STATE_IDLE; 554 spin_unlock_bh(&channel->state_lock); 555} 556 557/* False if the channel is currently owned. */ 558static inline bool efx_channel_disable(struct efx_channel *channel) 559{ 560 bool rc = true; 561 562 spin_lock_bh(&channel->state_lock); 563 if (channel->state & EFX_CHANNEL_OWNED) 564 rc = false; 565 channel->state |= EFX_CHANNEL_STATE_DISABLED; 566 spin_unlock_bh(&channel->state_lock); 567 568 return rc; 569} 570 571#else /* CONFIG_NET_RX_BUSY_POLL */ 572 573static inline void efx_channel_init_lock(struct efx_channel *channel) 574{ 575} 576 577static inline bool efx_channel_lock_napi(struct efx_channel *channel) 578{ 579 return true; 580} 581 582static inline void efx_channel_unlock_napi(struct efx_channel *channel) 583{ 584} 585 586static inline bool efx_channel_lock_poll(struct efx_channel *channel) 587{ 588 return false; 589} 590 591static inline void efx_channel_unlock_poll(struct efx_channel *channel) 592{ 593} 594 595static inline bool efx_channel_busy_polling(struct efx_channel *channel) 596{ 597 return false; 598} 599 600static inline void efx_channel_enable(struct efx_channel *channel) 601{ 602} 603 604static inline bool efx_channel_disable(struct efx_channel *channel) 605{ 606 return true; 607} 608#endif /* CONFIG_NET_RX_BUSY_POLL */ 609 610/** 611 * struct efx_msi_context - Context for each MSI 612 * @efx: The associated NIC 613 * @index: Index of the channel/IRQ 614 * @name: Name of the channel/IRQ 615 * 616 * Unlike &struct efx_channel, this is never reallocated and is always 617 * safe for the IRQ handler to access. 618 */ 619struct efx_msi_context { 620 struct efx_nic *efx; 621 unsigned int index; 622 char name[IFNAMSIZ + 6]; 623}; 624 625/** 626 * struct efx_channel_type - distinguishes traffic and extra channels 627 * @handle_no_channel: Handle failure to allocate an extra channel 628 * @pre_probe: Set up extra state prior to initialisation 629 * @post_remove: Tear down extra state after finalisation, if allocated. 630 * May be called on channels that have not been probed. 631 * @get_name: Generate the channel's name (used for its IRQ handler) 632 * @copy: Copy the channel state prior to reallocation. May be %NULL if 633 * reallocation is not supported. 634 * @receive_skb: Handle an skb ready to be passed to netif_receive_skb() 635 * @keep_eventq: Flag for whether event queue should be kept initialised 636 * while the device is stopped 637 */ 638struct efx_channel_type { 639 void (*handle_no_channel)(struct efx_nic *); 640 int (*pre_probe)(struct efx_channel *); 641 void (*post_remove)(struct efx_channel *); 642 void (*get_name)(struct efx_channel *, char *buf, size_t len); 643 struct efx_channel *(*copy)(const struct efx_channel *); 644 bool (*receive_skb)(struct efx_channel *, struct sk_buff *); 645 bool keep_eventq; 646}; 647 648enum efx_led_mode { 649 EFX_LED_OFF = 0, 650 EFX_LED_ON = 1, 651 EFX_LED_DEFAULT = 2 652}; 653 654#define STRING_TABLE_LOOKUP(val, member) \ 655 ((val) < member ## _max) ? member ## _names[val] : "(invalid)" 656 657extern const char *const efx_loopback_mode_names[]; 658extern const unsigned int efx_loopback_mode_max; 659#define LOOPBACK_MODE(efx) \ 660 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode) 661 662extern const char *const efx_reset_type_names[]; 663extern const unsigned int efx_reset_type_max; 664#define RESET_TYPE(type) \ 665 STRING_TABLE_LOOKUP(type, efx_reset_type) 666 667enum efx_int_mode { 668 /* Be careful if altering to correct macro below */ 669 EFX_INT_MODE_MSIX = 0, 670 EFX_INT_MODE_MSI = 1, 671 EFX_INT_MODE_LEGACY = 2, 672 EFX_INT_MODE_MAX /* Insert any new items before this */ 673}; 674#define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI) 675 676enum nic_state { 677 STATE_UNINIT = 0, /* device being probed/removed or is frozen */ 678 STATE_READY = 1, /* hardware ready and netdev registered */ 679 STATE_DISABLED = 2, /* device disabled due to hardware errors */ 680 STATE_RECOVERY = 3, /* device recovering from PCI error */ 681}; 682 683/* Forward declaration */ 684struct efx_nic; 685 686/* Pseudo bit-mask flow control field */ 687#define EFX_FC_RX FLOW_CTRL_RX 688#define EFX_FC_TX FLOW_CTRL_TX 689#define EFX_FC_AUTO 4 690 691/** 692 * struct efx_link_state - Current state of the link 693 * @up: Link is up 694 * @fd: Link is full-duplex 695 * @fc: Actual flow control flags 696 * @speed: Link speed (Mbps) 697 */ 698struct efx_link_state { 699 bool up; 700 bool fd; 701 u8 fc; 702 unsigned int speed; 703}; 704 705static inline bool efx_link_state_equal(const struct efx_link_state *left, 706 const struct efx_link_state *right) 707{ 708 return left->up == right->up && left->fd == right->fd && 709 left->fc == right->fc && left->speed == right->speed; 710} 711 712/** 713 * struct efx_phy_operations - Efx PHY operations table 714 * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds, 715 * efx->loopback_modes. 716 * @init: Initialise PHY 717 * @fini: Shut down PHY 718 * @reconfigure: Reconfigure PHY (e.g. for new link parameters) 719 * @poll: Update @link_state and report whether it changed. 720 * Serialised by the mac_lock. 721 * @get_settings: Get ethtool settings. Serialised by the mac_lock. 722 * @set_settings: Set ethtool settings. Serialised by the mac_lock. 723 * @set_npage_adv: Set abilities advertised in (Extended) Next Page 724 * (only needed where AN bit is set in mmds) 725 * @test_alive: Test that PHY is 'alive' (online) 726 * @test_name: Get the name of a PHY-specific test/result 727 * @run_tests: Run tests and record results as appropriate (offline). 728 * Flags are the ethtool tests flags. 729 */ 730struct efx_phy_operations { 731 int (*probe) (struct efx_nic *efx); 732 int (*init) (struct efx_nic *efx); 733 void (*fini) (struct efx_nic *efx); 734 void (*remove) (struct efx_nic *efx); 735 int (*reconfigure) (struct efx_nic *efx); 736 bool (*poll) (struct efx_nic *efx); 737 void (*get_settings) (struct efx_nic *efx, 738 struct ethtool_cmd *ecmd); 739 int (*set_settings) (struct efx_nic *efx, 740 struct ethtool_cmd *ecmd); 741 void (*set_npage_adv) (struct efx_nic *efx, u32); 742 int (*test_alive) (struct efx_nic *efx); 743 const char *(*test_name) (struct efx_nic *efx, unsigned int index); 744 int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags); 745 int (*get_module_eeprom) (struct efx_nic *efx, 746 struct ethtool_eeprom *ee, 747 u8 *data); 748 int (*get_module_info) (struct efx_nic *efx, 749 struct ethtool_modinfo *modinfo); 750}; 751 752/** 753 * enum efx_phy_mode - PHY operating mode flags 754 * @PHY_MODE_NORMAL: on and should pass traffic 755 * @PHY_MODE_TX_DISABLED: on with TX disabled 756 * @PHY_MODE_LOW_POWER: set to low power through MDIO 757 * @PHY_MODE_OFF: switched off through external control 758 * @PHY_MODE_SPECIAL: on but will not pass traffic 759 */ 760enum efx_phy_mode { 761 PHY_MODE_NORMAL = 0, 762 PHY_MODE_TX_DISABLED = 1, 763 PHY_MODE_LOW_POWER = 2, 764 PHY_MODE_OFF = 4, 765 PHY_MODE_SPECIAL = 8, 766}; 767 768static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode) 769{ 770 return !!(mode & ~PHY_MODE_TX_DISABLED); 771} 772 773/** 774 * struct efx_hw_stat_desc - Description of a hardware statistic 775 * @name: Name of the statistic as visible through ethtool, or %NULL if 776 * it should not be exposed 777 * @dma_width: Width in bits (0 for non-DMA statistics) 778 * @offset: Offset within stats (ignored for non-DMA statistics) 779 */ 780struct efx_hw_stat_desc { 781 const char *name; 782 u16 dma_width; 783 u16 offset; 784}; 785 786/* Number of bits used in a multicast filter hash address */ 787#define EFX_MCAST_HASH_BITS 8 788 789/* Number of (single-bit) entries in a multicast filter hash */ 790#define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS) 791 792/* An Efx multicast filter hash */ 793union efx_multicast_hash { 794 u8 byte[EFX_MCAST_HASH_ENTRIES / 8]; 795 efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8]; 796}; 797 798struct efx_vf; 799struct vfdi_status; 800 801/** 802 * struct efx_nic - an Efx NIC 803 * @name: Device name (net device name or bus id before net device registered) 804 * @pci_dev: The PCI device 805 * @node: List node for maintaning primary/secondary function lists 806 * @primary: &struct efx_nic instance for the primary function of this 807 * controller. May be the same structure, and may be %NULL if no 808 * primary function is bound. Serialised by rtnl_lock. 809 * @secondary_list: List of &struct efx_nic instances for the secondary PCI 810 * functions of the controller, if this is for the primary function. 811 * Serialised by rtnl_lock. 812 * @type: Controller type attributes 813 * @legacy_irq: IRQ number 814 * @workqueue: Workqueue for port reconfigures and the HW monitor. 815 * Work items do not hold and must not acquire RTNL. 816 * @workqueue_name: Name of workqueue 817 * @reset_work: Scheduled reset workitem 818 * @membase_phys: Memory BAR value as physical address 819 * @membase: Memory BAR value 820 * @interrupt_mode: Interrupt mode 821 * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds 822 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues 823 * @irq_rx_moderation: IRQ moderation time for RX event queues 824 * @msg_enable: Log message enable flags 825 * @state: Device state number (%STATE_*). Serialised by the rtnl_lock. 826 * @reset_pending: Bitmask for pending resets 827 * @tx_queue: TX DMA queues 828 * @rx_queue: RX DMA queues 829 * @channel: Channels 830 * @msi_context: Context for each MSI 831 * @extra_channel_types: Types of extra (non-traffic) channels that 832 * should be allocated for this NIC 833 * @rxq_entries: Size of receive queues requested by user. 834 * @txq_entries: Size of transmit queues requested by user. 835 * @txq_stop_thresh: TX queue fill level at or above which we stop it. 836 * @txq_wake_thresh: TX queue fill level at or below which we wake it. 837 * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches 838 * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches 839 * @sram_lim_qw: Qword address limit of SRAM 840 * @next_buffer_table: First available buffer table id 841 * @n_channels: Number of channels in use 842 * @n_rx_channels: Number of channels used for RX (= number of RX queues) 843 * @n_tx_channels: Number of channels used for TX 844 * @rx_ip_align: RX DMA address offset to have IP header aligned in 845 * in accordance with NET_IP_ALIGN 846 * @rx_dma_len: Current maximum RX DMA length 847 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer 848 * @rx_buffer_truesize: Amortised allocation size of an RX buffer, 849 * for use in sk_buff::truesize 850 * @rx_prefix_size: Size of RX prefix before packet data 851 * @rx_packet_hash_offset: Offset of RX flow hash from start of packet data 852 * (valid only if @rx_prefix_size != 0; always negative) 853 * @rx_packet_len_offset: Offset of RX packet length from start of packet data 854 * (valid only for NICs that set %EFX_RX_PKT_PREFIX_LEN; always negative) 855 * @rx_packet_ts_offset: Offset of timestamp from start of packet data 856 * (valid only if channel->sync_timestamps_enabled; always negative) 857 * @rx_hash_key: Toeplitz hash key for RSS 858 * @rx_indir_table: Indirection table for RSS 859 * @rx_scatter: Scatter mode enabled for receives 860 * @int_error_count: Number of internal errors seen recently 861 * @int_error_expire: Time at which error count will be expired 862 * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will 863 * acknowledge but do nothing else. 864 * @irq_status: Interrupt status buffer 865 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0 866 * @irq_level: IRQ level/index for IRQs not triggered by an event queue 867 * @selftest_work: Work item for asynchronous self-test 868 * @mtd_list: List of MTDs attached to the NIC 869 * @nic_data: Hardware dependent state 870 * @mcdi: Management-Controller-to-Driver Interface state 871 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode, 872 * efx_monitor() and efx_reconfigure_port() 873 * @port_enabled: Port enabled indicator. 874 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and 875 * efx_mac_work() with kernel interfaces. Safe to read under any 876 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must 877 * be held to modify it. 878 * @port_initialized: Port initialized? 879 * @net_dev: Operating system network device. Consider holding the rtnl lock 880 * @stats_buffer: DMA buffer for statistics 881 * @phy_type: PHY type 882 * @phy_op: PHY interface 883 * @phy_data: PHY private data (including PHY-specific stats) 884 * @mdio: PHY MDIO interface 885 * @mdio_bus: PHY MDIO bus ID (only used by Siena) 886 * @phy_mode: PHY operating mode. Serialised by @mac_lock. 887 * @link_advertising: Autonegotiation advertising flags 888 * @link_state: Current state of the link 889 * @n_link_state_changes: Number of times the link has changed state 890 * @unicast_filter: Flag for Falcon-arch simple unicast filter. 891 * Protected by @mac_lock. 892 * @multicast_hash: Multicast hash table for Falcon-arch. 893 * Protected by @mac_lock. 894 * @wanted_fc: Wanted flow control flags 895 * @fc_disable: When non-zero flow control is disabled. Typically used to 896 * ensure that network back pressure doesn't delay dma queue flushes. 897 * Serialised by the rtnl lock. 898 * @mac_work: Work item for changing MAC promiscuity and multicast hash 899 * @loopback_mode: Loopback status 900 * @loopback_modes: Supported loopback mode bitmask 901 * @loopback_selftest: Offline self-test private state 902 * @filter_lock: Filter table lock 903 * @filter_state: Architecture-dependent filter table state 904 * @rps_flow_id: Flow IDs of filters allocated for accelerated RFS, 905 * indexed by filter ID 906 * @rps_expire_index: Next index to check for expiry in @rps_flow_id 907 * @active_queues: Count of RX and TX queues that haven't been flushed and drained. 908 * @rxq_flush_pending: Count of number of receive queues that need to be flushed. 909 * Decremented when the efx_flush_rx_queue() is called. 910 * @rxq_flush_outstanding: Count of number of RX flushes started but not yet 911 * completed (either success or failure). Not used when MCDI is used to 912 * flush receive queues. 913 * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions. 914 * @vf: Array of &struct efx_vf objects. 915 * @vf_count: Number of VFs intended to be enabled. 916 * @vf_init_count: Number of VFs that have been fully initialised. 917 * @vi_scale: log2 number of vnics per VF. 918 * @ptp_data: PTP state data 919 * @vpd_sn: Serial number read from VPD 920 * @monitor_work: Hardware monitor workitem 921 * @biu_lock: BIU (bus interface unit) lock 922 * @last_irq_cpu: Last CPU to handle a possible test interrupt. This 923 * field is used by efx_test_interrupts() to verify that an 924 * interrupt has occurred. 925 * @stats_lock: Statistics update lock. Must be held when calling 926 * efx_nic_type::{update,start,stop}_stats. 927 * @n_rx_noskb_drops: Count of RX packets dropped due to failure to allocate an skb 928 * 929 * This is stored in the private area of the &struct net_device. 930 */ 931struct efx_nic { 932 /* The following fields should be written very rarely */ 933 934 char name[IFNAMSIZ]; 935 struct list_head node; 936 struct efx_nic *primary; 937 struct list_head secondary_list; 938 struct pci_dev *pci_dev; 939 unsigned int port_num; 940 const struct efx_nic_type *type; 941 int legacy_irq; 942 bool eeh_disabled_legacy_irq; 943 struct workqueue_struct *workqueue; 944 char workqueue_name[16]; 945 struct work_struct reset_work; 946 resource_size_t membase_phys; 947 void __iomem *membase; 948 949 enum efx_int_mode interrupt_mode; 950 unsigned int timer_quantum_ns; 951 bool irq_rx_adaptive; 952 unsigned int irq_rx_moderation; 953 u32 msg_enable; 954 955 enum nic_state state; 956 unsigned long reset_pending; 957 958 struct efx_channel *channel[EFX_MAX_CHANNELS]; 959 struct efx_msi_context msi_context[EFX_MAX_CHANNELS]; 960 const struct efx_channel_type * 961 extra_channel_type[EFX_MAX_EXTRA_CHANNELS]; 962 963 unsigned rxq_entries; 964 unsigned txq_entries; 965 unsigned int txq_stop_thresh; 966 unsigned int txq_wake_thresh; 967 968 unsigned tx_dc_base; 969 unsigned rx_dc_base; 970 unsigned sram_lim_qw; 971 unsigned next_buffer_table; 972 973 unsigned int max_channels; 974 unsigned n_channels; 975 unsigned n_rx_channels; 976 unsigned rss_spread; 977 unsigned tx_channel_offset; 978 unsigned n_tx_channels; 979 unsigned int rx_ip_align; 980 unsigned int rx_dma_len; 981 unsigned int rx_buffer_order; 982 unsigned int rx_buffer_truesize; 983 unsigned int rx_page_buf_step; 984 unsigned int rx_bufs_per_page; 985 unsigned int rx_pages_per_batch; 986 unsigned int rx_prefix_size; 987 int rx_packet_hash_offset; 988 int rx_packet_len_offset; 989 int rx_packet_ts_offset; 990 u8 rx_hash_key[40]; 991 u32 rx_indir_table[128]; 992 bool rx_scatter; 993 994 unsigned int_error_count; 995 unsigned long int_error_expire; 996 997 bool irq_soft_enabled; 998 struct efx_buffer irq_status; 999 unsigned irq_zero_count; 1000 unsigned irq_level; 1001 struct delayed_work selftest_work; 1002 1003#ifdef CONFIG_SFC_MTD 1004 struct list_head mtd_list; 1005#endif 1006 1007 void *nic_data; 1008 struct efx_mcdi_data *mcdi; 1009 1010 struct mutex mac_lock; 1011 struct work_struct mac_work; 1012 bool port_enabled; 1013 1014 bool mc_bist_for_other_fn; 1015 bool port_initialized; 1016 struct net_device *net_dev; 1017 1018 struct efx_buffer stats_buffer; 1019 u64 rx_nodesc_drops_total; 1020 u64 rx_nodesc_drops_while_down; 1021 bool rx_nodesc_drops_prev_state; 1022 1023 unsigned int phy_type; 1024 const struct efx_phy_operations *phy_op; 1025 void *phy_data; 1026 struct mdio_if_info mdio; 1027 unsigned int mdio_bus; 1028 enum efx_phy_mode phy_mode; 1029 1030 u32 link_advertising; 1031 struct efx_link_state link_state; 1032 unsigned int n_link_state_changes; 1033 1034 bool unicast_filter; 1035 union efx_multicast_hash multicast_hash; 1036 u8 wanted_fc; 1037 unsigned fc_disable; 1038 1039 atomic_t rx_reset; 1040 enum efx_loopback_mode loopback_mode; 1041 u64 loopback_modes; 1042 1043 void *loopback_selftest; 1044 1045 spinlock_t filter_lock; 1046 void *filter_state; 1047#ifdef CONFIG_RFS_ACCEL 1048 u32 *rps_flow_id; 1049 unsigned int rps_expire_index; 1050#endif 1051 1052 atomic_t active_queues; 1053 atomic_t rxq_flush_pending; 1054 atomic_t rxq_flush_outstanding; 1055 wait_queue_head_t flush_wq; 1056 1057#ifdef CONFIG_SFC_SRIOV 1058 struct efx_vf *vf; 1059 unsigned vf_count; 1060 unsigned vf_init_count; 1061 unsigned vi_scale; 1062#endif 1063 1064 struct efx_ptp_data *ptp_data; 1065 1066 char *vpd_sn; 1067 1068 /* The following fields may be written more often */ 1069 1070 struct delayed_work monitor_work ____cacheline_aligned_in_smp; 1071 spinlock_t biu_lock; 1072 int last_irq_cpu; 1073 spinlock_t stats_lock; 1074 atomic_t n_rx_noskb_drops; 1075}; 1076 1077static inline int efx_dev_registered(struct efx_nic *efx) 1078{ 1079 return efx->net_dev->reg_state == NETREG_REGISTERED; 1080} 1081 1082static inline unsigned int efx_port_num(struct efx_nic *efx) 1083{ 1084 return efx->port_num; 1085} 1086 1087struct efx_mtd_partition { 1088 struct list_head node; 1089 struct mtd_info mtd; 1090 const char *dev_type_name; 1091 const char *type_name; 1092 char name[IFNAMSIZ + 20]; 1093}; 1094 1095/** 1096 * struct efx_nic_type - Efx device type definition 1097 * @mem_map_size: Get memory BAR mapped size 1098 * @probe: Probe the controller 1099 * @remove: Free resources allocated by probe() 1100 * @init: Initialise the controller 1101 * @dimension_resources: Dimension controller resources (buffer table, 1102 * and VIs once the available interrupt resources are clear) 1103 * @fini: Shut down the controller 1104 * @monitor: Periodic function for polling link state and hardware monitor 1105 * @map_reset_reason: Map ethtool reset reason to a reset method 1106 * @map_reset_flags: Map ethtool reset flags to a reset method, if possible 1107 * @reset: Reset the controller hardware and possibly the PHY. This will 1108 * be called while the controller is uninitialised. 1109 * @probe_port: Probe the MAC and PHY 1110 * @remove_port: Free resources allocated by probe_port() 1111 * @handle_global_event: Handle a "global" event (may be %NULL) 1112 * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues) 1113 * @prepare_flush: Prepare the hardware for flushing the DMA queues 1114 * (for Falcon architecture) 1115 * @finish_flush: Clean up after flushing the DMA queues (for Falcon 1116 * architecture) 1117 * @prepare_flr: Prepare for an FLR 1118 * @finish_flr: Clean up after an FLR 1119 * @describe_stats: Describe statistics for ethtool 1120 * @update_stats: Update statistics not provided by event handling. 1121 * Either argument may be %NULL. 1122 * @start_stats: Start the regular fetching of statistics 1123 * @pull_stats: Pull stats from the NIC and wait until they arrive. 1124 * @stop_stats: Stop the regular fetching of statistics 1125 * @set_id_led: Set state of identifying LED or revert to automatic function 1126 * @push_irq_moderation: Apply interrupt moderation value 1127 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY 1128 * @prepare_enable_fc_tx: Prepare MAC to enable pause frame TX (may be %NULL) 1129 * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings 1130 * to the hardware. Serialised by the mac_lock. 1131 * @check_mac_fault: Check MAC fault state. True if fault present. 1132 * @get_wol: Get WoL configuration from driver state 1133 * @set_wol: Push WoL configuration to the NIC 1134 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume) 1135 * @test_chip: Test registers. May use efx_farch_test_registers(), and is 1136 * expected to reset the NIC. 1137 * @test_nvram: Test validity of NVRAM contents 1138 * @mcdi_request: Send an MCDI request with the given header and SDU. 1139 * The SDU length may be any value from 0 up to the protocol- 1140 * defined maximum, but its buffer will be padded to a multiple 1141 * of 4 bytes. 1142 * @mcdi_poll_response: Test whether an MCDI response is available. 1143 * @mcdi_read_response: Read the MCDI response PDU. The offset will 1144 * be a multiple of 4. The length may not be, but the buffer 1145 * will be padded so it is safe to round up. 1146 * @mcdi_poll_reboot: Test whether the MCDI has rebooted. If so, 1147 * return an appropriate error code for aborting any current 1148 * request; otherwise return 0. 1149 * @irq_enable_master: Enable IRQs on the NIC. Each event queue must 1150 * be separately enabled after this. 1151 * @irq_test_generate: Generate a test IRQ 1152 * @irq_disable_non_ev: Disable non-event IRQs on the NIC. Each event 1153 * queue must be separately disabled before this. 1154 * @irq_handle_msi: Handle MSI for a channel. The @dev_id argument is 1155 * a pointer to the &struct efx_msi_context for the channel. 1156 * @irq_handle_legacy: Handle legacy interrupt. The @dev_id argument 1157 * is a pointer to the &struct efx_nic. 1158 * @tx_probe: Allocate resources for TX queue 1159 * @tx_init: Initialise TX queue on the NIC 1160 * @tx_remove: Free resources for TX queue 1161 * @tx_write: Write TX descriptors and doorbell 1162 * @rx_push_rss_config: Write RSS hash key and indirection table to the NIC 1163 * @rx_probe: Allocate resources for RX queue 1164 * @rx_init: Initialise RX queue on the NIC 1165 * @rx_remove: Free resources for RX queue 1166 * @rx_write: Write RX descriptors and doorbell 1167 * @rx_defer_refill: Generate a refill reminder event 1168 * @ev_probe: Allocate resources for event queue 1169 * @ev_init: Initialise event queue on the NIC 1170 * @ev_fini: Deinitialise event queue on the NIC 1171 * @ev_remove: Free resources for event queue 1172 * @ev_process: Process events for a queue, up to the given NAPI quota 1173 * @ev_read_ack: Acknowledge read events on a queue, rearming its IRQ 1174 * @ev_test_generate: Generate a test event 1175 * @filter_table_probe: Probe filter capabilities and set up filter software state 1176 * @filter_table_restore: Restore filters removed from hardware 1177 * @filter_table_remove: Remove filters from hardware and tear down software state 1178 * @filter_update_rx_scatter: Update filters after change to rx scatter setting 1179 * @filter_insert: add or replace a filter 1180 * @filter_remove_safe: remove a filter by ID, carefully 1181 * @filter_get_safe: retrieve a filter by ID, carefully 1182 * @filter_clear_rx: Remove all RX filters whose priority is less than or 1183 * equal to the given priority and is not %EFX_FILTER_PRI_AUTO 1184 * @filter_count_rx_used: Get the number of filters in use at a given priority 1185 * @filter_get_rx_id_limit: Get maximum value of a filter id, plus 1 1186 * @filter_get_rx_ids: Get list of RX filters at a given priority 1187 * @filter_rfs_insert: Add or replace a filter for RFS. This must be 1188 * atomic. The hardware change may be asynchronous but should 1189 * not be delayed for long. It may fail if this can't be done 1190 * atomically. 1191 * @filter_rfs_expire_one: Consider expiring a filter inserted for RFS. 1192 * This must check whether the specified table entry is used by RFS 1193 * and that rps_may_expire_flow() returns true for it. 1194 * @mtd_probe: Probe and add MTD partitions associated with this net device, 1195 * using efx_mtd_add() 1196 * @mtd_rename: Set an MTD partition name using the net device name 1197 * @mtd_read: Read from an MTD partition 1198 * @mtd_erase: Erase part of an MTD partition 1199 * @mtd_write: Write to an MTD partition 1200 * @mtd_sync: Wait for write-back to complete on MTD partition. This 1201 * also notifies the driver that a writer has finished using this 1202 * partition. 1203 * @ptp_write_host_time: Send host time to MC as part of sync protocol 1204 * @ptp_set_ts_sync_events: Enable or disable sync events for inline RX 1205 * timestamping, possibly only temporarily for the purposes of a reset. 1206 * @ptp_set_ts_config: Set hardware timestamp configuration. The flags 1207 * and tx_type will already have been validated but this operation 1208 * must validate and update rx_filter. 1209 * @revision: Hardware architecture revision 1210 * @txd_ptr_tbl_base: TX descriptor ring base address 1211 * @rxd_ptr_tbl_base: RX descriptor ring base address 1212 * @buf_tbl_base: Buffer table base address 1213 * @evq_ptr_tbl_base: Event queue pointer table base address 1214 * @evq_rptr_tbl_base: Event queue read-pointer table base address 1215 * @max_dma_mask: Maximum possible DMA mask 1216 * @rx_prefix_size: Size of RX prefix before packet data 1217 * @rx_hash_offset: Offset of RX flow hash within prefix 1218 * @rx_ts_offset: Offset of timestamp within prefix 1219 * @rx_buffer_padding: Size of padding at end of RX packet 1220 * @can_rx_scatter: NIC is able to scatter packets to multiple buffers 1221 * @always_rx_scatter: NIC will always scatter packets to multiple buffers 1222 * @max_interrupt_mode: Highest capability interrupt mode supported 1223 * from &enum efx_init_mode. 1224 * @timer_period_max: Maximum period of interrupt timer (in ticks) 1225 * @offload_features: net_device feature flags for protocol offload 1226 * features implemented in hardware 1227 * @mcdi_max_ver: Maximum MCDI version supported 1228 * @hwtstamp_filters: Mask of hardware timestamp filter types supported 1229 */ 1230struct efx_nic_type { 1231 unsigned int (*mem_map_size)(struct efx_nic *efx); 1232 int (*probe)(struct efx_nic *efx); 1233 void (*remove)(struct efx_nic *efx); 1234 int (*init)(struct efx_nic *efx); 1235 int (*dimension_resources)(struct efx_nic *efx); 1236 void (*fini)(struct efx_nic *efx); 1237 void (*monitor)(struct efx_nic *efx); 1238 enum reset_type (*map_reset_reason)(enum reset_type reason); 1239 int (*map_reset_flags)(u32 *flags); 1240 int (*reset)(struct efx_nic *efx, enum reset_type method); 1241 int (*probe_port)(struct efx_nic *efx); 1242 void (*remove_port)(struct efx_nic *efx); 1243 bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *); 1244 int (*fini_dmaq)(struct efx_nic *efx); 1245 void (*prepare_flush)(struct efx_nic *efx); 1246 void (*finish_flush)(struct efx_nic *efx); 1247 void (*prepare_flr)(struct efx_nic *efx); 1248 void (*finish_flr)(struct efx_nic *efx); 1249 size_t (*describe_stats)(struct efx_nic *efx, u8 *names); 1250 size_t (*update_stats)(struct efx_nic *efx, u64 *full_stats, 1251 struct rtnl_link_stats64 *core_stats); 1252 void (*start_stats)(struct efx_nic *efx); 1253 void (*pull_stats)(struct efx_nic *efx); 1254 void (*stop_stats)(struct efx_nic *efx); 1255 void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode); 1256 void (*push_irq_moderation)(struct efx_channel *channel); 1257 int (*reconfigure_port)(struct efx_nic *efx); 1258 void (*prepare_enable_fc_tx)(struct efx_nic *efx); 1259 int (*reconfigure_mac)(struct efx_nic *efx); 1260 bool (*check_mac_fault)(struct efx_nic *efx); 1261 void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol); 1262 int (*set_wol)(struct efx_nic *efx, u32 type); 1263 void (*resume_wol)(struct efx_nic *efx); 1264 int (*test_chip)(struct efx_nic *efx, struct efx_self_tests *tests); 1265 int (*test_nvram)(struct efx_nic *efx); 1266 void (*mcdi_request)(struct efx_nic *efx, 1267 const efx_dword_t *hdr, size_t hdr_len, 1268 const efx_dword_t *sdu, size_t sdu_len); 1269 bool (*mcdi_poll_response)(struct efx_nic *efx); 1270 void (*mcdi_read_response)(struct efx_nic *efx, efx_dword_t *pdu, 1271 size_t pdu_offset, size_t pdu_len); 1272 int (*mcdi_poll_reboot)(struct efx_nic *efx); 1273 void (*irq_enable_master)(struct efx_nic *efx); 1274 void (*irq_test_generate)(struct efx_nic *efx); 1275 void (*irq_disable_non_ev)(struct efx_nic *efx); 1276 irqreturn_t (*irq_handle_msi)(int irq, void *dev_id); 1277 irqreturn_t (*irq_handle_legacy)(int irq, void *dev_id); 1278 int (*tx_probe)(struct efx_tx_queue *tx_queue); 1279 void (*tx_init)(struct efx_tx_queue *tx_queue); 1280 void (*tx_remove)(struct efx_tx_queue *tx_queue); 1281 void (*tx_write)(struct efx_tx_queue *tx_queue); 1282 void (*rx_push_rss_config)(struct efx_nic *efx); 1283 int (*rx_probe)(struct efx_rx_queue *rx_queue); 1284 void (*rx_init)(struct efx_rx_queue *rx_queue); 1285 void (*rx_remove)(struct efx_rx_queue *rx_queue); 1286 void (*rx_write)(struct efx_rx_queue *rx_queue); 1287 void (*rx_defer_refill)(struct efx_rx_queue *rx_queue); 1288 int (*ev_probe)(struct efx_channel *channel); 1289 int (*ev_init)(struct efx_channel *channel); 1290 void (*ev_fini)(struct efx_channel *channel); 1291 void (*ev_remove)(struct efx_channel *channel); 1292 int (*ev_process)(struct efx_channel *channel, int quota); 1293 void (*ev_read_ack)(struct efx_channel *channel); 1294 void (*ev_test_generate)(struct efx_channel *channel); 1295 int (*filter_table_probe)(struct efx_nic *efx); 1296 void (*filter_table_restore)(struct efx_nic *efx); 1297 void (*filter_table_remove)(struct efx_nic *efx); 1298 void (*filter_update_rx_scatter)(struct efx_nic *efx); 1299 s32 (*filter_insert)(struct efx_nic *efx, 1300 struct efx_filter_spec *spec, bool replace); 1301 int (*filter_remove_safe)(struct efx_nic *efx, 1302 enum efx_filter_priority priority, 1303 u32 filter_id); 1304 int (*filter_get_safe)(struct efx_nic *efx, 1305 enum efx_filter_priority priority, 1306 u32 filter_id, struct efx_filter_spec *); 1307 int (*filter_clear_rx)(struct efx_nic *efx, 1308 enum efx_filter_priority priority); 1309 u32 (*filter_count_rx_used)(struct efx_nic *efx, 1310 enum efx_filter_priority priority); 1311 u32 (*filter_get_rx_id_limit)(struct efx_nic *efx); 1312 s32 (*filter_get_rx_ids)(struct efx_nic *efx, 1313 enum efx_filter_priority priority, 1314 u32 *buf, u32 size); 1315#ifdef CONFIG_RFS_ACCEL 1316 s32 (*filter_rfs_insert)(struct efx_nic *efx, 1317 struct efx_filter_spec *spec); 1318 bool (*filter_rfs_expire_one)(struct efx_nic *efx, u32 flow_id, 1319 unsigned int index); 1320#endif 1321#ifdef CONFIG_SFC_MTD 1322 int (*mtd_probe)(struct efx_nic *efx); 1323 void (*mtd_rename)(struct efx_mtd_partition *part); 1324 int (*mtd_read)(struct mtd_info *mtd, loff_t start, size_t len, 1325 size_t *retlen, u8 *buffer); 1326 int (*mtd_erase)(struct mtd_info *mtd, loff_t start, size_t len); 1327 int (*mtd_write)(struct mtd_info *mtd, loff_t start, size_t len, 1328 size_t *retlen, const u8 *buffer); 1329 int (*mtd_sync)(struct mtd_info *mtd); 1330#endif 1331 void (*ptp_write_host_time)(struct efx_nic *efx, u32 host_time); 1332 int (*ptp_set_ts_sync_events)(struct efx_nic *efx, bool en, bool temp); 1333 int (*ptp_set_ts_config)(struct efx_nic *efx, 1334 struct hwtstamp_config *init); 1335 int (*sriov_init)(struct efx_nic *efx); 1336 void (*sriov_fini)(struct efx_nic *efx); 1337 void (*sriov_mac_address_changed)(struct efx_nic *efx); 1338 bool (*sriov_wanted)(struct efx_nic *efx); 1339 void (*sriov_reset)(struct efx_nic *efx); 1340 1341 int revision; 1342 unsigned int txd_ptr_tbl_base; 1343 unsigned int rxd_ptr_tbl_base; 1344 unsigned int buf_tbl_base; 1345 unsigned int evq_ptr_tbl_base; 1346 unsigned int evq_rptr_tbl_base; 1347 u64 max_dma_mask; 1348 unsigned int rx_prefix_size; 1349 unsigned int rx_hash_offset; 1350 unsigned int rx_ts_offset; 1351 unsigned int rx_buffer_padding; 1352 bool can_rx_scatter; 1353 bool always_rx_scatter; 1354 unsigned int max_interrupt_mode; 1355 unsigned int timer_period_max; 1356 netdev_features_t offload_features; 1357 int mcdi_max_ver; 1358 unsigned int max_rx_ip_filters; 1359 u32 hwtstamp_filters; 1360}; 1361 1362/************************************************************************** 1363 * 1364 * Prototypes and inline functions 1365 * 1366 *************************************************************************/ 1367 1368static inline struct efx_channel * 1369efx_get_channel(struct efx_nic *efx, unsigned index) 1370{ 1371 EFX_BUG_ON_PARANOID(index >= efx->n_channels); 1372 return efx->channel[index]; 1373} 1374 1375/* Iterate over all used channels */ 1376#define efx_for_each_channel(_channel, _efx) \ 1377 for (_channel = (_efx)->channel[0]; \ 1378 _channel; \ 1379 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \ 1380 (_efx)->channel[_channel->channel + 1] : NULL) 1381 1382/* Iterate over all used channels in reverse */ 1383#define efx_for_each_channel_rev(_channel, _efx) \ 1384 for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \ 1385 _channel; \ 1386 _channel = _channel->channel ? \ 1387 (_efx)->channel[_channel->channel - 1] : NULL) 1388 1389static inline struct efx_tx_queue * 1390efx_get_tx_queue(struct efx_nic *efx, unsigned index, unsigned type) 1391{ 1392 EFX_BUG_ON_PARANOID(index >= efx->n_tx_channels || 1393 type >= EFX_TXQ_TYPES); 1394 return &efx->channel[efx->tx_channel_offset + index]->tx_queue[type]; 1395} 1396 1397static inline bool efx_channel_has_tx_queues(struct efx_channel *channel) 1398{ 1399 return channel->channel - channel->efx->tx_channel_offset < 1400 channel->efx->n_tx_channels; 1401} 1402 1403static inline struct efx_tx_queue * 1404efx_channel_get_tx_queue(struct efx_channel *channel, unsigned type) 1405{ 1406 EFX_BUG_ON_PARANOID(!efx_channel_has_tx_queues(channel) || 1407 type >= EFX_TXQ_TYPES); 1408 return &channel->tx_queue[type]; 1409} 1410 1411static inline bool efx_tx_queue_used(struct efx_tx_queue *tx_queue) 1412{ 1413 return !(tx_queue->efx->net_dev->num_tc < 2 && 1414 tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI); 1415} 1416 1417/* Iterate over all TX queues belonging to a channel */ 1418#define efx_for_each_channel_tx_queue(_tx_queue, _channel) \ 1419 if (!efx_channel_has_tx_queues(_channel)) \ 1420 ; \ 1421 else \ 1422 for (_tx_queue = (_channel)->tx_queue; \ 1423 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES && \ 1424 efx_tx_queue_used(_tx_queue); \ 1425 _tx_queue++) 1426 1427/* Iterate over all possible TX queues belonging to a channel */ 1428#define efx_for_each_possible_channel_tx_queue(_tx_queue, _channel) \ 1429 if (!efx_channel_has_tx_queues(_channel)) \ 1430 ; \ 1431 else \ 1432 for (_tx_queue = (_channel)->tx_queue; \ 1433 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \ 1434 _tx_queue++) 1435 1436static inline bool efx_channel_has_rx_queue(struct efx_channel *channel) 1437{ 1438 return channel->rx_queue.core_index >= 0; 1439} 1440 1441static inline struct efx_rx_queue * 1442efx_channel_get_rx_queue(struct efx_channel *channel) 1443{ 1444 EFX_BUG_ON_PARANOID(!efx_channel_has_rx_queue(channel)); 1445 return &channel->rx_queue; 1446} 1447 1448/* Iterate over all RX queues belonging to a channel */ 1449#define efx_for_each_channel_rx_queue(_rx_queue, _channel) \ 1450 if (!efx_channel_has_rx_queue(_channel)) \ 1451 ; \ 1452 else \ 1453 for (_rx_queue = &(_channel)->rx_queue; \ 1454 _rx_queue; \ 1455 _rx_queue = NULL) 1456 1457static inline struct efx_channel * 1458efx_rx_queue_channel(struct efx_rx_queue *rx_queue) 1459{ 1460 return container_of(rx_queue, struct efx_channel, rx_queue); 1461} 1462 1463static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue) 1464{ 1465 return efx_rx_queue_channel(rx_queue)->channel; 1466} 1467 1468/* Returns a pointer to the specified receive buffer in the RX 1469 * descriptor queue. 1470 */ 1471static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue, 1472 unsigned int index) 1473{ 1474 return &rx_queue->buffer[index]; 1475} 1476 1477/** 1478 * EFX_MAX_FRAME_LEN - calculate maximum frame length 1479 * 1480 * This calculates the maximum frame length that will be used for a 1481 * given MTU. The frame length will be equal to the MTU plus a 1482 * constant amount of header space and padding. This is the quantity 1483 * that the net driver will program into the MAC as the maximum frame 1484 * length. 1485 * 1486 * The 10G MAC requires 8-byte alignment on the frame 1487 * length, so we round up to the nearest 8. 1488 * 1489 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an 1490 * XGMII cycle). If the frame length reaches the maximum value in the 1491 * same cycle, the XMAC can miss the IPG altogether. We work around 1492 * this by adding a further 16 bytes. 1493 */ 1494#define EFX_MAX_FRAME_LEN(mtu) \ 1495 ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16) 1496 1497static inline bool efx_xmit_with_hwtstamp(struct sk_buff *skb) 1498{ 1499 return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP; 1500} 1501static inline void efx_xmit_hwtstamp_pending(struct sk_buff *skb) 1502{ 1503 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1504} 1505 1506#endif /* EFX_NET_DRIVER_H */ 1507