1/*
2 * drivers/net/phy/lxt.c
3 *
4 * Driver for Intel LXT PHYs
5 *
6 * Author: Andy Fleming
7 *
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
9 *
10 * This program is free software; you can redistribute  it and/or modify it
11 * under  the terms of  the GNU General  Public License as published by the
12 * Free Software Foundation;  either version 2 of the  License, or (at your
13 * option) any later version.
14 *
15 */
16#include <linux/kernel.h>
17#include <linux/string.h>
18#include <linux/errno.h>
19#include <linux/unistd.h>
20#include <linux/interrupt.h>
21#include <linux/init.h>
22#include <linux/delay.h>
23#include <linux/netdevice.h>
24#include <linux/etherdevice.h>
25#include <linux/skbuff.h>
26#include <linux/spinlock.h>
27#include <linux/mm.h>
28#include <linux/module.h>
29#include <linux/mii.h>
30#include <linux/ethtool.h>
31#include <linux/phy.h>
32
33#include <asm/io.h>
34#include <asm/irq.h>
35#include <asm/uaccess.h>
36
37/* The Level one LXT970 is used by many boards				     */
38
39#define MII_LXT970_IER       17  /* Interrupt Enable Register */
40
41#define MII_LXT970_IER_IEN	0x0002
42
43#define MII_LXT970_ISR       18  /* Interrupt Status Register */
44
45#define MII_LXT970_CONFIG    19  /* Configuration Register    */
46
47/* ------------------------------------------------------------------------- */
48/* The Level one LXT971 is used on some of my custom boards                  */
49
50/* register definitions for the 971 */
51#define MII_LXT971_IER		18  /* Interrupt Enable Register */
52#define MII_LXT971_IER_IEN	0x00f2
53
54#define MII_LXT971_ISR		19  /* Interrupt Status Register */
55
56/* register definitions for the 973 */
57#define MII_LXT973_PCR 16 /* Port Configuration Register */
58#define PCR_FIBER_SELECT 1
59
60MODULE_DESCRIPTION("Intel LXT PHY driver");
61MODULE_AUTHOR("Andy Fleming");
62MODULE_LICENSE("GPL");
63
64static int lxt970_ack_interrupt(struct phy_device *phydev)
65{
66	int err;
67
68	err = phy_read(phydev, MII_BMSR);
69
70	if (err < 0)
71		return err;
72
73	err = phy_read(phydev, MII_LXT970_ISR);
74
75	if (err < 0)
76		return err;
77
78	return 0;
79}
80
81static int lxt970_config_intr(struct phy_device *phydev)
82{
83	int err;
84
85	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
86		err = phy_write(phydev, MII_LXT970_IER, MII_LXT970_IER_IEN);
87	else
88		err = phy_write(phydev, MII_LXT970_IER, 0);
89
90	return err;
91}
92
93static int lxt970_config_init(struct phy_device *phydev)
94{
95	int err;
96
97	err = phy_write(phydev, MII_LXT970_CONFIG, 0);
98
99	return err;
100}
101
102
103static int lxt971_ack_interrupt(struct phy_device *phydev)
104{
105	int err = phy_read(phydev, MII_LXT971_ISR);
106
107	if (err < 0)
108		return err;
109
110	return 0;
111}
112
113static int lxt971_config_intr(struct phy_device *phydev)
114{
115	int err;
116
117	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
118		err = phy_write(phydev, MII_LXT971_IER, MII_LXT971_IER_IEN);
119	else
120		err = phy_write(phydev, MII_LXT971_IER, 0);
121
122	return err;
123}
124
125/*
126 * A2 version of LXT973 chip has an ERRATA: it randomly return the contents
127 * of the previous even register when you read a odd register regularly
128 */
129
130static int lxt973a2_update_link(struct phy_device *phydev)
131{
132	int status;
133	int control;
134	int retry = 8; /* we try 8 times */
135
136	/* Do a fake read */
137	status = phy_read(phydev, MII_BMSR);
138
139	if (status < 0)
140		return status;
141
142	control = phy_read(phydev, MII_BMCR);
143	if (control < 0)
144		return control;
145
146	do {
147		/* Read link and autonegotiation status */
148		status = phy_read(phydev, MII_BMSR);
149	} while (status >= 0 && retry-- && status == control);
150
151	if (status < 0)
152		return status;
153
154	if ((status & BMSR_LSTATUS) == 0)
155		phydev->link = 0;
156	else
157		phydev->link = 1;
158
159	return 0;
160}
161
162static int lxt973a2_read_status(struct phy_device *phydev)
163{
164	int adv;
165	int err;
166	int lpa;
167	int lpagb = 0;
168
169	/* Update the link, but return if there was an error */
170	err = lxt973a2_update_link(phydev);
171	if (err)
172		return err;
173
174	if (AUTONEG_ENABLE == phydev->autoneg) {
175		int retry = 1;
176
177		adv = phy_read(phydev, MII_ADVERTISE);
178
179		if (adv < 0)
180			return adv;
181
182		do {
183			lpa = phy_read(phydev, MII_LPA);
184
185			if (lpa < 0)
186				return lpa;
187
188			/* If both registers are equal, it is suspect but not
189			* impossible, hence a new try
190			*/
191		} while (lpa == adv && retry--);
192
193		lpa &= adv;
194
195		phydev->speed = SPEED_10;
196		phydev->duplex = DUPLEX_HALF;
197		phydev->pause = phydev->asym_pause = 0;
198
199		if (lpagb & (LPA_1000FULL | LPA_1000HALF)) {
200			phydev->speed = SPEED_1000;
201
202			if (lpagb & LPA_1000FULL)
203				phydev->duplex = DUPLEX_FULL;
204		} else if (lpa & (LPA_100FULL | LPA_100HALF)) {
205			phydev->speed = SPEED_100;
206
207			if (lpa & LPA_100FULL)
208				phydev->duplex = DUPLEX_FULL;
209		} else {
210			if (lpa & LPA_10FULL)
211				phydev->duplex = DUPLEX_FULL;
212		}
213
214		if (phydev->duplex == DUPLEX_FULL) {
215			phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
216			phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
217		}
218	} else {
219		int bmcr = phy_read(phydev, MII_BMCR);
220
221		if (bmcr < 0)
222			return bmcr;
223
224		if (bmcr & BMCR_FULLDPLX)
225			phydev->duplex = DUPLEX_FULL;
226		else
227			phydev->duplex = DUPLEX_HALF;
228
229		if (bmcr & BMCR_SPEED1000)
230			phydev->speed = SPEED_1000;
231		else if (bmcr & BMCR_SPEED100)
232			phydev->speed = SPEED_100;
233		else
234			phydev->speed = SPEED_10;
235
236		phydev->pause = phydev->asym_pause = 0;
237	}
238
239	return 0;
240}
241
242static int lxt973_probe(struct phy_device *phydev)
243{
244	int val = phy_read(phydev, MII_LXT973_PCR);
245
246	if (val & PCR_FIBER_SELECT) {
247		/*
248		 * If fiber is selected, then the only correct setting
249		 * is 100Mbps, full duplex, and auto negotiation off.
250		 */
251		val = phy_read(phydev, MII_BMCR);
252		val |= (BMCR_SPEED100 | BMCR_FULLDPLX);
253		val &= ~BMCR_ANENABLE;
254		phy_write(phydev, MII_BMCR, val);
255		/* Remember that the port is in fiber mode. */
256		phydev->priv = lxt973_probe;
257	} else {
258		phydev->priv = NULL;
259	}
260	return 0;
261}
262
263static int lxt973_config_aneg(struct phy_device *phydev)
264{
265	/* Do nothing if port is in fiber mode. */
266	return phydev->priv ? 0 : genphy_config_aneg(phydev);
267}
268
269static struct phy_driver lxt97x_driver[] = {
270{
271	.phy_id		= 0x78100000,
272	.name		= "LXT970",
273	.phy_id_mask	= 0xfffffff0,
274	.features	= PHY_BASIC_FEATURES,
275	.flags		= PHY_HAS_INTERRUPT,
276	.config_init	= lxt970_config_init,
277	.config_aneg	= genphy_config_aneg,
278	.read_status	= genphy_read_status,
279	.ack_interrupt	= lxt970_ack_interrupt,
280	.config_intr	= lxt970_config_intr,
281	.driver		= { .owner = THIS_MODULE,},
282}, {
283	.phy_id		= 0x001378e0,
284	.name		= "LXT971",
285	.phy_id_mask	= 0xfffffff0,
286	.features	= PHY_BASIC_FEATURES,
287	.flags		= PHY_HAS_INTERRUPT,
288	.config_aneg	= genphy_config_aneg,
289	.read_status	= genphy_read_status,
290	.ack_interrupt	= lxt971_ack_interrupt,
291	.config_intr	= lxt971_config_intr,
292	.driver		= { .owner = THIS_MODULE,},
293}, {
294	.phy_id		= 0x00137a10,
295	.name		= "LXT973-A2",
296	.phy_id_mask	= 0xffffffff,
297	.features	= PHY_BASIC_FEATURES,
298	.flags		= 0,
299	.probe		= lxt973_probe,
300	.config_aneg	= lxt973_config_aneg,
301	.read_status	= lxt973a2_read_status,
302	.driver		= { .owner = THIS_MODULE,},
303}, {
304	.phy_id		= 0x00137a10,
305	.name		= "LXT973",
306	.phy_id_mask	= 0xfffffff0,
307	.features	= PHY_BASIC_FEATURES,
308	.flags		= 0,
309	.probe		= lxt973_probe,
310	.config_aneg	= lxt973_config_aneg,
311	.read_status	= genphy_read_status,
312	.driver		= { .owner = THIS_MODULE,},
313} };
314
315module_phy_driver(lxt97x_driver);
316
317static struct mdio_device_id __maybe_unused lxt_tbl[] = {
318	{ 0x78100000, 0xfffffff0 },
319	{ 0x001378e0, 0xfffffff0 },
320	{ 0x00137a10, 0xfffffff0 },
321	{ }
322};
323
324MODULE_DEVICE_TABLE(mdio, lxt_tbl);
325