1/* 2 * Linux driver for VMware's vmxnet3 ethernet NIC. 3 * 4 * Copyright (C) 2008-2009, VMware, Inc. All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; version 2 of the License and no later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 13 * NON INFRINGEMENT. See the GNU General Public License for more 14 * details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * The full GNU General Public License is included in this distribution in 21 * the file called "COPYING". 22 * 23 * Maintained by: Shreyas Bhatewara <pv-drivers@vmware.com> 24 * 25 */ 26 27#ifndef _VMXNET3_DEFS_H_ 28#define _VMXNET3_DEFS_H_ 29 30#include "upt1_defs.h" 31 32/* all registers are 32 bit wide */ 33/* BAR 1 */ 34enum { 35 VMXNET3_REG_VRRS = 0x0, /* Vmxnet3 Revision Report Selection */ 36 VMXNET3_REG_UVRS = 0x8, /* UPT Version Report Selection */ 37 VMXNET3_REG_DSAL = 0x10, /* Driver Shared Address Low */ 38 VMXNET3_REG_DSAH = 0x18, /* Driver Shared Address High */ 39 VMXNET3_REG_CMD = 0x20, /* Command */ 40 VMXNET3_REG_MACL = 0x28, /* MAC Address Low */ 41 VMXNET3_REG_MACH = 0x30, /* MAC Address High */ 42 VMXNET3_REG_ICR = 0x38, /* Interrupt Cause Register */ 43 VMXNET3_REG_ECR = 0x40 /* Event Cause Register */ 44}; 45 46/* BAR 0 */ 47enum { 48 VMXNET3_REG_IMR = 0x0, /* Interrupt Mask Register */ 49 VMXNET3_REG_TXPROD = 0x600, /* Tx Producer Index */ 50 VMXNET3_REG_RXPROD = 0x800, /* Rx Producer Index for ring 1 */ 51 VMXNET3_REG_RXPROD2 = 0xA00 /* Rx Producer Index for ring 2 */ 52}; 53 54#define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */ 55#define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */ 56 57#define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */ 58#define VMXNET3_REG_ALIGN_MASK 0x7 59 60/* I/O Mapped access to registers */ 61#define VMXNET3_IO_TYPE_PT 0 62#define VMXNET3_IO_TYPE_VD 1 63#define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF)) 64#define VMXNET3_IO_TYPE(addr) ((addr) >> 24) 65#define VMXNET3_IO_REG(addr) ((addr) & 0xFFFFFF) 66 67enum { 68 VMXNET3_CMD_FIRST_SET = 0xCAFE0000, 69 VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET, 70 VMXNET3_CMD_QUIESCE_DEV, 71 VMXNET3_CMD_RESET_DEV, 72 VMXNET3_CMD_UPDATE_RX_MODE, 73 VMXNET3_CMD_UPDATE_MAC_FILTERS, 74 VMXNET3_CMD_UPDATE_VLAN_FILTERS, 75 VMXNET3_CMD_UPDATE_RSSIDT, 76 VMXNET3_CMD_UPDATE_IML, 77 VMXNET3_CMD_UPDATE_PMCFG, 78 VMXNET3_CMD_UPDATE_FEATURE, 79 VMXNET3_CMD_LOAD_PLUGIN, 80 81 VMXNET3_CMD_FIRST_GET = 0xF00D0000, 82 VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET, 83 VMXNET3_CMD_GET_STATS, 84 VMXNET3_CMD_GET_LINK, 85 VMXNET3_CMD_GET_PERM_MAC_LO, 86 VMXNET3_CMD_GET_PERM_MAC_HI, 87 VMXNET3_CMD_GET_DID_LO, 88 VMXNET3_CMD_GET_DID_HI, 89 VMXNET3_CMD_GET_DEV_EXTRA_INFO, 90 VMXNET3_CMD_GET_CONF_INTR 91}; 92 93/* 94 * Little Endian layout of bitfields - 95 * Byte 0 : 7.....len.....0 96 * Byte 1 : rsvd gen 13.len.8 97 * Byte 2 : 5.msscof.0 ext1 dtype 98 * Byte 3 : 13...msscof...6 99 * 100 * Big Endian layout of bitfields - 101 * Byte 0: 13...msscof...6 102 * Byte 1 : 5.msscof.0 ext1 dtype 103 * Byte 2 : rsvd gen 13.len.8 104 * Byte 3 : 7.....len.....0 105 * 106 * Thus, le32_to_cpu on the dword will allow the big endian driver to read 107 * the bit fields correctly. And cpu_to_le32 will convert bitfields 108 * bit fields written by big endian driver to format required by device. 109 */ 110 111struct Vmxnet3_TxDesc { 112 __le64 addr; 113 114#ifdef __BIG_ENDIAN_BITFIELD 115 u32 msscof:14; /* MSS, checksum offset, flags */ 116 u32 ext1:1; 117 u32 dtype:1; /* descriptor type */ 118 u32 rsvd:1; 119 u32 gen:1; /* generation bit */ 120 u32 len:14; 121#else 122 u32 len:14; 123 u32 gen:1; /* generation bit */ 124 u32 rsvd:1; 125 u32 dtype:1; /* descriptor type */ 126 u32 ext1:1; 127 u32 msscof:14; /* MSS, checksum offset, flags */ 128#endif /* __BIG_ENDIAN_BITFIELD */ 129 130#ifdef __BIG_ENDIAN_BITFIELD 131 u32 tci:16; /* Tag to Insert */ 132 u32 ti:1; /* VLAN Tag Insertion */ 133 u32 ext2:1; 134 u32 cq:1; /* completion request */ 135 u32 eop:1; /* End Of Packet */ 136 u32 om:2; /* offload mode */ 137 u32 hlen:10; /* header len */ 138#else 139 u32 hlen:10; /* header len */ 140 u32 om:2; /* offload mode */ 141 u32 eop:1; /* End Of Packet */ 142 u32 cq:1; /* completion request */ 143 u32 ext2:1; 144 u32 ti:1; /* VLAN Tag Insertion */ 145 u32 tci:16; /* Tag to Insert */ 146#endif /* __BIG_ENDIAN_BITFIELD */ 147}; 148 149/* TxDesc.OM values */ 150#define VMXNET3_OM_NONE 0 151#define VMXNET3_OM_CSUM 2 152#define VMXNET3_OM_TSO 3 153 154/* fields in TxDesc we access w/o using bit fields */ 155#define VMXNET3_TXD_EOP_SHIFT 12 156#define VMXNET3_TXD_CQ_SHIFT 13 157#define VMXNET3_TXD_GEN_SHIFT 14 158#define VMXNET3_TXD_EOP_DWORD_SHIFT 3 159#define VMXNET3_TXD_GEN_DWORD_SHIFT 2 160 161#define VMXNET3_TXD_CQ (1 << VMXNET3_TXD_CQ_SHIFT) 162#define VMXNET3_TXD_EOP (1 << VMXNET3_TXD_EOP_SHIFT) 163#define VMXNET3_TXD_GEN (1 << VMXNET3_TXD_GEN_SHIFT) 164 165#define VMXNET3_HDR_COPY_SIZE 128 166 167 168struct Vmxnet3_TxDataDesc { 169 u8 data[VMXNET3_HDR_COPY_SIZE]; 170}; 171 172#define VMXNET3_TCD_GEN_SHIFT 31 173#define VMXNET3_TCD_GEN_SIZE 1 174#define VMXNET3_TCD_TXIDX_SHIFT 0 175#define VMXNET3_TCD_TXIDX_SIZE 12 176#define VMXNET3_TCD_GEN_DWORD_SHIFT 3 177 178struct Vmxnet3_TxCompDesc { 179 u32 txdIdx:12; /* Index of the EOP TxDesc */ 180 u32 ext1:20; 181 182 __le32 ext2; 183 __le32 ext3; 184 185 u32 rsvd:24; 186 u32 type:7; /* completion type */ 187 u32 gen:1; /* generation bit */ 188}; 189 190struct Vmxnet3_RxDesc { 191 __le64 addr; 192 193#ifdef __BIG_ENDIAN_BITFIELD 194 u32 gen:1; /* Generation bit */ 195 u32 rsvd:15; 196 u32 dtype:1; /* Descriptor type */ 197 u32 btype:1; /* Buffer Type */ 198 u32 len:14; 199#else 200 u32 len:14; 201 u32 btype:1; /* Buffer Type */ 202 u32 dtype:1; /* Descriptor type */ 203 u32 rsvd:15; 204 u32 gen:1; /* Generation bit */ 205#endif 206 u32 ext1; 207}; 208 209/* values of RXD.BTYPE */ 210#define VMXNET3_RXD_BTYPE_HEAD 0 /* head only */ 211#define VMXNET3_RXD_BTYPE_BODY 1 /* body only */ 212 213/* fields in RxDesc we access w/o using bit fields */ 214#define VMXNET3_RXD_BTYPE_SHIFT 14 215#define VMXNET3_RXD_GEN_SHIFT 31 216 217struct Vmxnet3_RxCompDesc { 218#ifdef __BIG_ENDIAN_BITFIELD 219 u32 ext2:1; 220 u32 cnc:1; /* Checksum Not Calculated */ 221 u32 rssType:4; /* RSS hash type used */ 222 u32 rqID:10; /* rx queue/ring ID */ 223 u32 sop:1; /* Start of Packet */ 224 u32 eop:1; /* End of Packet */ 225 u32 ext1:2; 226 u32 rxdIdx:12; /* Index of the RxDesc */ 227#else 228 u32 rxdIdx:12; /* Index of the RxDesc */ 229 u32 ext1:2; 230 u32 eop:1; /* End of Packet */ 231 u32 sop:1; /* Start of Packet */ 232 u32 rqID:10; /* rx queue/ring ID */ 233 u32 rssType:4; /* RSS hash type used */ 234 u32 cnc:1; /* Checksum Not Calculated */ 235 u32 ext2:1; 236#endif /* __BIG_ENDIAN_BITFIELD */ 237 238 __le32 rssHash; /* RSS hash value */ 239 240#ifdef __BIG_ENDIAN_BITFIELD 241 u32 tci:16; /* Tag stripped */ 242 u32 ts:1; /* Tag is stripped */ 243 u32 err:1; /* Error */ 244 u32 len:14; /* data length */ 245#else 246 u32 len:14; /* data length */ 247 u32 err:1; /* Error */ 248 u32 ts:1; /* Tag is stripped */ 249 u32 tci:16; /* Tag stripped */ 250#endif /* __BIG_ENDIAN_BITFIELD */ 251 252 253#ifdef __BIG_ENDIAN_BITFIELD 254 u32 gen:1; /* generation bit */ 255 u32 type:7; /* completion type */ 256 u32 fcs:1; /* Frame CRC correct */ 257 u32 frg:1; /* IP Fragment */ 258 u32 v4:1; /* IPv4 */ 259 u32 v6:1; /* IPv6 */ 260 u32 ipc:1; /* IP Checksum Correct */ 261 u32 tcp:1; /* TCP packet */ 262 u32 udp:1; /* UDP packet */ 263 u32 tuc:1; /* TCP/UDP Checksum Correct */ 264 u32 csum:16; 265#else 266 u32 csum:16; 267 u32 tuc:1; /* TCP/UDP Checksum Correct */ 268 u32 udp:1; /* UDP packet */ 269 u32 tcp:1; /* TCP packet */ 270 u32 ipc:1; /* IP Checksum Correct */ 271 u32 v6:1; /* IPv6 */ 272 u32 v4:1; /* IPv4 */ 273 u32 frg:1; /* IP Fragment */ 274 u32 fcs:1; /* Frame CRC correct */ 275 u32 type:7; /* completion type */ 276 u32 gen:1; /* generation bit */ 277#endif /* __BIG_ENDIAN_BITFIELD */ 278}; 279 280/* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */ 281#define VMXNET3_RCD_TUC_SHIFT 16 282#define VMXNET3_RCD_IPC_SHIFT 19 283 284/* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */ 285#define VMXNET3_RCD_TYPE_SHIFT 56 286#define VMXNET3_RCD_GEN_SHIFT 63 287 288/* csum OK for TCP/UDP pkts over IP */ 289#define VMXNET3_RCD_CSUM_OK (1 << VMXNET3_RCD_TUC_SHIFT | \ 290 1 << VMXNET3_RCD_IPC_SHIFT) 291#define VMXNET3_TXD_GEN_SIZE 1 292#define VMXNET3_TXD_EOP_SIZE 1 293 294/* value of RxCompDesc.rssType */ 295enum { 296 VMXNET3_RCD_RSS_TYPE_NONE = 0, 297 VMXNET3_RCD_RSS_TYPE_IPV4 = 1, 298 VMXNET3_RCD_RSS_TYPE_TCPIPV4 = 2, 299 VMXNET3_RCD_RSS_TYPE_IPV6 = 3, 300 VMXNET3_RCD_RSS_TYPE_TCPIPV6 = 4, 301}; 302 303 304/* a union for accessing all cmd/completion descriptors */ 305union Vmxnet3_GenericDesc { 306 __le64 qword[2]; 307 __le32 dword[4]; 308 __le16 word[8]; 309 struct Vmxnet3_TxDesc txd; 310 struct Vmxnet3_RxDesc rxd; 311 struct Vmxnet3_TxCompDesc tcd; 312 struct Vmxnet3_RxCompDesc rcd; 313}; 314 315#define VMXNET3_INIT_GEN 1 316 317/* Max size of a single tx buffer */ 318#define VMXNET3_MAX_TX_BUF_SIZE (1 << 14) 319 320/* # of tx desc needed for a tx buffer size */ 321#define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / \ 322 VMXNET3_MAX_TX_BUF_SIZE) 323 324/* max # of tx descs for a non-tso pkt */ 325#define VMXNET3_MAX_TXD_PER_PKT 16 326 327/* Max size of a single rx buffer */ 328#define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1) 329/* Minimum size of a type 0 buffer */ 330#define VMXNET3_MIN_T0_BUF_SIZE 128 331#define VMXNET3_MAX_CSUM_OFFSET 1024 332 333/* Ring base address alignment */ 334#define VMXNET3_RING_BA_ALIGN 512 335#define VMXNET3_RING_BA_MASK (VMXNET3_RING_BA_ALIGN - 1) 336 337/* Ring size must be a multiple of 32 */ 338#define VMXNET3_RING_SIZE_ALIGN 32 339#define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1) 340 341/* Max ring size */ 342#define VMXNET3_TX_RING_MAX_SIZE 4096 343#define VMXNET3_TC_RING_MAX_SIZE 4096 344#define VMXNET3_RX_RING_MAX_SIZE 4096 345#define VMXNET3_RX_RING2_MAX_SIZE 2048 346#define VMXNET3_RC_RING_MAX_SIZE 8192 347 348/* a list of reasons for queue stop */ 349 350enum { 351 VMXNET3_ERR_NOEOP = 0x80000000, /* cannot find the EOP desc of a pkt */ 352 VMXNET3_ERR_TXD_REUSE = 0x80000001, /* reuse TxDesc before tx completion */ 353 VMXNET3_ERR_BIG_PKT = 0x80000002, /* too many TxDesc for a pkt */ 354 VMXNET3_ERR_DESC_NOT_SPT = 0x80000003, /* descriptor type not supported */ 355 VMXNET3_ERR_SMALL_BUF = 0x80000004, /* type 0 buffer too small */ 356 VMXNET3_ERR_STRESS = 0x80000005, /* stress option firing in vmkernel */ 357 VMXNET3_ERR_SWITCH = 0x80000006, /* mode switch failure */ 358 VMXNET3_ERR_TXD_INVALID = 0x80000007, /* invalid TxDesc */ 359}; 360 361/* completion descriptor types */ 362#define VMXNET3_CDTYPE_TXCOMP 0 /* Tx Completion Descriptor */ 363#define VMXNET3_CDTYPE_RXCOMP 3 /* Rx Completion Descriptor */ 364 365enum { 366 VMXNET3_GOS_BITS_UNK = 0, /* unknown */ 367 VMXNET3_GOS_BITS_32 = 1, 368 VMXNET3_GOS_BITS_64 = 2, 369}; 370 371#define VMXNET3_GOS_TYPE_LINUX 1 372 373 374struct Vmxnet3_GOSInfo { 375#ifdef __BIG_ENDIAN_BITFIELD 376 u32 gosMisc:10; /* other info about gos */ 377 u32 gosVer:16; /* gos version */ 378 u32 gosType:4; /* which guest */ 379 u32 gosBits:2; /* 32-bit or 64-bit? */ 380#else 381 u32 gosBits:2; /* 32-bit or 64-bit? */ 382 u32 gosType:4; /* which guest */ 383 u32 gosVer:16; /* gos version */ 384 u32 gosMisc:10; /* other info about gos */ 385#endif /* __BIG_ENDIAN_BITFIELD */ 386}; 387 388struct Vmxnet3_DriverInfo { 389 __le32 version; 390 struct Vmxnet3_GOSInfo gos; 391 __le32 vmxnet3RevSpt; 392 __le32 uptVerSpt; 393}; 394 395 396#define VMXNET3_REV1_MAGIC 3133079265u 397 398/* 399 * QueueDescPA must be 128 bytes aligned. It points to an array of 400 * Vmxnet3_TxQueueDesc followed by an array of Vmxnet3_RxQueueDesc. 401 * The number of Vmxnet3_TxQueueDesc/Vmxnet3_RxQueueDesc are specified by 402 * Vmxnet3_MiscConf.numTxQueues/numRxQueues, respectively. 403 */ 404#define VMXNET3_QUEUE_DESC_ALIGN 128 405 406 407struct Vmxnet3_MiscConf { 408 struct Vmxnet3_DriverInfo driverInfo; 409 __le64 uptFeatures; 410 __le64 ddPA; /* driver data PA */ 411 __le64 queueDescPA; /* queue descriptor table PA */ 412 __le32 ddLen; /* driver data len */ 413 __le32 queueDescLen; /* queue desc. table len in bytes */ 414 __le32 mtu; 415 __le16 maxNumRxSG; 416 u8 numTxQueues; 417 u8 numRxQueues; 418 __le32 reserved[4]; 419}; 420 421 422struct Vmxnet3_TxQueueConf { 423 __le64 txRingBasePA; 424 __le64 dataRingBasePA; 425 __le64 compRingBasePA; 426 __le64 ddPA; /* driver data */ 427 __le64 reserved; 428 __le32 txRingSize; /* # of tx desc */ 429 __le32 dataRingSize; /* # of data desc */ 430 __le32 compRingSize; /* # of comp desc */ 431 __le32 ddLen; /* size of driver data */ 432 u8 intrIdx; 433 u8 _pad[7]; 434}; 435 436 437struct Vmxnet3_RxQueueConf { 438 __le64 rxRingBasePA[2]; 439 __le64 compRingBasePA; 440 __le64 ddPA; /* driver data */ 441 __le64 reserved; 442 __le32 rxRingSize[2]; /* # of rx desc */ 443 __le32 compRingSize; /* # of rx comp desc */ 444 __le32 ddLen; /* size of driver data */ 445 u8 intrIdx; 446 u8 _pad[7]; 447}; 448 449 450enum vmxnet3_intr_mask_mode { 451 VMXNET3_IMM_AUTO = 0, 452 VMXNET3_IMM_ACTIVE = 1, 453 VMXNET3_IMM_LAZY = 2 454}; 455 456enum vmxnet3_intr_type { 457 VMXNET3_IT_AUTO = 0, 458 VMXNET3_IT_INTX = 1, 459 VMXNET3_IT_MSI = 2, 460 VMXNET3_IT_MSIX = 3 461}; 462 463#define VMXNET3_MAX_TX_QUEUES 8 464#define VMXNET3_MAX_RX_QUEUES 16 465/* addition 1 for events */ 466#define VMXNET3_MAX_INTRS 25 467 468/* value of intrCtrl */ 469#define VMXNET3_IC_DISABLE_ALL 0x1 /* bit 0 */ 470 471 472struct Vmxnet3_IntrConf { 473 bool autoMask; 474 u8 numIntrs; /* # of interrupts */ 475 u8 eventIntrIdx; 476 u8 modLevels[VMXNET3_MAX_INTRS]; /* moderation level for 477 * each intr */ 478 __le32 intrCtrl; 479 __le32 reserved[2]; 480}; 481 482/* one bit per VLAN ID, the size is in the units of u32 */ 483#define VMXNET3_VFT_SIZE (4096 / (sizeof(u32) * 8)) 484 485 486struct Vmxnet3_QueueStatus { 487 bool stopped; 488 u8 _pad[3]; 489 __le32 error; 490}; 491 492 493struct Vmxnet3_TxQueueCtrl { 494 __le32 txNumDeferred; 495 __le32 txThreshold; 496 __le64 reserved; 497}; 498 499 500struct Vmxnet3_RxQueueCtrl { 501 bool updateRxProd; 502 u8 _pad[7]; 503 __le64 reserved; 504}; 505 506enum { 507 VMXNET3_RXM_UCAST = 0x01, /* unicast only */ 508 VMXNET3_RXM_MCAST = 0x02, /* multicast passing the filters */ 509 VMXNET3_RXM_BCAST = 0x04, /* broadcast only */ 510 VMXNET3_RXM_ALL_MULTI = 0x08, /* all multicast */ 511 VMXNET3_RXM_PROMISC = 0x10 /* promiscuous */ 512}; 513 514struct Vmxnet3_RxFilterConf { 515 __le32 rxMode; /* VMXNET3_RXM_xxx */ 516 __le16 mfTableLen; /* size of the multicast filter table */ 517 __le16 _pad1; 518 __le64 mfTablePA; /* PA of the multicast filters table */ 519 __le32 vfTable[VMXNET3_VFT_SIZE]; /* vlan filter */ 520}; 521 522 523#define VMXNET3_PM_MAX_FILTERS 6 524#define VMXNET3_PM_MAX_PATTERN_SIZE 128 525#define VMXNET3_PM_MAX_MASK_SIZE (VMXNET3_PM_MAX_PATTERN_SIZE / 8) 526 527#define VMXNET3_PM_WAKEUP_MAGIC cpu_to_le16(0x01) /* wake up on magic pkts */ 528#define VMXNET3_PM_WAKEUP_FILTER cpu_to_le16(0x02) /* wake up on pkts matching 529 * filters */ 530 531 532struct Vmxnet3_PM_PktFilter { 533 u8 maskSize; 534 u8 patternSize; 535 u8 mask[VMXNET3_PM_MAX_MASK_SIZE]; 536 u8 pattern[VMXNET3_PM_MAX_PATTERN_SIZE]; 537 u8 pad[6]; 538}; 539 540 541struct Vmxnet3_PMConf { 542 __le16 wakeUpEvents; /* VMXNET3_PM_WAKEUP_xxx */ 543 u8 numFilters; 544 u8 pad[5]; 545 struct Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS]; 546}; 547 548 549struct Vmxnet3_VariableLenConfDesc { 550 __le32 confVer; 551 __le32 confLen; 552 __le64 confPA; 553}; 554 555 556struct Vmxnet3_TxQueueDesc { 557 struct Vmxnet3_TxQueueCtrl ctrl; 558 struct Vmxnet3_TxQueueConf conf; 559 560 /* Driver read after a GET command */ 561 struct Vmxnet3_QueueStatus status; 562 struct UPT1_TxStats stats; 563 u8 _pad[88]; /* 128 aligned */ 564}; 565 566 567struct Vmxnet3_RxQueueDesc { 568 struct Vmxnet3_RxQueueCtrl ctrl; 569 struct Vmxnet3_RxQueueConf conf; 570 /* Driver read after a GET commad */ 571 struct Vmxnet3_QueueStatus status; 572 struct UPT1_RxStats stats; 573 u8 __pad[88]; /* 128 aligned */ 574}; 575 576 577struct Vmxnet3_DSDevRead { 578 /* read-only region for device, read by dev in response to a SET cmd */ 579 struct Vmxnet3_MiscConf misc; 580 struct Vmxnet3_IntrConf intrConf; 581 struct Vmxnet3_RxFilterConf rxFilterConf; 582 struct Vmxnet3_VariableLenConfDesc rssConfDesc; 583 struct Vmxnet3_VariableLenConfDesc pmConfDesc; 584 struct Vmxnet3_VariableLenConfDesc pluginConfDesc; 585}; 586 587/* All structures in DriverShared are padded to multiples of 8 bytes */ 588struct Vmxnet3_DriverShared { 589 __le32 magic; 590 /* make devRead start at 64bit boundaries */ 591 __le32 pad; 592 struct Vmxnet3_DSDevRead devRead; 593 __le32 ecr; 594 __le32 reserved[5]; 595}; 596 597 598#define VMXNET3_ECR_RQERR (1 << 0) 599#define VMXNET3_ECR_TQERR (1 << 1) 600#define VMXNET3_ECR_LINK (1 << 2) 601#define VMXNET3_ECR_DIC (1 << 3) 602#define VMXNET3_ECR_DEBUG (1 << 4) 603 604/* flip the gen bit of a ring */ 605#define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1) 606 607/* only use this if moving the idx won't affect the gen bit */ 608#define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) \ 609 do {\ 610 (idx)++;\ 611 if (unlikely((idx) == (ring_size))) {\ 612 (idx) = 0;\ 613 } \ 614 } while (0) 615 616#define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \ 617 (vfTable[vid >> 5] |= (1 << (vid & 31))) 618#define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \ 619 (vfTable[vid >> 5] &= ~(1 << (vid & 31))) 620 621#define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \ 622 ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0) 623 624#define VMXNET3_MAX_MTU 9000 625#define VMXNET3_MIN_MTU 60 626 627#define VMXNET3_LINK_UP (10000 << 16 | 1) /* 10 Gbps, up */ 628#define VMXNET3_LINK_DOWN 0 629 630#endif /* _VMXNET3_DEFS_H_ */ 631