1/* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include <linux/kernel.h> 18#include <linux/export.h> 19#include "hw.h" 20#include "hw-ops.h" 21 22struct ani_ofdm_level_entry { 23 int spur_immunity_level; 24 int fir_step_level; 25 int ofdm_weak_signal_on; 26}; 27 28/* values here are relative to the INI */ 29 30/* 31 * Legend: 32 * 33 * SI: Spur immunity 34 * FS: FIR Step 35 * WS: OFDM / CCK Weak Signal detection 36 * MRC-CCK: Maximal Ratio Combining for CCK 37 */ 38 39static const struct ani_ofdm_level_entry ofdm_level_table[] = { 40 /* SI FS WS */ 41 { 0, 0, 1 }, /* lvl 0 */ 42 { 1, 1, 1 }, /* lvl 1 */ 43 { 2, 2, 1 }, /* lvl 2 */ 44 { 3, 2, 1 }, /* lvl 3 (default) */ 45 { 4, 3, 1 }, /* lvl 4 */ 46 { 5, 4, 1 }, /* lvl 5 */ 47 { 6, 5, 1 }, /* lvl 6 */ 48 { 7, 6, 1 }, /* lvl 7 */ 49 { 7, 7, 1 }, /* lvl 8 */ 50 { 7, 8, 0 } /* lvl 9 */ 51}; 52#define ATH9K_ANI_OFDM_NUM_LEVEL \ 53 ARRAY_SIZE(ofdm_level_table) 54#define ATH9K_ANI_OFDM_MAX_LEVEL \ 55 (ATH9K_ANI_OFDM_NUM_LEVEL-1) 56#define ATH9K_ANI_OFDM_DEF_LEVEL \ 57 3 /* default level - matches the INI settings */ 58 59/* 60 * MRC (Maximal Ratio Combining) has always been used with multi-antenna ofdm. 61 * With OFDM for single stream you just add up all antenna inputs, you're 62 * only interested in what you get after FFT. Signal aligment is also not 63 * required for OFDM because any phase difference adds up in the frequency 64 * domain. 65 * 66 * MRC requires extra work for use with CCK. You need to align the antenna 67 * signals from the different antenna before you can add the signals together. 68 * You need aligment of signals as CCK is in time domain, so addition can cancel 69 * your signal completely if phase is 180 degrees (think of adding sine waves). 70 * You also need to remove noise before the addition and this is where ANI 71 * MRC CCK comes into play. One of the antenna inputs may be stronger but 72 * lower SNR, so just adding after alignment can be dangerous. 73 * 74 * Regardless of alignment in time, the antenna signals add constructively after 75 * FFT and improve your reception. For more information: 76 * 77 * http://en.wikipedia.org/wiki/Maximal-ratio_combining 78 */ 79 80struct ani_cck_level_entry { 81 int fir_step_level; 82 int mrc_cck_on; 83}; 84 85static const struct ani_cck_level_entry cck_level_table[] = { 86 /* FS MRC-CCK */ 87 { 0, 1 }, /* lvl 0 */ 88 { 1, 1 }, /* lvl 1 */ 89 { 2, 1 }, /* lvl 2 (default) */ 90 { 3, 1 }, /* lvl 3 */ 91 { 4, 0 }, /* lvl 4 */ 92 { 5, 0 }, /* lvl 5 */ 93 { 6, 0 }, /* lvl 6 */ 94 { 7, 0 }, /* lvl 7 (only for high rssi) */ 95 { 8, 0 } /* lvl 8 (only for high rssi) */ 96}; 97 98#define ATH9K_ANI_CCK_NUM_LEVEL \ 99 ARRAY_SIZE(cck_level_table) 100#define ATH9K_ANI_CCK_MAX_LEVEL \ 101 (ATH9K_ANI_CCK_NUM_LEVEL-1) 102#define ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI \ 103 (ATH9K_ANI_CCK_NUM_LEVEL-3) 104#define ATH9K_ANI_CCK_DEF_LEVEL \ 105 2 /* default level - matches the INI settings */ 106 107static void ath9k_hw_update_mibstats(struct ath_hw *ah, 108 struct ath9k_mib_stats *stats) 109{ 110 u32 addr[5] = {AR_RTS_OK, AR_RTS_FAIL, AR_ACK_FAIL, 111 AR_FCS_FAIL, AR_BEACON_CNT}; 112 u32 data[5]; 113 114 REG_READ_MULTI(ah, &addr[0], &data[0], 5); 115 /* AR_RTS_OK */ 116 stats->rts_good += data[0]; 117 /* AR_RTS_FAIL */ 118 stats->rts_bad += data[1]; 119 /* AR_ACK_FAIL */ 120 stats->ackrcv_bad += data[2]; 121 /* AR_FCS_FAIL */ 122 stats->fcs_bad += data[3]; 123 /* AR_BEACON_CNT */ 124 stats->beacons += data[4]; 125} 126 127static void ath9k_ani_restart(struct ath_hw *ah) 128{ 129 struct ar5416AniState *aniState; 130 131 if (!ah->curchan) 132 return; 133 134 aniState = &ah->ani; 135 aniState->listenTime = 0; 136 137 ENABLE_REGWRITE_BUFFER(ah); 138 139 REG_WRITE(ah, AR_PHY_ERR_1, 0); 140 REG_WRITE(ah, AR_PHY_ERR_2, 0); 141 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 142 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 143 144 REGWRITE_BUFFER_FLUSH(ah); 145 146 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); 147 148 aniState->ofdmPhyErrCount = 0; 149 aniState->cckPhyErrCount = 0; 150} 151 152/* Adjust the OFDM Noise Immunity Level */ 153static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel, 154 bool scan) 155{ 156 struct ar5416AniState *aniState = &ah->ani; 157 struct ath_common *common = ath9k_hw_common(ah); 158 const struct ani_ofdm_level_entry *entry_ofdm; 159 const struct ani_cck_level_entry *entry_cck; 160 bool weak_sig; 161 162 ath_dbg(common, ANI, "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n", 163 aniState->ofdmNoiseImmunityLevel, 164 immunityLevel, BEACON_RSSI(ah), 165 ATH9K_ANI_RSSI_THR_LOW, 166 ATH9K_ANI_RSSI_THR_HIGH); 167 168 if (AR_SREV_9100(ah) && immunityLevel < ATH9K_ANI_OFDM_DEF_LEVEL) 169 immunityLevel = ATH9K_ANI_OFDM_DEF_LEVEL; 170 171 if (!scan) 172 aniState->ofdmNoiseImmunityLevel = immunityLevel; 173 174 entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel]; 175 entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel]; 176 177 if (aniState->spurImmunityLevel != entry_ofdm->spur_immunity_level) 178 ath9k_hw_ani_control(ah, 179 ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 180 entry_ofdm->spur_immunity_level); 181 182 if (aniState->firstepLevel != entry_ofdm->fir_step_level && 183 entry_ofdm->fir_step_level >= entry_cck->fir_step_level) 184 ath9k_hw_ani_control(ah, 185 ATH9K_ANI_FIRSTEP_LEVEL, 186 entry_ofdm->fir_step_level); 187 188 weak_sig = entry_ofdm->ofdm_weak_signal_on; 189 if (ah->opmode == NL80211_IFTYPE_STATION && 190 BEACON_RSSI(ah) <= ATH9K_ANI_RSSI_THR_HIGH) 191 weak_sig = true; 192 /* 193 * Newer chipsets are better at dealing with high PHY error counts - 194 * keep weak signal detection enabled when no RSSI threshold is 195 * available to determine if it is needed (mode != STA) 196 */ 197 else if (AR_SREV_9300_20_OR_LATER(ah) && 198 ah->opmode != NL80211_IFTYPE_STATION) 199 weak_sig = true; 200 201 /* Older chipsets are more sensitive to high PHY error counts */ 202 else if (!AR_SREV_9300_20_OR_LATER(ah) && 203 aniState->ofdmNoiseImmunityLevel >= 8) 204 weak_sig = false; 205 206 if (aniState->ofdmWeakSigDetect != weak_sig) 207 ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, 208 weak_sig); 209 210 if (!AR_SREV_9300_20_OR_LATER(ah)) 211 return; 212 213 if (aniState->ofdmNoiseImmunityLevel >= ATH9K_ANI_OFDM_DEF_LEVEL) { 214 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH; 215 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_ABOVE_INI; 216 } else { 217 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_BELOW_INI; 218 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW; 219 } 220} 221 222static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah) 223{ 224 struct ar5416AniState *aniState; 225 226 if (!ah->curchan) 227 return; 228 229 aniState = &ah->ani; 230 231 if (aniState->ofdmNoiseImmunityLevel < ATH9K_ANI_OFDM_MAX_LEVEL) 232 ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel + 1, false); 233} 234 235/* 236 * Set the ANI settings to match an CCK level. 237 */ 238static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel, 239 bool scan) 240{ 241 struct ar5416AniState *aniState = &ah->ani; 242 struct ath_common *common = ath9k_hw_common(ah); 243 const struct ani_ofdm_level_entry *entry_ofdm; 244 const struct ani_cck_level_entry *entry_cck; 245 246 ath_dbg(common, ANI, "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n", 247 aniState->cckNoiseImmunityLevel, immunityLevel, 248 BEACON_RSSI(ah), ATH9K_ANI_RSSI_THR_LOW, 249 ATH9K_ANI_RSSI_THR_HIGH); 250 251 if (AR_SREV_9100(ah) && immunityLevel < ATH9K_ANI_CCK_DEF_LEVEL) 252 immunityLevel = ATH9K_ANI_CCK_DEF_LEVEL; 253 254 if (ah->opmode == NL80211_IFTYPE_STATION && 255 BEACON_RSSI(ah) <= ATH9K_ANI_RSSI_THR_LOW && 256 immunityLevel > ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI) 257 immunityLevel = ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI; 258 259 if (!scan) 260 aniState->cckNoiseImmunityLevel = immunityLevel; 261 262 entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel]; 263 entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel]; 264 265 if (aniState->firstepLevel != entry_cck->fir_step_level && 266 entry_cck->fir_step_level >= entry_ofdm->fir_step_level) 267 ath9k_hw_ani_control(ah, 268 ATH9K_ANI_FIRSTEP_LEVEL, 269 entry_cck->fir_step_level); 270 271 /* Skip MRC CCK for pre AR9003 families */ 272 if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9485(ah) || 273 AR_SREV_9565(ah) || AR_SREV_9561(ah)) 274 return; 275 276 if (aniState->mrcCCK != entry_cck->mrc_cck_on) 277 ath9k_hw_ani_control(ah, 278 ATH9K_ANI_MRC_CCK, 279 entry_cck->mrc_cck_on); 280} 281 282static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah) 283{ 284 struct ar5416AniState *aniState; 285 286 if (!ah->curchan) 287 return; 288 289 aniState = &ah->ani; 290 291 if (aniState->cckNoiseImmunityLevel < ATH9K_ANI_CCK_MAX_LEVEL) 292 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel + 1, 293 false); 294} 295 296/* 297 * only lower either OFDM or CCK errors per turn 298 * we lower the other one next time 299 */ 300static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah) 301{ 302 struct ar5416AniState *aniState; 303 304 aniState = &ah->ani; 305 306 /* lower OFDM noise immunity */ 307 if (aniState->ofdmNoiseImmunityLevel > 0 && 308 (aniState->ofdmsTurn || aniState->cckNoiseImmunityLevel == 0)) { 309 ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel - 1, 310 false); 311 return; 312 } 313 314 /* lower CCK noise immunity */ 315 if (aniState->cckNoiseImmunityLevel > 0) 316 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel - 1, 317 false); 318} 319 320/* 321 * Restore the ANI parameters in the HAL and reset the statistics. 322 * This routine should be called for every hardware reset and for 323 * every channel change. 324 */ 325void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning) 326{ 327 struct ar5416AniState *aniState = &ah->ani; 328 struct ath9k_channel *chan = ah->curchan; 329 struct ath_common *common = ath9k_hw_common(ah); 330 int ofdm_nil, cck_nil; 331 332 if (!ah->curchan) 333 return; 334 335 BUG_ON(aniState == NULL); 336 ah->stats.ast_ani_reset++; 337 338 ofdm_nil = max_t(int, ATH9K_ANI_OFDM_DEF_LEVEL, 339 aniState->ofdmNoiseImmunityLevel); 340 cck_nil = max_t(int, ATH9K_ANI_CCK_DEF_LEVEL, 341 aniState->cckNoiseImmunityLevel); 342 343 if (is_scanning || 344 (ah->opmode != NL80211_IFTYPE_STATION && 345 ah->opmode != NL80211_IFTYPE_ADHOC)) { 346 /* 347 * If we're scanning or in AP mode, the defaults (ini) 348 * should be in place. For an AP we assume the historical 349 * levels for this channel are probably outdated so start 350 * from defaults instead. 351 */ 352 if (aniState->ofdmNoiseImmunityLevel != 353 ATH9K_ANI_OFDM_DEF_LEVEL || 354 aniState->cckNoiseImmunityLevel != 355 ATH9K_ANI_CCK_DEF_LEVEL) { 356 ath_dbg(common, ANI, 357 "Restore defaults: opmode %u chan %d Mhz is_scanning=%d ofdm:%d cck:%d\n", 358 ah->opmode, 359 chan->channel, 360 is_scanning, 361 aniState->ofdmNoiseImmunityLevel, 362 aniState->cckNoiseImmunityLevel); 363 364 ofdm_nil = ATH9K_ANI_OFDM_DEF_LEVEL; 365 cck_nil = ATH9K_ANI_CCK_DEF_LEVEL; 366 } 367 } else { 368 /* 369 * restore historical levels for this channel 370 */ 371 ath_dbg(common, ANI, 372 "Restore history: opmode %u chan %d Mhz is_scanning=%d ofdm:%d cck:%d\n", 373 ah->opmode, 374 chan->channel, 375 is_scanning, 376 aniState->ofdmNoiseImmunityLevel, 377 aniState->cckNoiseImmunityLevel); 378 } 379 ath9k_hw_set_ofdm_nil(ah, ofdm_nil, is_scanning); 380 ath9k_hw_set_cck_nil(ah, cck_nil, is_scanning); 381 382 ath9k_ani_restart(ah); 383} 384 385static bool ath9k_hw_ani_read_counters(struct ath_hw *ah) 386{ 387 struct ath_common *common = ath9k_hw_common(ah); 388 struct ar5416AniState *aniState = &ah->ani; 389 u32 phyCnt1, phyCnt2; 390 int32_t listenTime; 391 392 ath_hw_cycle_counters_update(common); 393 listenTime = ath_hw_get_listen_time(common); 394 395 if (listenTime <= 0) { 396 ah->stats.ast_ani_lneg_or_lzero++; 397 ath9k_ani_restart(ah); 398 return false; 399 } 400 401 aniState->listenTime += listenTime; 402 403 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); 404 405 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1); 406 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); 407 408 ah->stats.ast_ani_ofdmerrs += phyCnt1 - aniState->ofdmPhyErrCount; 409 aniState->ofdmPhyErrCount = phyCnt1; 410 411 ah->stats.ast_ani_cckerrs += phyCnt2 - aniState->cckPhyErrCount; 412 aniState->cckPhyErrCount = phyCnt2; 413 414 return true; 415} 416 417void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan) 418{ 419 struct ar5416AniState *aniState; 420 struct ath_common *common = ath9k_hw_common(ah); 421 u32 ofdmPhyErrRate, cckPhyErrRate; 422 423 if (!ah->curchan) 424 return; 425 426 aniState = &ah->ani; 427 if (!ath9k_hw_ani_read_counters(ah)) 428 return; 429 430 ofdmPhyErrRate = aniState->ofdmPhyErrCount * 1000 / 431 aniState->listenTime; 432 cckPhyErrRate = aniState->cckPhyErrCount * 1000 / 433 aniState->listenTime; 434 435 ath_dbg(common, ANI, 436 "listenTime=%d OFDM:%d errs=%d/s CCK:%d errs=%d/s ofdm_turn=%d\n", 437 aniState->listenTime, 438 aniState->ofdmNoiseImmunityLevel, 439 ofdmPhyErrRate, aniState->cckNoiseImmunityLevel, 440 cckPhyErrRate, aniState->ofdmsTurn); 441 442 if (aniState->listenTime > ah->aniperiod) { 443 if (cckPhyErrRate < ah->config.cck_trig_low && 444 ofdmPhyErrRate < ah->config.ofdm_trig_low) { 445 ath9k_hw_ani_lower_immunity(ah); 446 aniState->ofdmsTurn = !aniState->ofdmsTurn; 447 } else if (ofdmPhyErrRate > ah->config.ofdm_trig_high) { 448 ath9k_hw_ani_ofdm_err_trigger(ah); 449 aniState->ofdmsTurn = false; 450 } else if (cckPhyErrRate > ah->config.cck_trig_high) { 451 ath9k_hw_ani_cck_err_trigger(ah); 452 aniState->ofdmsTurn = true; 453 } 454 ath9k_ani_restart(ah); 455 } 456} 457EXPORT_SYMBOL(ath9k_hw_ani_monitor); 458 459void ath9k_enable_mib_counters(struct ath_hw *ah) 460{ 461 struct ath_common *common = ath9k_hw_common(ah); 462 463 ath_dbg(common, ANI, "Enable MIB counters\n"); 464 465 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); 466 467 ENABLE_REGWRITE_BUFFER(ah); 468 469 REG_WRITE(ah, AR_FILT_OFDM, 0); 470 REG_WRITE(ah, AR_FILT_CCK, 0); 471 REG_WRITE(ah, AR_MIBC, 472 ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS) 473 & 0x0f); 474 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 475 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 476 477 REGWRITE_BUFFER_FLUSH(ah); 478} 479 480/* Freeze the MIB counters, get the stats and then clear them */ 481void ath9k_hw_disable_mib_counters(struct ath_hw *ah) 482{ 483 struct ath_common *common = ath9k_hw_common(ah); 484 485 ath_dbg(common, ANI, "Disable MIB counters\n"); 486 487 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); 488 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); 489 REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC); 490 REG_WRITE(ah, AR_FILT_OFDM, 0); 491 REG_WRITE(ah, AR_FILT_CCK, 0); 492} 493EXPORT_SYMBOL(ath9k_hw_disable_mib_counters); 494 495void ath9k_hw_ani_init(struct ath_hw *ah) 496{ 497 struct ath_common *common = ath9k_hw_common(ah); 498 struct ar5416AniState *ani = &ah->ani; 499 500 ath_dbg(common, ANI, "Initialize ANI\n"); 501 502 if (AR_SREV_9300_20_OR_LATER(ah)) { 503 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH; 504 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW; 505 ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH; 506 ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW; 507 } else { 508 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_OLD; 509 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_OLD; 510 ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH_OLD; 511 ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW_OLD; 512 } 513 514 ani->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; 515 ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL; 516 ani->mrcCCK = AR_SREV_9300_20_OR_LATER(ah) ? true : false; 517 ani->ofdmsTurn = true; 518 ani->ofdmWeakSigDetect = true; 519 ani->cckNoiseImmunityLevel = ATH9K_ANI_CCK_DEF_LEVEL; 520 ani->ofdmNoiseImmunityLevel = ATH9K_ANI_OFDM_DEF_LEVEL; 521 522 /* 523 * since we expect some ongoing maintenance on the tables, let's sanity 524 * check here default level should not modify INI setting. 525 */ 526 ah->aniperiod = ATH9K_ANI_PERIOD; 527 ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL; 528 529 ath9k_ani_restart(ah); 530 ath9k_enable_mib_counters(ah); 531} 532