1/* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include <linux/dma-mapping.h> 18#include "ath9k.h" 19#include "ar9003_mac.h" 20 21#define BITS_PER_BYTE 8 22#define OFDM_PLCP_BITS 22 23#define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) 24#define L_STF 8 25#define L_LTF 8 26#define L_SIG 4 27#define HT_SIG 8 28#define HT_STF 4 29#define HT_LTF(_ns) (4 * (_ns)) 30#define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */ 31#define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */ 32#define TIME_SYMBOLS(t) ((t) >> 2) 33#define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18) 34#define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2) 35#define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18) 36 37 38static u16 bits_per_symbol[][2] = { 39 /* 20MHz 40MHz */ 40 { 26, 54 }, /* 0: BPSK */ 41 { 52, 108 }, /* 1: QPSK 1/2 */ 42 { 78, 162 }, /* 2: QPSK 3/4 */ 43 { 104, 216 }, /* 3: 16-QAM 1/2 */ 44 { 156, 324 }, /* 4: 16-QAM 3/4 */ 45 { 208, 432 }, /* 5: 64-QAM 2/3 */ 46 { 234, 486 }, /* 6: 64-QAM 3/4 */ 47 { 260, 540 }, /* 7: 64-QAM 5/6 */ 48}; 49 50static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, 51 struct ath_atx_tid *tid, struct sk_buff *skb); 52static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, 53 int tx_flags, struct ath_txq *txq); 54static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, 55 struct ath_txq *txq, struct list_head *bf_q, 56 struct ath_tx_status *ts, int txok); 57static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, 58 struct list_head *head, bool internal); 59static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, 60 struct ath_tx_status *ts, int nframes, int nbad, 61 int txok); 62static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 63 int seqno); 64static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, 65 struct ath_txq *txq, 66 struct ath_atx_tid *tid, 67 struct sk_buff *skb); 68 69enum { 70 MCS_HT20, 71 MCS_HT20_SGI, 72 MCS_HT40, 73 MCS_HT40_SGI, 74}; 75 76/*********************/ 77/* Aggregation logic */ 78/*********************/ 79 80void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq) 81 __acquires(&txq->axq_lock) 82{ 83 spin_lock_bh(&txq->axq_lock); 84} 85 86void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq) 87 __releases(&txq->axq_lock) 88{ 89 spin_unlock_bh(&txq->axq_lock); 90} 91 92void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq) 93 __releases(&txq->axq_lock) 94{ 95 struct sk_buff_head q; 96 struct sk_buff *skb; 97 98 __skb_queue_head_init(&q); 99 skb_queue_splice_init(&txq->complete_q, &q); 100 spin_unlock_bh(&txq->axq_lock); 101 102 while ((skb = __skb_dequeue(&q))) 103 ieee80211_tx_status(sc->hw, skb); 104} 105 106static void ath_tx_queue_tid(struct ath_softc *sc, struct ath_txq *txq, 107 struct ath_atx_tid *tid) 108{ 109 struct ath_atx_ac *ac = tid->ac; 110 struct list_head *list; 111 struct ath_vif *avp = (struct ath_vif *) tid->an->vif->drv_priv; 112 struct ath_chanctx *ctx = avp->chanctx; 113 114 if (!ctx) 115 return; 116 117 if (tid->sched) 118 return; 119 120 tid->sched = true; 121 list_add_tail(&tid->list, &ac->tid_q); 122 123 if (ac->sched) 124 return; 125 126 ac->sched = true; 127 128 list = &ctx->acq[TID_TO_WME_AC(tid->tidno)]; 129 list_add_tail(&ac->list, list); 130} 131 132static struct ath_frame_info *get_frame_info(struct sk_buff *skb) 133{ 134 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 135 BUILD_BUG_ON(sizeof(struct ath_frame_info) > 136 sizeof(tx_info->rate_driver_data)); 137 return (struct ath_frame_info *) &tx_info->rate_driver_data[0]; 138} 139 140static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno) 141{ 142 if (!tid->an->sta) 143 return; 144 145 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno, 146 seqno << IEEE80211_SEQ_SEQ_SHIFT); 147} 148 149static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta, 150 struct ath_buf *bf) 151{ 152 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates, 153 ARRAY_SIZE(bf->rates)); 154} 155 156static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq, 157 struct sk_buff *skb) 158{ 159 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 160 struct ath_frame_info *fi = get_frame_info(skb); 161 int q = fi->txq; 162 163 if (q < 0) 164 return; 165 166 txq = sc->tx.txq_map[q]; 167 if (WARN_ON(--txq->pending_frames < 0)) 168 txq->pending_frames = 0; 169 170 if (txq->stopped && 171 txq->pending_frames < sc->tx.txq_max_pending[q]) { 172 if (ath9k_is_chanctx_enabled()) 173 ieee80211_wake_queue(sc->hw, info->hw_queue); 174 else 175 ieee80211_wake_queue(sc->hw, q); 176 txq->stopped = false; 177 } 178} 179 180static struct ath_atx_tid * 181ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb) 182{ 183 u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 184 return ATH_AN_2_TID(an, tidno); 185} 186 187static bool ath_tid_has_buffered(struct ath_atx_tid *tid) 188{ 189 return !skb_queue_empty(&tid->buf_q) || !skb_queue_empty(&tid->retry_q); 190} 191 192static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid) 193{ 194 struct sk_buff *skb; 195 196 skb = __skb_dequeue(&tid->retry_q); 197 if (!skb) 198 skb = __skb_dequeue(&tid->buf_q); 199 200 return skb; 201} 202 203/* 204 * ath_tx_tid_change_state: 205 * - clears a-mpdu flag of previous session 206 * - force sequence number allocation to fix next BlockAck Window 207 */ 208static void 209ath_tx_tid_change_state(struct ath_softc *sc, struct ath_atx_tid *tid) 210{ 211 struct ath_txq *txq = tid->ac->txq; 212 struct ieee80211_tx_info *tx_info; 213 struct sk_buff *skb, *tskb; 214 struct ath_buf *bf; 215 struct ath_frame_info *fi; 216 217 skb_queue_walk_safe(&tid->buf_q, skb, tskb) { 218 fi = get_frame_info(skb); 219 bf = fi->bf; 220 221 tx_info = IEEE80211_SKB_CB(skb); 222 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU; 223 224 if (bf) 225 continue; 226 227 bf = ath_tx_setup_buffer(sc, txq, tid, skb); 228 if (!bf) { 229 __skb_unlink(skb, &tid->buf_q); 230 ath_txq_skb_done(sc, txq, skb); 231 ieee80211_free_txskb(sc->hw, skb); 232 continue; 233 } 234 } 235 236} 237 238static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid) 239{ 240 struct ath_txq *txq = tid->ac->txq; 241 struct sk_buff *skb; 242 struct ath_buf *bf; 243 struct list_head bf_head; 244 struct ath_tx_status ts; 245 struct ath_frame_info *fi; 246 bool sendbar = false; 247 248 INIT_LIST_HEAD(&bf_head); 249 250 memset(&ts, 0, sizeof(ts)); 251 252 while ((skb = __skb_dequeue(&tid->retry_q))) { 253 fi = get_frame_info(skb); 254 bf = fi->bf; 255 if (!bf) { 256 ath_txq_skb_done(sc, txq, skb); 257 ieee80211_free_txskb(sc->hw, skb); 258 continue; 259 } 260 261 if (fi->baw_tracked) { 262 ath_tx_update_baw(sc, tid, bf->bf_state.seqno); 263 sendbar = true; 264 } 265 266 list_add_tail(&bf->list, &bf_head); 267 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0); 268 } 269 270 if (sendbar) { 271 ath_txq_unlock(sc, txq); 272 ath_send_bar(tid, tid->seq_start); 273 ath_txq_lock(sc, txq); 274 } 275} 276 277static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 278 int seqno) 279{ 280 int index, cindex; 281 282 index = ATH_BA_INDEX(tid->seq_start, seqno); 283 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 284 285 __clear_bit(cindex, tid->tx_buf); 286 287 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) { 288 INCR(tid->seq_start, IEEE80211_SEQ_MAX); 289 INCR(tid->baw_head, ATH_TID_MAX_BUFS); 290 if (tid->bar_index >= 0) 291 tid->bar_index--; 292 } 293} 294 295static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 296 struct ath_buf *bf) 297{ 298 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); 299 u16 seqno = bf->bf_state.seqno; 300 int index, cindex; 301 302 index = ATH_BA_INDEX(tid->seq_start, seqno); 303 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 304 __set_bit(cindex, tid->tx_buf); 305 fi->baw_tracked = 1; 306 307 if (index >= ((tid->baw_tail - tid->baw_head) & 308 (ATH_TID_MAX_BUFS - 1))) { 309 tid->baw_tail = cindex; 310 INCR(tid->baw_tail, ATH_TID_MAX_BUFS); 311 } 312} 313 314static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq, 315 struct ath_atx_tid *tid) 316 317{ 318 struct sk_buff *skb; 319 struct ath_buf *bf; 320 struct list_head bf_head; 321 struct ath_tx_status ts; 322 struct ath_frame_info *fi; 323 324 memset(&ts, 0, sizeof(ts)); 325 INIT_LIST_HEAD(&bf_head); 326 327 while ((skb = ath_tid_dequeue(tid))) { 328 fi = get_frame_info(skb); 329 bf = fi->bf; 330 331 if (!bf) { 332 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq); 333 continue; 334 } 335 336 list_add_tail(&bf->list, &bf_head); 337 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0); 338 } 339} 340 341static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq, 342 struct sk_buff *skb, int count) 343{ 344 struct ath_frame_info *fi = get_frame_info(skb); 345 struct ath_buf *bf = fi->bf; 346 struct ieee80211_hdr *hdr; 347 int prev = fi->retries; 348 349 TX_STAT_INC(txq->axq_qnum, a_retries); 350 fi->retries += count; 351 352 if (prev > 0) 353 return; 354 355 hdr = (struct ieee80211_hdr *)skb->data; 356 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); 357 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, 358 sizeof(*hdr), DMA_TO_DEVICE); 359} 360 361static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc) 362{ 363 struct ath_buf *bf = NULL; 364 365 spin_lock_bh(&sc->tx.txbuflock); 366 367 if (unlikely(list_empty(&sc->tx.txbuf))) { 368 spin_unlock_bh(&sc->tx.txbuflock); 369 return NULL; 370 } 371 372 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); 373 list_del(&bf->list); 374 375 spin_unlock_bh(&sc->tx.txbuflock); 376 377 return bf; 378} 379 380static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf) 381{ 382 spin_lock_bh(&sc->tx.txbuflock); 383 list_add_tail(&bf->list, &sc->tx.txbuf); 384 spin_unlock_bh(&sc->tx.txbuflock); 385} 386 387static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf) 388{ 389 struct ath_buf *tbf; 390 391 tbf = ath_tx_get_buffer(sc); 392 if (WARN_ON(!tbf)) 393 return NULL; 394 395 ATH_TXBUF_RESET(tbf); 396 397 tbf->bf_mpdu = bf->bf_mpdu; 398 tbf->bf_buf_addr = bf->bf_buf_addr; 399 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len); 400 tbf->bf_state = bf->bf_state; 401 tbf->bf_state.stale = false; 402 403 return tbf; 404} 405 406static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf, 407 struct ath_tx_status *ts, int txok, 408 int *nframes, int *nbad) 409{ 410 struct ath_frame_info *fi; 411 u16 seq_st = 0; 412 u32 ba[WME_BA_BMP_SIZE >> 5]; 413 int ba_index; 414 int isaggr = 0; 415 416 *nbad = 0; 417 *nframes = 0; 418 419 isaggr = bf_isaggr(bf); 420 if (isaggr) { 421 seq_st = ts->ts_seqnum; 422 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3); 423 } 424 425 while (bf) { 426 fi = get_frame_info(bf->bf_mpdu); 427 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno); 428 429 (*nframes)++; 430 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index))) 431 (*nbad)++; 432 433 bf = bf->bf_next; 434 } 435} 436 437 438static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, 439 struct ath_buf *bf, struct list_head *bf_q, 440 struct ath_tx_status *ts, int txok) 441{ 442 struct ath_node *an = NULL; 443 struct sk_buff *skb; 444 struct ieee80211_sta *sta; 445 struct ieee80211_hw *hw = sc->hw; 446 struct ieee80211_hdr *hdr; 447 struct ieee80211_tx_info *tx_info; 448 struct ath_atx_tid *tid = NULL; 449 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf; 450 struct list_head bf_head; 451 struct sk_buff_head bf_pending; 452 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first; 453 u32 ba[WME_BA_BMP_SIZE >> 5]; 454 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0; 455 bool rc_update = true, isba; 456 struct ieee80211_tx_rate rates[4]; 457 struct ath_frame_info *fi; 458 int nframes; 459 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH); 460 int i, retries; 461 int bar_index = -1; 462 463 skb = bf->bf_mpdu; 464 hdr = (struct ieee80211_hdr *)skb->data; 465 466 tx_info = IEEE80211_SKB_CB(skb); 467 468 memcpy(rates, bf->rates, sizeof(rates)); 469 470 retries = ts->ts_longretry + 1; 471 for (i = 0; i < ts->ts_rateindex; i++) 472 retries += rates[i].count; 473 474 rcu_read_lock(); 475 476 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2); 477 if (!sta) { 478 rcu_read_unlock(); 479 480 INIT_LIST_HEAD(&bf_head); 481 while (bf) { 482 bf_next = bf->bf_next; 483 484 if (!bf->bf_state.stale || bf_next != NULL) 485 list_move_tail(&bf->list, &bf_head); 486 487 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0); 488 489 bf = bf_next; 490 } 491 return; 492 } 493 494 an = (struct ath_node *)sta->drv_priv; 495 tid = ath_get_skb_tid(sc, an, skb); 496 seq_first = tid->seq_start; 497 isba = ts->ts_flags & ATH9K_TX_BA; 498 499 /* 500 * The hardware occasionally sends a tx status for the wrong TID. 501 * In this case, the BA status cannot be considered valid and all 502 * subframes need to be retransmitted 503 * 504 * Only BlockAcks have a TID and therefore normal Acks cannot be 505 * checked 506 */ 507 if (isba && tid->tidno != ts->tid) 508 txok = false; 509 510 isaggr = bf_isaggr(bf); 511 memset(ba, 0, WME_BA_BMP_SIZE >> 3); 512 513 if (isaggr && txok) { 514 if (ts->ts_flags & ATH9K_TX_BA) { 515 seq_st = ts->ts_seqnum; 516 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3); 517 } else { 518 /* 519 * AR5416 can become deaf/mute when BA 520 * issue happens. Chip needs to be reset. 521 * But AP code may have sychronization issues 522 * when perform internal reset in this routine. 523 * Only enable reset in STA mode for now. 524 */ 525 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) 526 needreset = 1; 527 } 528 } 529 530 __skb_queue_head_init(&bf_pending); 531 532 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad); 533 while (bf) { 534 u16 seqno = bf->bf_state.seqno; 535 536 txfail = txpending = sendbar = 0; 537 bf_next = bf->bf_next; 538 539 skb = bf->bf_mpdu; 540 tx_info = IEEE80211_SKB_CB(skb); 541 fi = get_frame_info(skb); 542 543 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) || 544 !tid->active) { 545 /* 546 * Outside of the current BlockAck window, 547 * maybe part of a previous session 548 */ 549 txfail = 1; 550 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) { 551 /* transmit completion, subframe is 552 * acked by block ack */ 553 acked_cnt++; 554 } else if (!isaggr && txok) { 555 /* transmit completion */ 556 acked_cnt++; 557 } else if (flush) { 558 txpending = 1; 559 } else if (fi->retries < ATH_MAX_SW_RETRIES) { 560 if (txok || !an->sleeping) 561 ath_tx_set_retry(sc, txq, bf->bf_mpdu, 562 retries); 563 564 txpending = 1; 565 } else { 566 txfail = 1; 567 txfail_cnt++; 568 bar_index = max_t(int, bar_index, 569 ATH_BA_INDEX(seq_first, seqno)); 570 } 571 572 /* 573 * Make sure the last desc is reclaimed if it 574 * not a holding desc. 575 */ 576 INIT_LIST_HEAD(&bf_head); 577 if (bf_next != NULL || !bf_last->bf_state.stale) 578 list_move_tail(&bf->list, &bf_head); 579 580 if (!txpending) { 581 /* 582 * complete the acked-ones/xretried ones; update 583 * block-ack window 584 */ 585 ath_tx_update_baw(sc, tid, seqno); 586 587 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) { 588 memcpy(tx_info->control.rates, rates, sizeof(rates)); 589 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok); 590 rc_update = false; 591 if (bf == bf->bf_lastbf) 592 ath_dynack_sample_tx_ts(sc->sc_ah, 593 bf->bf_mpdu, 594 ts); 595 } 596 597 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 598 !txfail); 599 } else { 600 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) { 601 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP; 602 ieee80211_sta_eosp(sta); 603 } 604 /* retry the un-acked ones */ 605 if (bf->bf_next == NULL && bf_last->bf_state.stale) { 606 struct ath_buf *tbf; 607 608 tbf = ath_clone_txbuf(sc, bf_last); 609 /* 610 * Update tx baw and complete the 611 * frame with failed status if we 612 * run out of tx buf. 613 */ 614 if (!tbf) { 615 ath_tx_update_baw(sc, tid, seqno); 616 617 ath_tx_complete_buf(sc, bf, txq, 618 &bf_head, ts, 0); 619 bar_index = max_t(int, bar_index, 620 ATH_BA_INDEX(seq_first, seqno)); 621 break; 622 } 623 624 fi->bf = tbf; 625 } 626 627 /* 628 * Put this buffer to the temporary pending 629 * queue to retain ordering 630 */ 631 __skb_queue_tail(&bf_pending, skb); 632 } 633 634 bf = bf_next; 635 } 636 637 /* prepend un-acked frames to the beginning of the pending frame queue */ 638 if (!skb_queue_empty(&bf_pending)) { 639 if (an->sleeping) 640 ieee80211_sta_set_buffered(sta, tid->tidno, true); 641 642 skb_queue_splice_tail(&bf_pending, &tid->retry_q); 643 if (!an->sleeping) { 644 ath_tx_queue_tid(sc, txq, tid); 645 646 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY)) 647 tid->ac->clear_ps_filter = true; 648 } 649 } 650 651 if (bar_index >= 0) { 652 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index); 653 654 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq)) 655 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq); 656 657 ath_txq_unlock(sc, txq); 658 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1)); 659 ath_txq_lock(sc, txq); 660 } 661 662 rcu_read_unlock(); 663 664 if (needreset) 665 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR); 666} 667 668static bool bf_is_ampdu_not_probing(struct ath_buf *bf) 669{ 670 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu); 671 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE); 672} 673 674static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq, 675 struct ath_tx_status *ts, struct ath_buf *bf, 676 struct list_head *bf_head) 677{ 678 struct ieee80211_tx_info *info; 679 bool txok, flush; 680 681 txok = !(ts->ts_status & ATH9K_TXERR_MASK); 682 flush = !!(ts->ts_status & ATH9K_TX_FLUSH); 683 txq->axq_tx_inprogress = false; 684 685 txq->axq_depth--; 686 if (bf_is_ampdu_not_probing(bf)) 687 txq->axq_ampdu_depth--; 688 689 ts->duration = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc, 690 ts->ts_rateindex); 691 if (!bf_isampdu(bf)) { 692 if (!flush) { 693 info = IEEE80211_SKB_CB(bf->bf_mpdu); 694 memcpy(info->control.rates, bf->rates, 695 sizeof(info->control.rates)); 696 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok); 697 ath_dynack_sample_tx_ts(sc->sc_ah, bf->bf_mpdu, ts); 698 } 699 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok); 700 } else 701 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok); 702 703 if (!flush) 704 ath_txq_schedule(sc, txq); 705} 706 707static bool ath_lookup_legacy(struct ath_buf *bf) 708{ 709 struct sk_buff *skb; 710 struct ieee80211_tx_info *tx_info; 711 struct ieee80211_tx_rate *rates; 712 int i; 713 714 skb = bf->bf_mpdu; 715 tx_info = IEEE80211_SKB_CB(skb); 716 rates = tx_info->control.rates; 717 718 for (i = 0; i < 4; i++) { 719 if (!rates[i].count || rates[i].idx < 0) 720 break; 721 722 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) 723 return true; 724 } 725 726 return false; 727} 728 729static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf, 730 struct ath_atx_tid *tid) 731{ 732 struct sk_buff *skb; 733 struct ieee80211_tx_info *tx_info; 734 struct ieee80211_tx_rate *rates; 735 u32 max_4ms_framelen, frmlen; 736 u16 aggr_limit, bt_aggr_limit, legacy = 0; 737 int q = tid->ac->txq->mac80211_qnum; 738 int i; 739 740 skb = bf->bf_mpdu; 741 tx_info = IEEE80211_SKB_CB(skb); 742 rates = bf->rates; 743 744 /* 745 * Find the lowest frame length among the rate series that will have a 746 * 4ms (or TXOP limited) transmit duration. 747 */ 748 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX; 749 750 for (i = 0; i < 4; i++) { 751 int modeidx; 752 753 if (!rates[i].count) 754 continue; 755 756 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) { 757 legacy = 1; 758 break; 759 } 760 761 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 762 modeidx = MCS_HT40; 763 else 764 modeidx = MCS_HT20; 765 766 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) 767 modeidx++; 768 769 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx]; 770 max_4ms_framelen = min(max_4ms_framelen, frmlen); 771 } 772 773 /* 774 * limit aggregate size by the minimum rate if rate selected is 775 * not a probe rate, if rate selected is a probe rate then 776 * avoid aggregation of this packet. 777 */ 778 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy) 779 return 0; 780 781 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX); 782 783 /* 784 * Override the default aggregation limit for BTCOEX. 785 */ 786 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen); 787 if (bt_aggr_limit) 788 aggr_limit = bt_aggr_limit; 789 790 if (tid->an->maxampdu) 791 aggr_limit = min(aggr_limit, tid->an->maxampdu); 792 793 return aggr_limit; 794} 795 796/* 797 * Returns the number of delimiters to be added to 798 * meet the minimum required mpdudensity. 799 */ 800static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid, 801 struct ath_buf *bf, u16 frmlen, 802 bool first_subfrm) 803{ 804#define FIRST_DESC_NDELIMS 60 805 u32 nsymbits, nsymbols; 806 u16 minlen; 807 u8 flags, rix; 808 int width, streams, half_gi, ndelim, mindelim; 809 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); 810 811 /* Select standard number of delimiters based on frame length alone */ 812 ndelim = ATH_AGGR_GET_NDELIM(frmlen); 813 814 /* 815 * If encryption enabled, hardware requires some more padding between 816 * subframes. 817 * TODO - this could be improved to be dependent on the rate. 818 * The hardware can keep up at lower rates, but not higher rates 819 */ 820 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) && 821 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) 822 ndelim += ATH_AGGR_ENCRYPTDELIM; 823 824 /* 825 * Add delimiter when using RTS/CTS with aggregation 826 * and non enterprise AR9003 card 827 */ 828 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) && 829 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE)) 830 ndelim = max(ndelim, FIRST_DESC_NDELIMS); 831 832 /* 833 * Convert desired mpdu density from microeconds to bytes based 834 * on highest rate in rate series (i.e. first rate) to determine 835 * required minimum length for subframe. Take into account 836 * whether high rate is 20 or 40Mhz and half or full GI. 837 * 838 * If there is no mpdu density restriction, no further calculation 839 * is needed. 840 */ 841 842 if (tid->an->mpdudensity == 0) 843 return ndelim; 844 845 rix = bf->rates[0].idx; 846 flags = bf->rates[0].flags; 847 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0; 848 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0; 849 850 if (half_gi) 851 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity); 852 else 853 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity); 854 855 if (nsymbols == 0) 856 nsymbols = 1; 857 858 streams = HT_RC_2_STREAMS(rix); 859 nsymbits = bits_per_symbol[rix % 8][width] * streams; 860 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; 861 862 if (frmlen < minlen) { 863 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ; 864 ndelim = max(mindelim, ndelim); 865 } 866 867 return ndelim; 868} 869 870static struct ath_buf * 871ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq, 872 struct ath_atx_tid *tid, struct sk_buff_head **q) 873{ 874 struct ieee80211_tx_info *tx_info; 875 struct ath_frame_info *fi; 876 struct sk_buff *skb; 877 struct ath_buf *bf; 878 u16 seqno; 879 880 while (1) { 881 *q = &tid->retry_q; 882 if (skb_queue_empty(*q)) 883 *q = &tid->buf_q; 884 885 skb = skb_peek(*q); 886 if (!skb) 887 break; 888 889 fi = get_frame_info(skb); 890 bf = fi->bf; 891 if (!fi->bf) 892 bf = ath_tx_setup_buffer(sc, txq, tid, skb); 893 else 894 bf->bf_state.stale = false; 895 896 if (!bf) { 897 __skb_unlink(skb, *q); 898 ath_txq_skb_done(sc, txq, skb); 899 ieee80211_free_txskb(sc->hw, skb); 900 continue; 901 } 902 903 bf->bf_next = NULL; 904 bf->bf_lastbf = bf; 905 906 tx_info = IEEE80211_SKB_CB(skb); 907 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT; 908 909 /* 910 * No aggregation session is running, but there may be frames 911 * from a previous session or a failed attempt in the queue. 912 * Send them out as normal data frames 913 */ 914 if (!tid->active) 915 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU; 916 917 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) { 918 bf->bf_state.bf_type = 0; 919 return bf; 920 } 921 922 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR; 923 seqno = bf->bf_state.seqno; 924 925 /* do not step over block-ack window */ 926 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) 927 break; 928 929 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) { 930 struct ath_tx_status ts = {}; 931 struct list_head bf_head; 932 933 INIT_LIST_HEAD(&bf_head); 934 list_add(&bf->list, &bf_head); 935 __skb_unlink(skb, *q); 936 ath_tx_update_baw(sc, tid, seqno); 937 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0); 938 continue; 939 } 940 941 return bf; 942 } 943 944 return NULL; 945} 946 947static bool 948ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq, 949 struct ath_atx_tid *tid, struct list_head *bf_q, 950 struct ath_buf *bf_first, struct sk_buff_head *tid_q, 951 int *aggr_len) 952{ 953#define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) 954 struct ath_buf *bf = bf_first, *bf_prev = NULL; 955 int nframes = 0, ndelim; 956 u16 aggr_limit = 0, al = 0, bpad = 0, 957 al_delta, h_baw = tid->baw_size / 2; 958 struct ieee80211_tx_info *tx_info; 959 struct ath_frame_info *fi; 960 struct sk_buff *skb; 961 bool closed = false; 962 963 bf = bf_first; 964 aggr_limit = ath_lookup_rate(sc, bf, tid); 965 966 do { 967 skb = bf->bf_mpdu; 968 fi = get_frame_info(skb); 969 970 /* do not exceed aggregation limit */ 971 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen; 972 if (nframes) { 973 if (aggr_limit < al + bpad + al_delta || 974 ath_lookup_legacy(bf) || nframes >= h_baw) 975 break; 976 977 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 978 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) || 979 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) 980 break; 981 } 982 983 /* add padding for previous frame to aggregation length */ 984 al += bpad + al_delta; 985 986 /* 987 * Get the delimiters needed to meet the MPDU 988 * density for this node. 989 */ 990 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen, 991 !nframes); 992 bpad = PADBYTES(al_delta) + (ndelim << 2); 993 994 nframes++; 995 bf->bf_next = NULL; 996 997 /* link buffers of this frame to the aggregate */ 998 if (!fi->baw_tracked) 999 ath_tx_addto_baw(sc, tid, bf); 1000 bf->bf_state.ndelim = ndelim; 1001 1002 __skb_unlink(skb, tid_q); 1003 list_add_tail(&bf->list, bf_q); 1004 if (bf_prev) 1005 bf_prev->bf_next = bf; 1006 1007 bf_prev = bf; 1008 1009 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q); 1010 if (!bf) { 1011 closed = true; 1012 break; 1013 } 1014 } while (ath_tid_has_buffered(tid)); 1015 1016 bf = bf_first; 1017 bf->bf_lastbf = bf_prev; 1018 1019 if (bf == bf_prev) { 1020 al = get_frame_info(bf->bf_mpdu)->framelen; 1021 bf->bf_state.bf_type = BUF_AMPDU; 1022 } else { 1023 TX_STAT_INC(txq->axq_qnum, a_aggr); 1024 } 1025 1026 *aggr_len = al; 1027 1028 return closed; 1029#undef PADBYTES 1030} 1031 1032/* 1033 * rix - rate index 1034 * pktlen - total bytes (delims + data + fcs + pads + pad delims) 1035 * width - 0 for 20 MHz, 1 for 40 MHz 1036 * half_gi - to use 4us v/s 3.6 us for symbol time 1037 */ 1038static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen, 1039 int width, int half_gi, bool shortPreamble) 1040{ 1041 u32 nbits, nsymbits, duration, nsymbols; 1042 int streams; 1043 1044 /* find number of symbols: PLCP + data */ 1045 streams = HT_RC_2_STREAMS(rix); 1046 nbits = (pktlen << 3) + OFDM_PLCP_BITS; 1047 nsymbits = bits_per_symbol[rix % 8][width] * streams; 1048 nsymbols = (nbits + nsymbits - 1) / nsymbits; 1049 1050 if (!half_gi) 1051 duration = SYMBOL_TIME(nsymbols); 1052 else 1053 duration = SYMBOL_TIME_HALFGI(nsymbols); 1054 1055 /* addup duration for legacy/ht training and signal fields */ 1056 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); 1057 1058 return duration; 1059} 1060 1061static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi) 1062{ 1063 int streams = HT_RC_2_STREAMS(mcs); 1064 int symbols, bits; 1065 int bytes = 0; 1066 1067 usec -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); 1068 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec); 1069 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams; 1070 bits -= OFDM_PLCP_BITS; 1071 bytes = bits / 8; 1072 if (bytes > 65532) 1073 bytes = 65532; 1074 1075 return bytes; 1076} 1077 1078void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop) 1079{ 1080 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi; 1081 int mcs; 1082 1083 /* 4ms is the default (and maximum) duration */ 1084 if (!txop || txop > 4096) 1085 txop = 4096; 1086 1087 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20]; 1088 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI]; 1089 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40]; 1090 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI]; 1091 for (mcs = 0; mcs < 32; mcs++) { 1092 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false); 1093 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true); 1094 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false); 1095 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true); 1096 } 1097} 1098 1099static u8 ath_get_rate_txpower(struct ath_softc *sc, struct ath_buf *bf, 1100 u8 rateidx, bool is_40, bool is_cck) 1101{ 1102 u8 max_power; 1103 struct sk_buff *skb; 1104 struct ath_frame_info *fi; 1105 struct ieee80211_tx_info *info; 1106 struct ath_hw *ah = sc->sc_ah; 1107 1108 if (sc->tx99_state || !ah->tpc_enabled) 1109 return MAX_RATE_POWER; 1110 1111 skb = bf->bf_mpdu; 1112 fi = get_frame_info(skb); 1113 info = IEEE80211_SKB_CB(skb); 1114 1115 if (!AR_SREV_9300_20_OR_LATER(ah)) { 1116 int txpower = fi->tx_power; 1117 1118 if (is_40) { 1119 u8 power_ht40delta; 1120 struct ar5416_eeprom_def *eep = &ah->eeprom.def; 1121 1122 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) { 1123 bool is_2ghz; 1124 struct modal_eep_header *pmodal; 1125 1126 is_2ghz = info->band == IEEE80211_BAND_2GHZ; 1127 pmodal = &eep->modalHeader[is_2ghz]; 1128 power_ht40delta = pmodal->ht40PowerIncForPdadc; 1129 } else { 1130 power_ht40delta = 2; 1131 } 1132 txpower += power_ht40delta; 1133 } 1134 1135 if (AR_SREV_9287(ah) || AR_SREV_9285(ah) || 1136 AR_SREV_9271(ah)) { 1137 txpower -= 2 * AR9287_PWR_TABLE_OFFSET_DB; 1138 } else if (AR_SREV_9280_20_OR_LATER(ah)) { 1139 s8 power_offset; 1140 1141 power_offset = ah->eep_ops->get_eeprom(ah, 1142 EEP_PWR_TABLE_OFFSET); 1143 txpower -= 2 * power_offset; 1144 } 1145 1146 if (OLC_FOR_AR9280_20_LATER && is_cck) 1147 txpower -= 2; 1148 1149 txpower = max(txpower, 0); 1150 max_power = min_t(u8, ah->tx_power[rateidx], txpower); 1151 1152 /* XXX: clamp minimum TX power at 1 for AR9160 since if 1153 * max_power is set to 0, frames are transmitted at max 1154 * TX power 1155 */ 1156 if (!max_power && !AR_SREV_9280_20_OR_LATER(ah)) 1157 max_power = 1; 1158 } else if (!bf->bf_state.bfs_paprd) { 1159 if (rateidx < 8 && (info->flags & IEEE80211_TX_CTL_STBC)) 1160 max_power = min_t(u8, ah->tx_power_stbc[rateidx], 1161 fi->tx_power); 1162 else 1163 max_power = min_t(u8, ah->tx_power[rateidx], 1164 fi->tx_power); 1165 } else { 1166 max_power = ah->paprd_training_power; 1167 } 1168 1169 return max_power; 1170} 1171 1172static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, 1173 struct ath_tx_info *info, int len, bool rts) 1174{ 1175 struct ath_hw *ah = sc->sc_ah; 1176 struct ath_common *common = ath9k_hw_common(ah); 1177 struct sk_buff *skb; 1178 struct ieee80211_tx_info *tx_info; 1179 struct ieee80211_tx_rate *rates; 1180 const struct ieee80211_rate *rate; 1181 struct ieee80211_hdr *hdr; 1182 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); 1183 u32 rts_thresh = sc->hw->wiphy->rts_threshold; 1184 int i; 1185 u8 rix = 0; 1186 1187 skb = bf->bf_mpdu; 1188 tx_info = IEEE80211_SKB_CB(skb); 1189 rates = bf->rates; 1190 hdr = (struct ieee80211_hdr *)skb->data; 1191 1192 /* set dur_update_en for l-sig computation except for PS-Poll frames */ 1193 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control); 1194 info->rtscts_rate = fi->rtscts_rate; 1195 1196 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) { 1197 bool is_40, is_sgi, is_sp, is_cck; 1198 int phy; 1199 1200 if (!rates[i].count || (rates[i].idx < 0)) 1201 continue; 1202 1203 rix = rates[i].idx; 1204 info->rates[i].Tries = rates[i].count; 1205 1206 /* 1207 * Handle RTS threshold for unaggregated HT frames. 1208 */ 1209 if (bf_isampdu(bf) && !bf_isaggr(bf) && 1210 (rates[i].flags & IEEE80211_TX_RC_MCS) && 1211 unlikely(rts_thresh != (u32) -1)) { 1212 if (!rts_thresh || (len > rts_thresh)) 1213 rts = true; 1214 } 1215 1216 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) { 1217 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; 1218 info->flags |= ATH9K_TXDESC_RTSENA; 1219 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 1220 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; 1221 info->flags |= ATH9K_TXDESC_CTSENA; 1222 } 1223 1224 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 1225 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040; 1226 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) 1227 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI; 1228 1229 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI); 1230 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH); 1231 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE); 1232 1233 if (rates[i].flags & IEEE80211_TX_RC_MCS) { 1234 /* MCS rates */ 1235 info->rates[i].Rate = rix | 0x80; 1236 info->rates[i].ChSel = ath_txchainmask_reduction(sc, 1237 ah->txchainmask, info->rates[i].Rate); 1238 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len, 1239 is_40, is_sgi, is_sp); 1240 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC)) 1241 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC; 1242 1243 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, 1244 is_40, false); 1245 continue; 1246 } 1247 1248 /* legacy rates */ 1249 rate = &common->sbands[tx_info->band].bitrates[rates[i].idx]; 1250 if ((tx_info->band == IEEE80211_BAND_2GHZ) && 1251 !(rate->flags & IEEE80211_RATE_ERP_G)) 1252 phy = WLAN_RC_PHY_CCK; 1253 else 1254 phy = WLAN_RC_PHY_OFDM; 1255 1256 info->rates[i].Rate = rate->hw_value; 1257 if (rate->hw_value_short) { 1258 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 1259 info->rates[i].Rate |= rate->hw_value_short; 1260 } else { 1261 is_sp = false; 1262 } 1263 1264 if (bf->bf_state.bfs_paprd) 1265 info->rates[i].ChSel = ah->txchainmask; 1266 else 1267 info->rates[i].ChSel = ath_txchainmask_reduction(sc, 1268 ah->txchainmask, info->rates[i].Rate); 1269 1270 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah, 1271 phy, rate->bitrate * 100, len, rix, is_sp); 1272 1273 is_cck = IS_CCK_RATE(info->rates[i].Rate); 1274 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, false, 1275 is_cck); 1276 } 1277 1278 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ 1279 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit)) 1280 info->flags &= ~ATH9K_TXDESC_RTSENA; 1281 1282 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */ 1283 if (info->flags & ATH9K_TXDESC_RTSENA) 1284 info->flags &= ~ATH9K_TXDESC_CTSENA; 1285} 1286 1287static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb) 1288{ 1289 struct ieee80211_hdr *hdr; 1290 enum ath9k_pkt_type htype; 1291 __le16 fc; 1292 1293 hdr = (struct ieee80211_hdr *)skb->data; 1294 fc = hdr->frame_control; 1295 1296 if (ieee80211_is_beacon(fc)) 1297 htype = ATH9K_PKT_TYPE_BEACON; 1298 else if (ieee80211_is_probe_resp(fc)) 1299 htype = ATH9K_PKT_TYPE_PROBE_RESP; 1300 else if (ieee80211_is_atim(fc)) 1301 htype = ATH9K_PKT_TYPE_ATIM; 1302 else if (ieee80211_is_pspoll(fc)) 1303 htype = ATH9K_PKT_TYPE_PSPOLL; 1304 else 1305 htype = ATH9K_PKT_TYPE_NORMAL; 1306 1307 return htype; 1308} 1309 1310static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf, 1311 struct ath_txq *txq, int len) 1312{ 1313 struct ath_hw *ah = sc->sc_ah; 1314 struct ath_buf *bf_first = NULL; 1315 struct ath_tx_info info; 1316 u32 rts_thresh = sc->hw->wiphy->rts_threshold; 1317 bool rts = false; 1318 1319 memset(&info, 0, sizeof(info)); 1320 info.is_first = true; 1321 info.is_last = true; 1322 info.qcu = txq->axq_qnum; 1323 1324 while (bf) { 1325 struct sk_buff *skb = bf->bf_mpdu; 1326 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1327 struct ath_frame_info *fi = get_frame_info(skb); 1328 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR); 1329 1330 info.type = get_hw_packet_type(skb); 1331 if (bf->bf_next) 1332 info.link = bf->bf_next->bf_daddr; 1333 else 1334 info.link = (sc->tx99_state) ? bf->bf_daddr : 0; 1335 1336 if (!bf_first) { 1337 bf_first = bf; 1338 1339 if (!sc->tx99_state) 1340 info.flags = ATH9K_TXDESC_INTREQ; 1341 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) || 1342 txq == sc->tx.uapsdq) 1343 info.flags |= ATH9K_TXDESC_CLRDMASK; 1344 1345 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) 1346 info.flags |= ATH9K_TXDESC_NOACK; 1347 if (tx_info->flags & IEEE80211_TX_CTL_LDPC) 1348 info.flags |= ATH9K_TXDESC_LDPC; 1349 1350 if (bf->bf_state.bfs_paprd) 1351 info.flags |= (u32) bf->bf_state.bfs_paprd << 1352 ATH9K_TXDESC_PAPRD_S; 1353 1354 /* 1355 * mac80211 doesn't handle RTS threshold for HT because 1356 * the decision has to be taken based on AMPDU length 1357 * and aggregation is done entirely inside ath9k. 1358 * Set the RTS/CTS flag for the first subframe based 1359 * on the threshold. 1360 */ 1361 if (aggr && (bf == bf_first) && 1362 unlikely(rts_thresh != (u32) -1)) { 1363 /* 1364 * "len" is the size of the entire AMPDU. 1365 */ 1366 if (!rts_thresh || (len > rts_thresh)) 1367 rts = true; 1368 } 1369 1370 if (!aggr) 1371 len = fi->framelen; 1372 1373 ath_buf_set_rate(sc, bf, &info, len, rts); 1374 } 1375 1376 info.buf_addr[0] = bf->bf_buf_addr; 1377 info.buf_len[0] = skb->len; 1378 info.pkt_len = fi->framelen; 1379 info.keyix = fi->keyix; 1380 info.keytype = fi->keytype; 1381 1382 if (aggr) { 1383 if (bf == bf_first) 1384 info.aggr = AGGR_BUF_FIRST; 1385 else if (bf == bf_first->bf_lastbf) 1386 info.aggr = AGGR_BUF_LAST; 1387 else 1388 info.aggr = AGGR_BUF_MIDDLE; 1389 1390 info.ndelim = bf->bf_state.ndelim; 1391 info.aggr_len = len; 1392 } 1393 1394 if (bf == bf_first->bf_lastbf) 1395 bf_first = NULL; 1396 1397 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info); 1398 bf = bf->bf_next; 1399 } 1400} 1401 1402static void 1403ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq, 1404 struct ath_atx_tid *tid, struct list_head *bf_q, 1405 struct ath_buf *bf_first, struct sk_buff_head *tid_q) 1406{ 1407 struct ath_buf *bf = bf_first, *bf_prev = NULL; 1408 struct sk_buff *skb; 1409 int nframes = 0; 1410 1411 do { 1412 struct ieee80211_tx_info *tx_info; 1413 skb = bf->bf_mpdu; 1414 1415 nframes++; 1416 __skb_unlink(skb, tid_q); 1417 list_add_tail(&bf->list, bf_q); 1418 if (bf_prev) 1419 bf_prev->bf_next = bf; 1420 bf_prev = bf; 1421 1422 if (nframes >= 2) 1423 break; 1424 1425 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q); 1426 if (!bf) 1427 break; 1428 1429 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 1430 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) 1431 break; 1432 1433 ath_set_rates(tid->an->vif, tid->an->sta, bf); 1434 } while (1); 1435} 1436 1437static bool ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq, 1438 struct ath_atx_tid *tid, bool *stop) 1439{ 1440 struct ath_buf *bf; 1441 struct ieee80211_tx_info *tx_info; 1442 struct sk_buff_head *tid_q; 1443 struct list_head bf_q; 1444 int aggr_len = 0; 1445 bool aggr, last = true; 1446 1447 if (!ath_tid_has_buffered(tid)) 1448 return false; 1449 1450 INIT_LIST_HEAD(&bf_q); 1451 1452 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q); 1453 if (!bf) 1454 return false; 1455 1456 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 1457 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU); 1458 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) || 1459 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) { 1460 *stop = true; 1461 return false; 1462 } 1463 1464 ath_set_rates(tid->an->vif, tid->an->sta, bf); 1465 if (aggr) 1466 last = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf, 1467 tid_q, &aggr_len); 1468 else 1469 ath_tx_form_burst(sc, txq, tid, &bf_q, bf, tid_q); 1470 1471 if (list_empty(&bf_q)) 1472 return false; 1473 1474 if (tid->ac->clear_ps_filter || tid->an->no_ps_filter) { 1475 tid->ac->clear_ps_filter = false; 1476 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT; 1477 } 1478 1479 ath_tx_fill_desc(sc, bf, txq, aggr_len); 1480 ath_tx_txqaddbuf(sc, txq, &bf_q, false); 1481 return true; 1482} 1483 1484int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, 1485 u16 tid, u16 *ssn) 1486{ 1487 struct ath_atx_tid *txtid; 1488 struct ath_txq *txq; 1489 struct ath_node *an; 1490 u8 density; 1491 1492 an = (struct ath_node *)sta->drv_priv; 1493 txtid = ATH_AN_2_TID(an, tid); 1494 txq = txtid->ac->txq; 1495 1496 ath_txq_lock(sc, txq); 1497 1498 /* update ampdu factor/density, they may have changed. This may happen 1499 * in HT IBSS when a beacon with HT-info is received after the station 1500 * has already been added. 1501 */ 1502 if (sta->ht_cap.ht_supported) { 1503 an->maxampdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + 1504 sta->ht_cap.ampdu_factor)) - 1; 1505 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density); 1506 an->mpdudensity = density; 1507 } 1508 1509 /* force sequence number allocation for pending frames */ 1510 ath_tx_tid_change_state(sc, txtid); 1511 1512 txtid->active = true; 1513 *ssn = txtid->seq_start = txtid->seq_next; 1514 txtid->bar_index = -1; 1515 1516 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf)); 1517 txtid->baw_head = txtid->baw_tail = 0; 1518 1519 ath_txq_unlock_complete(sc, txq); 1520 1521 return 0; 1522} 1523 1524void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) 1525{ 1526 struct ath_node *an = (struct ath_node *)sta->drv_priv; 1527 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid); 1528 struct ath_txq *txq = txtid->ac->txq; 1529 1530 ath_txq_lock(sc, txq); 1531 txtid->active = false; 1532 ath_tx_flush_tid(sc, txtid); 1533 ath_tx_tid_change_state(sc, txtid); 1534 ath_txq_unlock_complete(sc, txq); 1535} 1536 1537void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc, 1538 struct ath_node *an) 1539{ 1540 struct ath_atx_tid *tid; 1541 struct ath_atx_ac *ac; 1542 struct ath_txq *txq; 1543 bool buffered; 1544 int tidno; 1545 1546 for (tidno = 0, tid = &an->tid[tidno]; 1547 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) { 1548 1549 ac = tid->ac; 1550 txq = ac->txq; 1551 1552 ath_txq_lock(sc, txq); 1553 1554 if (!tid->sched) { 1555 ath_txq_unlock(sc, txq); 1556 continue; 1557 } 1558 1559 buffered = ath_tid_has_buffered(tid); 1560 1561 tid->sched = false; 1562 list_del(&tid->list); 1563 1564 if (ac->sched) { 1565 ac->sched = false; 1566 list_del(&ac->list); 1567 } 1568 1569 ath_txq_unlock(sc, txq); 1570 1571 ieee80211_sta_set_buffered(sta, tidno, buffered); 1572 } 1573} 1574 1575void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an) 1576{ 1577 struct ath_atx_tid *tid; 1578 struct ath_atx_ac *ac; 1579 struct ath_txq *txq; 1580 int tidno; 1581 1582 for (tidno = 0, tid = &an->tid[tidno]; 1583 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) { 1584 1585 ac = tid->ac; 1586 txq = ac->txq; 1587 1588 ath_txq_lock(sc, txq); 1589 ac->clear_ps_filter = true; 1590 1591 if (ath_tid_has_buffered(tid)) { 1592 ath_tx_queue_tid(sc, txq, tid); 1593 ath_txq_schedule(sc, txq); 1594 } 1595 1596 ath_txq_unlock_complete(sc, txq); 1597 } 1598} 1599 1600void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, 1601 u16 tidno) 1602{ 1603 struct ath_atx_tid *tid; 1604 struct ath_node *an; 1605 struct ath_txq *txq; 1606 1607 an = (struct ath_node *)sta->drv_priv; 1608 tid = ATH_AN_2_TID(an, tidno); 1609 txq = tid->ac->txq; 1610 1611 ath_txq_lock(sc, txq); 1612 1613 tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor; 1614 1615 if (ath_tid_has_buffered(tid)) { 1616 ath_tx_queue_tid(sc, txq, tid); 1617 ath_txq_schedule(sc, txq); 1618 } 1619 1620 ath_txq_unlock_complete(sc, txq); 1621} 1622 1623void ath9k_release_buffered_frames(struct ieee80211_hw *hw, 1624 struct ieee80211_sta *sta, 1625 u16 tids, int nframes, 1626 enum ieee80211_frame_release_type reason, 1627 bool more_data) 1628{ 1629 struct ath_softc *sc = hw->priv; 1630 struct ath_node *an = (struct ath_node *)sta->drv_priv; 1631 struct ath_txq *txq = sc->tx.uapsdq; 1632 struct ieee80211_tx_info *info; 1633 struct list_head bf_q; 1634 struct ath_buf *bf_tail = NULL, *bf; 1635 struct sk_buff_head *tid_q; 1636 int sent = 0; 1637 int i; 1638 1639 INIT_LIST_HEAD(&bf_q); 1640 for (i = 0; tids && nframes; i++, tids >>= 1) { 1641 struct ath_atx_tid *tid; 1642 1643 if (!(tids & 1)) 1644 continue; 1645 1646 tid = ATH_AN_2_TID(an, i); 1647 1648 ath_txq_lock(sc, tid->ac->txq); 1649 while (nframes > 0) { 1650 bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid, &tid_q); 1651 if (!bf) 1652 break; 1653 1654 __skb_unlink(bf->bf_mpdu, tid_q); 1655 list_add_tail(&bf->list, &bf_q); 1656 ath_set_rates(tid->an->vif, tid->an->sta, bf); 1657 if (bf_isampdu(bf)) { 1658 ath_tx_addto_baw(sc, tid, bf); 1659 bf->bf_state.bf_type &= ~BUF_AGGR; 1660 } 1661 if (bf_tail) 1662 bf_tail->bf_next = bf; 1663 1664 bf_tail = bf; 1665 nframes--; 1666 sent++; 1667 TX_STAT_INC(txq->axq_qnum, a_queued_hw); 1668 1669 if (an->sta && !ath_tid_has_buffered(tid)) 1670 ieee80211_sta_set_buffered(an->sta, i, false); 1671 } 1672 ath_txq_unlock_complete(sc, tid->ac->txq); 1673 } 1674 1675 if (list_empty(&bf_q)) 1676 return; 1677 1678 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu); 1679 info->flags |= IEEE80211_TX_STATUS_EOSP; 1680 1681 bf = list_first_entry(&bf_q, struct ath_buf, list); 1682 ath_txq_lock(sc, txq); 1683 ath_tx_fill_desc(sc, bf, txq, 0); 1684 ath_tx_txqaddbuf(sc, txq, &bf_q, false); 1685 ath_txq_unlock(sc, txq); 1686} 1687 1688/********************/ 1689/* Queue Management */ 1690/********************/ 1691 1692struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 1693{ 1694 struct ath_hw *ah = sc->sc_ah; 1695 struct ath9k_tx_queue_info qi; 1696 static const int subtype_txq_to_hwq[] = { 1697 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE, 1698 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK, 1699 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI, 1700 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO, 1701 }; 1702 int axq_qnum, i; 1703 1704 memset(&qi, 0, sizeof(qi)); 1705 qi.tqi_subtype = subtype_txq_to_hwq[subtype]; 1706 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT; 1707 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT; 1708 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT; 1709 qi.tqi_physCompBuf = 0; 1710 1711 /* 1712 * Enable interrupts only for EOL and DESC conditions. 1713 * We mark tx descriptors to receive a DESC interrupt 1714 * when a tx queue gets deep; otherwise waiting for the 1715 * EOL to reap descriptors. Note that this is done to 1716 * reduce interrupt load and this only defers reaping 1717 * descriptors, never transmitting frames. Aside from 1718 * reducing interrupts this also permits more concurrency. 1719 * The only potential downside is if the tx queue backs 1720 * up in which case the top half of the kernel may backup 1721 * due to a lack of tx descriptors. 1722 * 1723 * The UAPSD queue is an exception, since we take a desc- 1724 * based intr on the EOSP frames. 1725 */ 1726 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 1727 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE; 1728 } else { 1729 if (qtype == ATH9K_TX_QUEUE_UAPSD) 1730 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; 1731 else 1732 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | 1733 TXQ_FLAG_TXDESCINT_ENABLE; 1734 } 1735 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi); 1736 if (axq_qnum == -1) { 1737 /* 1738 * NB: don't print a message, this happens 1739 * normally on parts with too few tx queues 1740 */ 1741 return NULL; 1742 } 1743 if (!ATH_TXQ_SETUP(sc, axq_qnum)) { 1744 struct ath_txq *txq = &sc->tx.txq[axq_qnum]; 1745 1746 txq->axq_qnum = axq_qnum; 1747 txq->mac80211_qnum = -1; 1748 txq->axq_link = NULL; 1749 __skb_queue_head_init(&txq->complete_q); 1750 INIT_LIST_HEAD(&txq->axq_q); 1751 spin_lock_init(&txq->axq_lock); 1752 txq->axq_depth = 0; 1753 txq->axq_ampdu_depth = 0; 1754 txq->axq_tx_inprogress = false; 1755 sc->tx.txqsetup |= 1<<axq_qnum; 1756 1757 txq->txq_headidx = txq->txq_tailidx = 0; 1758 for (i = 0; i < ATH_TXFIFO_DEPTH; i++) 1759 INIT_LIST_HEAD(&txq->txq_fifo[i]); 1760 } 1761 return &sc->tx.txq[axq_qnum]; 1762} 1763 1764int ath_txq_update(struct ath_softc *sc, int qnum, 1765 struct ath9k_tx_queue_info *qinfo) 1766{ 1767 struct ath_hw *ah = sc->sc_ah; 1768 int error = 0; 1769 struct ath9k_tx_queue_info qi; 1770 1771 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum); 1772 1773 ath9k_hw_get_txq_props(ah, qnum, &qi); 1774 qi.tqi_aifs = qinfo->tqi_aifs; 1775 qi.tqi_cwmin = qinfo->tqi_cwmin; 1776 qi.tqi_cwmax = qinfo->tqi_cwmax; 1777 qi.tqi_burstTime = qinfo->tqi_burstTime; 1778 qi.tqi_readyTime = qinfo->tqi_readyTime; 1779 1780 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { 1781 ath_err(ath9k_hw_common(sc->sc_ah), 1782 "Unable to update hardware queue %u!\n", qnum); 1783 error = -EIO; 1784 } else { 1785 ath9k_hw_resettxqueue(ah, qnum); 1786 } 1787 1788 return error; 1789} 1790 1791int ath_cabq_update(struct ath_softc *sc) 1792{ 1793 struct ath9k_tx_queue_info qi; 1794 struct ath_beacon_config *cur_conf = &sc->cur_chan->beacon; 1795 int qnum = sc->beacon.cabq->axq_qnum; 1796 1797 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi); 1798 1799 qi.tqi_readyTime = (TU_TO_USEC(cur_conf->beacon_interval) * 1800 ATH_CABQ_READY_TIME) / 100; 1801 ath_txq_update(sc, qnum, &qi); 1802 1803 return 0; 1804} 1805 1806static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq, 1807 struct list_head *list) 1808{ 1809 struct ath_buf *bf, *lastbf; 1810 struct list_head bf_head; 1811 struct ath_tx_status ts; 1812 1813 memset(&ts, 0, sizeof(ts)); 1814 ts.ts_status = ATH9K_TX_FLUSH; 1815 INIT_LIST_HEAD(&bf_head); 1816 1817 while (!list_empty(list)) { 1818 bf = list_first_entry(list, struct ath_buf, list); 1819 1820 if (bf->bf_state.stale) { 1821 list_del(&bf->list); 1822 1823 ath_tx_return_buffer(sc, bf); 1824 continue; 1825 } 1826 1827 lastbf = bf->bf_lastbf; 1828 list_cut_position(&bf_head, list, &lastbf->list); 1829 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); 1830 } 1831} 1832 1833/* 1834 * Drain a given TX queue (could be Beacon or Data) 1835 * 1836 * This assumes output has been stopped and 1837 * we do not need to block ath_tx_tasklet. 1838 */ 1839void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq) 1840{ 1841 ath_txq_lock(sc, txq); 1842 1843 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 1844 int idx = txq->txq_tailidx; 1845 1846 while (!list_empty(&txq->txq_fifo[idx])) { 1847 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]); 1848 1849 INCR(idx, ATH_TXFIFO_DEPTH); 1850 } 1851 txq->txq_tailidx = idx; 1852 } 1853 1854 txq->axq_link = NULL; 1855 txq->axq_tx_inprogress = false; 1856 ath_drain_txq_list(sc, txq, &txq->axq_q); 1857 1858 ath_txq_unlock_complete(sc, txq); 1859} 1860 1861bool ath_drain_all_txq(struct ath_softc *sc) 1862{ 1863 struct ath_hw *ah = sc->sc_ah; 1864 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1865 struct ath_txq *txq; 1866 int i; 1867 u32 npend = 0; 1868 1869 if (test_bit(ATH_OP_INVALID, &common->op_flags)) 1870 return true; 1871 1872 ath9k_hw_abort_tx_dma(ah); 1873 1874 /* Check if any queue remains active */ 1875 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1876 if (!ATH_TXQ_SETUP(sc, i)) 1877 continue; 1878 1879 if (!sc->tx.txq[i].axq_depth) 1880 continue; 1881 1882 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum)) 1883 npend |= BIT(i); 1884 } 1885 1886 if (npend) 1887 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend); 1888 1889 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1890 if (!ATH_TXQ_SETUP(sc, i)) 1891 continue; 1892 1893 /* 1894 * The caller will resume queues with ieee80211_wake_queues. 1895 * Mark the queue as not stopped to prevent ath_tx_complete 1896 * from waking the queue too early. 1897 */ 1898 txq = &sc->tx.txq[i]; 1899 txq->stopped = false; 1900 ath_draintxq(sc, txq); 1901 } 1902 1903 return !npend; 1904} 1905 1906void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 1907{ 1908 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum); 1909 sc->tx.txqsetup &= ~(1<<txq->axq_qnum); 1910} 1911 1912/* For each acq entry, for each tid, try to schedule packets 1913 * for transmit until ampdu_depth has reached min Q depth. 1914 */ 1915void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq) 1916{ 1917 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1918 struct ath_atx_ac *ac, *last_ac; 1919 struct ath_atx_tid *tid, *last_tid; 1920 struct list_head *ac_list; 1921 bool sent = false; 1922 1923 if (txq->mac80211_qnum < 0) 1924 return; 1925 1926 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) 1927 return; 1928 1929 spin_lock_bh(&sc->chan_lock); 1930 ac_list = &sc->cur_chan->acq[txq->mac80211_qnum]; 1931 1932 if (list_empty(ac_list)) { 1933 spin_unlock_bh(&sc->chan_lock); 1934 return; 1935 } 1936 1937 rcu_read_lock(); 1938 1939 last_ac = list_entry(ac_list->prev, struct ath_atx_ac, list); 1940 while (!list_empty(ac_list)) { 1941 bool stop = false; 1942 1943 if (sc->cur_chan->stopped) 1944 break; 1945 1946 ac = list_first_entry(ac_list, struct ath_atx_ac, list); 1947 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list); 1948 list_del(&ac->list); 1949 ac->sched = false; 1950 1951 while (!list_empty(&ac->tid_q)) { 1952 1953 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, 1954 list); 1955 list_del(&tid->list); 1956 tid->sched = false; 1957 1958 if (ath_tx_sched_aggr(sc, txq, tid, &stop)) 1959 sent = true; 1960 1961 /* 1962 * add tid to round-robin queue if more frames 1963 * are pending for the tid 1964 */ 1965 if (ath_tid_has_buffered(tid)) 1966 ath_tx_queue_tid(sc, txq, tid); 1967 1968 if (stop || tid == last_tid) 1969 break; 1970 } 1971 1972 if (!list_empty(&ac->tid_q) && !ac->sched) { 1973 ac->sched = true; 1974 list_add_tail(&ac->list, ac_list); 1975 } 1976 1977 if (stop) 1978 break; 1979 1980 if (ac == last_ac) { 1981 if (!sent) 1982 break; 1983 1984 sent = false; 1985 last_ac = list_entry(ac_list->prev, 1986 struct ath_atx_ac, list); 1987 } 1988 } 1989 1990 rcu_read_unlock(); 1991 spin_unlock_bh(&sc->chan_lock); 1992} 1993 1994void ath_txq_schedule_all(struct ath_softc *sc) 1995{ 1996 struct ath_txq *txq; 1997 int i; 1998 1999 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 2000 txq = sc->tx.txq_map[i]; 2001 2002 spin_lock_bh(&txq->axq_lock); 2003 ath_txq_schedule(sc, txq); 2004 spin_unlock_bh(&txq->axq_lock); 2005 } 2006} 2007 2008/***********/ 2009/* TX, DMA */ 2010/***********/ 2011 2012/* 2013 * Insert a chain of ath_buf (descriptors) on a txq and 2014 * assume the descriptors are already chained together by caller. 2015 */ 2016static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, 2017 struct list_head *head, bool internal) 2018{ 2019 struct ath_hw *ah = sc->sc_ah; 2020 struct ath_common *common = ath9k_hw_common(ah); 2021 struct ath_buf *bf, *bf_last; 2022 bool puttxbuf = false; 2023 bool edma; 2024 2025 /* 2026 * Insert the frame on the outbound list and 2027 * pass it on to the hardware. 2028 */ 2029 2030 if (list_empty(head)) 2031 return; 2032 2033 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 2034 bf = list_first_entry(head, struct ath_buf, list); 2035 bf_last = list_entry(head->prev, struct ath_buf, list); 2036 2037 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n", 2038 txq->axq_qnum, txq->axq_depth); 2039 2040 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) { 2041 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]); 2042 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH); 2043 puttxbuf = true; 2044 } else { 2045 list_splice_tail_init(head, &txq->axq_q); 2046 2047 if (txq->axq_link) { 2048 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr); 2049 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n", 2050 txq->axq_qnum, txq->axq_link, 2051 ito64(bf->bf_daddr), bf->bf_desc); 2052 } else if (!edma) 2053 puttxbuf = true; 2054 2055 txq->axq_link = bf_last->bf_desc; 2056 } 2057 2058 if (puttxbuf) { 2059 TX_STAT_INC(txq->axq_qnum, puttxbuf); 2060 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 2061 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n", 2062 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); 2063 } 2064 2065 if (!edma || sc->tx99_state) { 2066 TX_STAT_INC(txq->axq_qnum, txstart); 2067 ath9k_hw_txstart(ah, txq->axq_qnum); 2068 } 2069 2070 if (!internal) { 2071 while (bf) { 2072 txq->axq_depth++; 2073 if (bf_is_ampdu_not_probing(bf)) 2074 txq->axq_ampdu_depth++; 2075 2076 bf_last = bf->bf_lastbf; 2077 bf = bf_last->bf_next; 2078 bf_last->bf_next = NULL; 2079 } 2080 } 2081} 2082 2083static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, 2084 struct ath_atx_tid *tid, struct sk_buff *skb) 2085{ 2086 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2087 struct ath_frame_info *fi = get_frame_info(skb); 2088 struct list_head bf_head; 2089 struct ath_buf *bf = fi->bf; 2090 2091 INIT_LIST_HEAD(&bf_head); 2092 list_add_tail(&bf->list, &bf_head); 2093 bf->bf_state.bf_type = 0; 2094 if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) { 2095 bf->bf_state.bf_type = BUF_AMPDU; 2096 ath_tx_addto_baw(sc, tid, bf); 2097 } 2098 2099 bf->bf_next = NULL; 2100 bf->bf_lastbf = bf; 2101 ath_tx_fill_desc(sc, bf, txq, fi->framelen); 2102 ath_tx_txqaddbuf(sc, txq, &bf_head, false); 2103 TX_STAT_INC(txq->axq_qnum, queued); 2104} 2105 2106static void setup_frame_info(struct ieee80211_hw *hw, 2107 struct ieee80211_sta *sta, 2108 struct sk_buff *skb, 2109 int framelen) 2110{ 2111 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2112 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key; 2113 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2114 const struct ieee80211_rate *rate; 2115 struct ath_frame_info *fi = get_frame_info(skb); 2116 struct ath_node *an = NULL; 2117 enum ath9k_key_type keytype; 2118 bool short_preamble = false; 2119 u8 txpower; 2120 2121 /* 2122 * We check if Short Preamble is needed for the CTS rate by 2123 * checking the BSS's global flag. 2124 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used. 2125 */ 2126 if (tx_info->control.vif && 2127 tx_info->control.vif->bss_conf.use_short_preamble) 2128 short_preamble = true; 2129 2130 rate = ieee80211_get_rts_cts_rate(hw, tx_info); 2131 keytype = ath9k_cmn_get_hw_crypto_keytype(skb); 2132 2133 if (sta) 2134 an = (struct ath_node *) sta->drv_priv; 2135 2136 if (tx_info->control.vif) { 2137 struct ieee80211_vif *vif = tx_info->control.vif; 2138 2139 txpower = 2 * vif->bss_conf.txpower; 2140 } else { 2141 struct ath_softc *sc = hw->priv; 2142 2143 txpower = sc->cur_chan->cur_txpower; 2144 } 2145 2146 memset(fi, 0, sizeof(*fi)); 2147 fi->txq = -1; 2148 if (hw_key) 2149 fi->keyix = hw_key->hw_key_idx; 2150 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0) 2151 fi->keyix = an->ps_key; 2152 else 2153 fi->keyix = ATH9K_TXKEYIX_INVALID; 2154 fi->keytype = keytype; 2155 fi->framelen = framelen; 2156 fi->tx_power = txpower; 2157 2158 if (!rate) 2159 return; 2160 fi->rtscts_rate = rate->hw_value; 2161 if (short_preamble) 2162 fi->rtscts_rate |= rate->hw_value_short; 2163} 2164 2165u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate) 2166{ 2167 struct ath_hw *ah = sc->sc_ah; 2168 struct ath9k_channel *curchan = ah->curchan; 2169 2170 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) && 2171 (chainmask == 0x7) && (rate < 0x90)) 2172 return 0x3; 2173 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) && 2174 IS_CCK_RATE(rate)) 2175 return 0x2; 2176 else 2177 return chainmask; 2178} 2179 2180/* 2181 * Assign a descriptor (and sequence number if necessary, 2182 * and map buffer for DMA. Frees skb on error 2183 */ 2184static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, 2185 struct ath_txq *txq, 2186 struct ath_atx_tid *tid, 2187 struct sk_buff *skb) 2188{ 2189 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2190 struct ath_frame_info *fi = get_frame_info(skb); 2191 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2192 struct ath_buf *bf; 2193 int fragno; 2194 u16 seqno; 2195 2196 bf = ath_tx_get_buffer(sc); 2197 if (!bf) { 2198 ath_dbg(common, XMIT, "TX buffers are full\n"); 2199 return NULL; 2200 } 2201 2202 ATH_TXBUF_RESET(bf); 2203 2204 if (tid && ieee80211_is_data_present(hdr->frame_control)) { 2205 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG; 2206 seqno = tid->seq_next; 2207 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT); 2208 2209 if (fragno) 2210 hdr->seq_ctrl |= cpu_to_le16(fragno); 2211 2212 if (!ieee80211_has_morefrags(hdr->frame_control)) 2213 INCR(tid->seq_next, IEEE80211_SEQ_MAX); 2214 2215 bf->bf_state.seqno = seqno; 2216 } 2217 2218 bf->bf_mpdu = skb; 2219 2220 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, 2221 skb->len, DMA_TO_DEVICE); 2222 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) { 2223 bf->bf_mpdu = NULL; 2224 bf->bf_buf_addr = 0; 2225 ath_err(ath9k_hw_common(sc->sc_ah), 2226 "dma_mapping_error() on TX\n"); 2227 ath_tx_return_buffer(sc, bf); 2228 return NULL; 2229 } 2230 2231 fi->bf = bf; 2232 2233 return bf; 2234} 2235 2236void ath_assign_seq(struct ath_common *common, struct sk_buff *skb) 2237{ 2238 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 2239 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 2240 struct ieee80211_vif *vif = info->control.vif; 2241 struct ath_vif *avp; 2242 2243 if (!(info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)) 2244 return; 2245 2246 if (!vif) 2247 return; 2248 2249 avp = (struct ath_vif *)vif->drv_priv; 2250 2251 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) 2252 avp->seq_no += 0x10; 2253 2254 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); 2255 hdr->seq_ctrl |= cpu_to_le16(avp->seq_no); 2256} 2257 2258static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb, 2259 struct ath_tx_control *txctl) 2260{ 2261 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 2262 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 2263 struct ieee80211_sta *sta = txctl->sta; 2264 struct ieee80211_vif *vif = info->control.vif; 2265 struct ath_vif *avp; 2266 struct ath_softc *sc = hw->priv; 2267 int frmlen = skb->len + FCS_LEN; 2268 int padpos, padsize; 2269 2270 /* NOTE: sta can be NULL according to net/mac80211.h */ 2271 if (sta) 2272 txctl->an = (struct ath_node *)sta->drv_priv; 2273 else if (vif && ieee80211_is_data(hdr->frame_control)) { 2274 avp = (void *)vif->drv_priv; 2275 txctl->an = &avp->mcast_node; 2276 } 2277 2278 if (info->control.hw_key) 2279 frmlen += info->control.hw_key->icv_len; 2280 2281 ath_assign_seq(ath9k_hw_common(sc->sc_ah), skb); 2282 2283 if ((vif && vif->type != NL80211_IFTYPE_AP && 2284 vif->type != NL80211_IFTYPE_AP_VLAN) || 2285 !ieee80211_is_data(hdr->frame_control)) 2286 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT; 2287 2288 /* Add the padding after the header if this is not already done */ 2289 padpos = ieee80211_hdrlen(hdr->frame_control); 2290 padsize = padpos & 3; 2291 if (padsize && skb->len > padpos) { 2292 if (skb_headroom(skb) < padsize) 2293 return -ENOMEM; 2294 2295 skb_push(skb, padsize); 2296 memmove(skb->data, skb->data + padsize, padpos); 2297 } 2298 2299 setup_frame_info(hw, sta, skb, frmlen); 2300 return 0; 2301} 2302 2303 2304/* Upon failure caller should free skb */ 2305int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, 2306 struct ath_tx_control *txctl) 2307{ 2308 struct ieee80211_hdr *hdr; 2309 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 2310 struct ieee80211_sta *sta = txctl->sta; 2311 struct ieee80211_vif *vif = info->control.vif; 2312 struct ath_frame_info *fi = get_frame_info(skb); 2313 struct ath_vif *avp = NULL; 2314 struct ath_softc *sc = hw->priv; 2315 struct ath_txq *txq = txctl->txq; 2316 struct ath_atx_tid *tid = NULL; 2317 struct ath_buf *bf; 2318 bool queue, skip_uapsd = false, ps_resp; 2319 int q, ret; 2320 2321 if (vif) 2322 avp = (void *)vif->drv_priv; 2323 2324 if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN) 2325 txctl->force_channel = true; 2326 2327 ps_resp = !!(info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE); 2328 2329 ret = ath_tx_prepare(hw, skb, txctl); 2330 if (ret) 2331 return ret; 2332 2333 hdr = (struct ieee80211_hdr *) skb->data; 2334 /* 2335 * At this point, the vif, hw_key and sta pointers in the tx control 2336 * info are no longer valid (overwritten by the ath_frame_info data. 2337 */ 2338 2339 q = skb_get_queue_mapping(skb); 2340 2341 ath_txq_lock(sc, txq); 2342 if (txq == sc->tx.txq_map[q]) { 2343 fi->txq = q; 2344 if (++txq->pending_frames > sc->tx.txq_max_pending[q] && 2345 !txq->stopped) { 2346 if (ath9k_is_chanctx_enabled()) 2347 ieee80211_stop_queue(sc->hw, info->hw_queue); 2348 else 2349 ieee80211_stop_queue(sc->hw, q); 2350 txq->stopped = true; 2351 } 2352 } 2353 2354 queue = ieee80211_is_data_present(hdr->frame_control); 2355 2356 /* Force queueing of all frames that belong to a virtual interface on 2357 * a different channel context, to ensure that they are sent on the 2358 * correct channel. 2359 */ 2360 if (((avp && avp->chanctx != sc->cur_chan) || 2361 sc->cur_chan->stopped) && !txctl->force_channel) { 2362 if (!txctl->an) 2363 txctl->an = &avp->mcast_node; 2364 queue = true; 2365 skip_uapsd = true; 2366 } 2367 2368 if (txctl->an && queue) 2369 tid = ath_get_skb_tid(sc, txctl->an, skb); 2370 2371 if (!skip_uapsd && ps_resp) { 2372 ath_txq_unlock(sc, txq); 2373 txq = sc->tx.uapsdq; 2374 ath_txq_lock(sc, txq); 2375 } else if (txctl->an && queue) { 2376 WARN_ON(tid->ac->txq != txctl->txq); 2377 2378 if (info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) 2379 tid->ac->clear_ps_filter = true; 2380 2381 /* 2382 * Add this frame to software queue for scheduling later 2383 * for aggregation. 2384 */ 2385 TX_STAT_INC(txq->axq_qnum, a_queued_sw); 2386 __skb_queue_tail(&tid->buf_q, skb); 2387 if (!txctl->an->sleeping) 2388 ath_tx_queue_tid(sc, txq, tid); 2389 2390 ath_txq_schedule(sc, txq); 2391 goto out; 2392 } 2393 2394 bf = ath_tx_setup_buffer(sc, txq, tid, skb); 2395 if (!bf) { 2396 ath_txq_skb_done(sc, txq, skb); 2397 if (txctl->paprd) 2398 dev_kfree_skb_any(skb); 2399 else 2400 ieee80211_free_txskb(sc->hw, skb); 2401 goto out; 2402 } 2403 2404 bf->bf_state.bfs_paprd = txctl->paprd; 2405 2406 if (txctl->paprd) 2407 bf->bf_state.bfs_paprd_timestamp = jiffies; 2408 2409 ath_set_rates(vif, sta, bf); 2410 ath_tx_send_normal(sc, txq, tid, skb); 2411 2412out: 2413 ath_txq_unlock(sc, txq); 2414 2415 return 0; 2416} 2417 2418void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 2419 struct sk_buff *skb) 2420{ 2421 struct ath_softc *sc = hw->priv; 2422 struct ath_tx_control txctl = { 2423 .txq = sc->beacon.cabq 2424 }; 2425 struct ath_tx_info info = {}; 2426 struct ieee80211_hdr *hdr; 2427 struct ath_buf *bf_tail = NULL; 2428 struct ath_buf *bf; 2429 LIST_HEAD(bf_q); 2430 int duration = 0; 2431 int max_duration; 2432 2433 max_duration = 2434 sc->cur_chan->beacon.beacon_interval * 1000 * 2435 sc->cur_chan->beacon.dtim_period / ATH_BCBUF; 2436 2437 do { 2438 struct ath_frame_info *fi = get_frame_info(skb); 2439 2440 if (ath_tx_prepare(hw, skb, &txctl)) 2441 break; 2442 2443 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb); 2444 if (!bf) 2445 break; 2446 2447 bf->bf_lastbf = bf; 2448 ath_set_rates(vif, NULL, bf); 2449 ath_buf_set_rate(sc, bf, &info, fi->framelen, false); 2450 duration += info.rates[0].PktDuration; 2451 if (bf_tail) 2452 bf_tail->bf_next = bf; 2453 2454 list_add_tail(&bf->list, &bf_q); 2455 bf_tail = bf; 2456 skb = NULL; 2457 2458 if (duration > max_duration) 2459 break; 2460 2461 skb = ieee80211_get_buffered_bc(hw, vif); 2462 } while(skb); 2463 2464 if (skb) 2465 ieee80211_free_txskb(hw, skb); 2466 2467 if (list_empty(&bf_q)) 2468 return; 2469 2470 bf = list_first_entry(&bf_q, struct ath_buf, list); 2471 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data; 2472 2473 if (hdr->frame_control & IEEE80211_FCTL_MOREDATA) { 2474 hdr->frame_control &= ~IEEE80211_FCTL_MOREDATA; 2475 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, 2476 sizeof(*hdr), DMA_TO_DEVICE); 2477 } 2478 2479 ath_txq_lock(sc, txctl.txq); 2480 ath_tx_fill_desc(sc, bf, txctl.txq, 0); 2481 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false); 2482 TX_STAT_INC(txctl.txq->axq_qnum, queued); 2483 ath_txq_unlock(sc, txctl.txq); 2484} 2485 2486/*****************/ 2487/* TX Completion */ 2488/*****************/ 2489 2490static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, 2491 int tx_flags, struct ath_txq *txq) 2492{ 2493 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2494 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2495 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data; 2496 int padpos, padsize; 2497 unsigned long flags; 2498 2499 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb); 2500 2501 if (sc->sc_ah->caldata) 2502 set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags); 2503 2504 if (!(tx_flags & ATH_TX_ERROR)) { 2505 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) 2506 tx_info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 2507 else 2508 tx_info->flags |= IEEE80211_TX_STAT_ACK; 2509 } 2510 2511 padpos = ieee80211_hdrlen(hdr->frame_control); 2512 padsize = padpos & 3; 2513 if (padsize && skb->len>padpos+padsize) { 2514 /* 2515 * Remove MAC header padding before giving the frame back to 2516 * mac80211. 2517 */ 2518 memmove(skb->data + padsize, skb->data, padpos); 2519 skb_pull(skb, padsize); 2520 } 2521 2522 spin_lock_irqsave(&sc->sc_pm_lock, flags); 2523 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) { 2524 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK; 2525 ath_dbg(common, PS, 2526 "Going back to sleep after having received TX status (0x%lx)\n", 2527 sc->ps_flags & (PS_WAIT_FOR_BEACON | 2528 PS_WAIT_FOR_CAB | 2529 PS_WAIT_FOR_PSPOLL_DATA | 2530 PS_WAIT_FOR_TX_ACK)); 2531 } 2532 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 2533 2534 __skb_queue_tail(&txq->complete_q, skb); 2535 ath_txq_skb_done(sc, txq, skb); 2536} 2537 2538static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, 2539 struct ath_txq *txq, struct list_head *bf_q, 2540 struct ath_tx_status *ts, int txok) 2541{ 2542 struct sk_buff *skb = bf->bf_mpdu; 2543 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2544 unsigned long flags; 2545 int tx_flags = 0; 2546 2547 if (!txok) 2548 tx_flags |= ATH_TX_ERROR; 2549 2550 if (ts->ts_status & ATH9K_TXERR_FILT) 2551 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 2552 2553 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE); 2554 bf->bf_buf_addr = 0; 2555 if (sc->tx99_state) 2556 goto skip_tx_complete; 2557 2558 if (bf->bf_state.bfs_paprd) { 2559 if (time_after(jiffies, 2560 bf->bf_state.bfs_paprd_timestamp + 2561 msecs_to_jiffies(ATH_PAPRD_TIMEOUT))) 2562 dev_kfree_skb_any(skb); 2563 else 2564 complete(&sc->paprd_complete); 2565 } else { 2566 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags); 2567 ath_tx_complete(sc, skb, tx_flags, txq); 2568 } 2569skip_tx_complete: 2570 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't 2571 * accidentally reference it later. 2572 */ 2573 bf->bf_mpdu = NULL; 2574 2575 /* 2576 * Return the list of ath_buf of this mpdu to free queue 2577 */ 2578 spin_lock_irqsave(&sc->tx.txbuflock, flags); 2579 list_splice_tail_init(bf_q, &sc->tx.txbuf); 2580 spin_unlock_irqrestore(&sc->tx.txbuflock, flags); 2581} 2582 2583static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, 2584 struct ath_tx_status *ts, int nframes, int nbad, 2585 int txok) 2586{ 2587 struct sk_buff *skb = bf->bf_mpdu; 2588 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2589 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2590 struct ieee80211_hw *hw = sc->hw; 2591 struct ath_hw *ah = sc->sc_ah; 2592 u8 i, tx_rateindex; 2593 2594 if (txok) 2595 tx_info->status.ack_signal = ts->ts_rssi; 2596 2597 tx_rateindex = ts->ts_rateindex; 2598 WARN_ON(tx_rateindex >= hw->max_rates); 2599 2600 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { 2601 tx_info->flags |= IEEE80211_TX_STAT_AMPDU; 2602 2603 BUG_ON(nbad > nframes); 2604 } 2605 tx_info->status.ampdu_len = nframes; 2606 tx_info->status.ampdu_ack_len = nframes - nbad; 2607 2608 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 && 2609 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) { 2610 /* 2611 * If an underrun error is seen assume it as an excessive 2612 * retry only if max frame trigger level has been reached 2613 * (2 KB for single stream, and 4 KB for dual stream). 2614 * Adjust the long retry as if the frame was tried 2615 * hw->max_rate_tries times to affect how rate control updates 2616 * PER for the failed rate. 2617 * In case of congestion on the bus penalizing this type of 2618 * underruns should help hardware actually transmit new frames 2619 * successfully by eventually preferring slower rates. 2620 * This itself should also alleviate congestion on the bus. 2621 */ 2622 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN | 2623 ATH9K_TX_DELIM_UNDERRUN)) && 2624 ieee80211_is_data(hdr->frame_control) && 2625 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level) 2626 tx_info->status.rates[tx_rateindex].count = 2627 hw->max_rate_tries; 2628 } 2629 2630 for (i = tx_rateindex + 1; i < hw->max_rates; i++) { 2631 tx_info->status.rates[i].count = 0; 2632 tx_info->status.rates[i].idx = -1; 2633 } 2634 2635 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1; 2636} 2637 2638static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 2639{ 2640 struct ath_hw *ah = sc->sc_ah; 2641 struct ath_common *common = ath9k_hw_common(ah); 2642 struct ath_buf *bf, *lastbf, *bf_held = NULL; 2643 struct list_head bf_head; 2644 struct ath_desc *ds; 2645 struct ath_tx_status ts; 2646 int status; 2647 2648 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n", 2649 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), 2650 txq->axq_link); 2651 2652 ath_txq_lock(sc, txq); 2653 for (;;) { 2654 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) 2655 break; 2656 2657 if (list_empty(&txq->axq_q)) { 2658 txq->axq_link = NULL; 2659 ath_txq_schedule(sc, txq); 2660 break; 2661 } 2662 bf = list_first_entry(&txq->axq_q, struct ath_buf, list); 2663 2664 /* 2665 * There is a race condition that a BH gets scheduled 2666 * after sw writes TxE and before hw re-load the last 2667 * descriptor to get the newly chained one. 2668 * Software must keep the last DONE descriptor as a 2669 * holding descriptor - software does so by marking 2670 * it with the STALE flag. 2671 */ 2672 bf_held = NULL; 2673 if (bf->bf_state.stale) { 2674 bf_held = bf; 2675 if (list_is_last(&bf_held->list, &txq->axq_q)) 2676 break; 2677 2678 bf = list_entry(bf_held->list.next, struct ath_buf, 2679 list); 2680 } 2681 2682 lastbf = bf->bf_lastbf; 2683 ds = lastbf->bf_desc; 2684 2685 memset(&ts, 0, sizeof(ts)); 2686 status = ath9k_hw_txprocdesc(ah, ds, &ts); 2687 if (status == -EINPROGRESS) 2688 break; 2689 2690 TX_STAT_INC(txq->axq_qnum, txprocdesc); 2691 2692 /* 2693 * Remove ath_buf's of the same transmit unit from txq, 2694 * however leave the last descriptor back as the holding 2695 * descriptor for hw. 2696 */ 2697 lastbf->bf_state.stale = true; 2698 INIT_LIST_HEAD(&bf_head); 2699 if (!list_is_singular(&lastbf->list)) 2700 list_cut_position(&bf_head, 2701 &txq->axq_q, lastbf->list.prev); 2702 2703 if (bf_held) { 2704 list_del(&bf_held->list); 2705 ath_tx_return_buffer(sc, bf_held); 2706 } 2707 2708 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); 2709 } 2710 ath_txq_unlock_complete(sc, txq); 2711} 2712 2713void ath_tx_tasklet(struct ath_softc *sc) 2714{ 2715 struct ath_hw *ah = sc->sc_ah; 2716 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs; 2717 int i; 2718 2719 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 2720 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i))) 2721 ath_tx_processq(sc, &sc->tx.txq[i]); 2722 } 2723} 2724 2725void ath_tx_edma_tasklet(struct ath_softc *sc) 2726{ 2727 struct ath_tx_status ts; 2728 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2729 struct ath_hw *ah = sc->sc_ah; 2730 struct ath_txq *txq; 2731 struct ath_buf *bf, *lastbf; 2732 struct list_head bf_head; 2733 struct list_head *fifo_list; 2734 int status; 2735 2736 for (;;) { 2737 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) 2738 break; 2739 2740 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts); 2741 if (status == -EINPROGRESS) 2742 break; 2743 if (status == -EIO) { 2744 ath_dbg(common, XMIT, "Error processing tx status\n"); 2745 break; 2746 } 2747 2748 /* Process beacon completions separately */ 2749 if (ts.qid == sc->beacon.beaconq) { 2750 sc->beacon.tx_processed = true; 2751 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); 2752 2753 if (ath9k_is_chanctx_enabled()) { 2754 ath_chanctx_event(sc, NULL, 2755 ATH_CHANCTX_EVENT_BEACON_SENT); 2756 } 2757 2758 ath9k_csa_update(sc); 2759 continue; 2760 } 2761 2762 txq = &sc->tx.txq[ts.qid]; 2763 2764 ath_txq_lock(sc, txq); 2765 2766 TX_STAT_INC(txq->axq_qnum, txprocdesc); 2767 2768 fifo_list = &txq->txq_fifo[txq->txq_tailidx]; 2769 if (list_empty(fifo_list)) { 2770 ath_txq_unlock(sc, txq); 2771 return; 2772 } 2773 2774 bf = list_first_entry(fifo_list, struct ath_buf, list); 2775 if (bf->bf_state.stale) { 2776 list_del(&bf->list); 2777 ath_tx_return_buffer(sc, bf); 2778 bf = list_first_entry(fifo_list, struct ath_buf, list); 2779 } 2780 2781 lastbf = bf->bf_lastbf; 2782 2783 INIT_LIST_HEAD(&bf_head); 2784 if (list_is_last(&lastbf->list, fifo_list)) { 2785 list_splice_tail_init(fifo_list, &bf_head); 2786 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH); 2787 2788 if (!list_empty(&txq->axq_q)) { 2789 struct list_head bf_q; 2790 2791 INIT_LIST_HEAD(&bf_q); 2792 txq->axq_link = NULL; 2793 list_splice_tail_init(&txq->axq_q, &bf_q); 2794 ath_tx_txqaddbuf(sc, txq, &bf_q, true); 2795 } 2796 } else { 2797 lastbf->bf_state.stale = true; 2798 if (bf != lastbf) 2799 list_cut_position(&bf_head, fifo_list, 2800 lastbf->list.prev); 2801 } 2802 2803 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); 2804 ath_txq_unlock_complete(sc, txq); 2805 } 2806} 2807 2808/*****************/ 2809/* Init, Cleanup */ 2810/*****************/ 2811 2812static int ath_txstatus_setup(struct ath_softc *sc, int size) 2813{ 2814 struct ath_descdma *dd = &sc->txsdma; 2815 u8 txs_len = sc->sc_ah->caps.txs_len; 2816 2817 dd->dd_desc_len = size * txs_len; 2818 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len, 2819 &dd->dd_desc_paddr, GFP_KERNEL); 2820 if (!dd->dd_desc) 2821 return -ENOMEM; 2822 2823 return 0; 2824} 2825 2826static int ath_tx_edma_init(struct ath_softc *sc) 2827{ 2828 int err; 2829 2830 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE); 2831 if (!err) 2832 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc, 2833 sc->txsdma.dd_desc_paddr, 2834 ATH_TXSTATUS_RING_SIZE); 2835 2836 return err; 2837} 2838 2839int ath_tx_init(struct ath_softc *sc, int nbufs) 2840{ 2841 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2842 int error = 0; 2843 2844 spin_lock_init(&sc->tx.txbuflock); 2845 2846 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, 2847 "tx", nbufs, 1, 1); 2848 if (error != 0) { 2849 ath_err(common, 2850 "Failed to allocate tx descriptors: %d\n", error); 2851 return error; 2852 } 2853 2854 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, 2855 "beacon", ATH_BCBUF, 1, 1); 2856 if (error != 0) { 2857 ath_err(common, 2858 "Failed to allocate beacon descriptors: %d\n", error); 2859 return error; 2860 } 2861 2862 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work); 2863 2864 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 2865 error = ath_tx_edma_init(sc); 2866 2867 return error; 2868} 2869 2870void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an) 2871{ 2872 struct ath_atx_tid *tid; 2873 struct ath_atx_ac *ac; 2874 int tidno, acno; 2875 2876 for (tidno = 0, tid = &an->tid[tidno]; 2877 tidno < IEEE80211_NUM_TIDS; 2878 tidno++, tid++) { 2879 tid->an = an; 2880 tid->tidno = tidno; 2881 tid->seq_start = tid->seq_next = 0; 2882 tid->baw_size = WME_MAX_BA; 2883 tid->baw_head = tid->baw_tail = 0; 2884 tid->sched = false; 2885 tid->active = false; 2886 __skb_queue_head_init(&tid->buf_q); 2887 __skb_queue_head_init(&tid->retry_q); 2888 acno = TID_TO_WME_AC(tidno); 2889 tid->ac = &an->ac[acno]; 2890 } 2891 2892 for (acno = 0, ac = &an->ac[acno]; 2893 acno < IEEE80211_NUM_ACS; acno++, ac++) { 2894 ac->sched = false; 2895 ac->clear_ps_filter = true; 2896 ac->txq = sc->tx.txq_map[acno]; 2897 INIT_LIST_HEAD(&ac->tid_q); 2898 } 2899} 2900 2901void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an) 2902{ 2903 struct ath_atx_ac *ac; 2904 struct ath_atx_tid *tid; 2905 struct ath_txq *txq; 2906 int tidno; 2907 2908 for (tidno = 0, tid = &an->tid[tidno]; 2909 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) { 2910 2911 ac = tid->ac; 2912 txq = ac->txq; 2913 2914 ath_txq_lock(sc, txq); 2915 2916 if (tid->sched) { 2917 list_del(&tid->list); 2918 tid->sched = false; 2919 } 2920 2921 if (ac->sched) { 2922 list_del(&ac->list); 2923 tid->ac->sched = false; 2924 } 2925 2926 ath_tid_drain(sc, txq, tid); 2927 tid->active = false; 2928 2929 ath_txq_unlock(sc, txq); 2930 } 2931} 2932 2933#ifdef CONFIG_ATH9K_TX99 2934 2935int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb, 2936 struct ath_tx_control *txctl) 2937{ 2938 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 2939 struct ath_frame_info *fi = get_frame_info(skb); 2940 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2941 struct ath_buf *bf; 2942 int padpos, padsize; 2943 2944 padpos = ieee80211_hdrlen(hdr->frame_control); 2945 padsize = padpos & 3; 2946 2947 if (padsize && skb->len > padpos) { 2948 if (skb_headroom(skb) < padsize) { 2949 ath_dbg(common, XMIT, 2950 "tx99 padding failed\n"); 2951 return -EINVAL; 2952 } 2953 2954 skb_push(skb, padsize); 2955 memmove(skb->data, skb->data + padsize, padpos); 2956 } 2957 2958 fi->keyix = ATH9K_TXKEYIX_INVALID; 2959 fi->framelen = skb->len + FCS_LEN; 2960 fi->keytype = ATH9K_KEY_TYPE_CLEAR; 2961 2962 bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb); 2963 if (!bf) { 2964 ath_dbg(common, XMIT, "tx99 buffer setup failed\n"); 2965 return -EINVAL; 2966 } 2967 2968 ath_set_rates(sc->tx99_vif, NULL, bf); 2969 2970 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr); 2971 ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum); 2972 2973 ath_tx_send_normal(sc, txctl->txq, NULL, skb); 2974 2975 return 0; 2976} 2977 2978#endif /* CONFIG_ATH9K_TX99 */ 2979