1#ifndef B43_XMIT_H_ 2#define B43_XMIT_H_ 3 4#include "main.h" 5#include <net/mac80211.h> 6 7 8#define _b43_declare_plcp_hdr(size) \ 9 struct b43_plcp_hdr##size { \ 10 union { \ 11 __le32 data; \ 12 __u8 raw[size]; \ 13 } __packed; \ 14 } __packed 15 16/* struct b43_plcp_hdr4 */ 17_b43_declare_plcp_hdr(4); 18/* struct b43_plcp_hdr6 */ 19_b43_declare_plcp_hdr(6); 20 21#undef _b43_declare_plcp_hdr 22 23/* TX header for v4 firmware */ 24struct b43_txhdr { 25 __le32 mac_ctl; /* MAC TX control */ 26 __le16 mac_frame_ctl; /* Copy of the FrameControl field */ 27 __le16 tx_fes_time_norm; /* TX FES Time Normal */ 28 __le16 phy_ctl; /* PHY TX control */ 29 __le16 phy_ctl1; /* PHY TX control word 1 */ 30 __le16 phy_ctl1_fb; /* PHY TX control word 1 for fallback rates */ 31 __le16 phy_ctl1_rts; /* PHY TX control word 1 RTS */ 32 __le16 phy_ctl1_rts_fb; /* PHY TX control word 1 RTS for fallback rates */ 33 __u8 phy_rate; /* PHY rate */ 34 __u8 phy_rate_rts; /* PHY rate for RTS/CTS */ 35 __u8 extra_ft; /* Extra Frame Types */ 36 __u8 chan_radio_code; /* Channel Radio Code */ 37 __u8 iv[16]; /* Encryption IV */ 38 __u8 tx_receiver[6]; /* TX Frame Receiver address */ 39 __le16 tx_fes_time_fb; /* TX FES Time Fallback */ 40 struct b43_plcp_hdr6 rts_plcp_fb; /* RTS fallback PLCP header */ 41 __le16 rts_dur_fb; /* RTS fallback duration */ 42 struct b43_plcp_hdr6 plcp_fb; /* Fallback PLCP header */ 43 __le16 dur_fb; /* Fallback duration */ 44 __le16 mimo_modelen; /* MIMO mode length */ 45 __le16 mimo_ratelen_fb; /* MIMO fallback rate length */ 46 __le32 timeout; /* Timeout */ 47 48 union { 49 /* Tested with 598.314, 644.1001 and 666.2 */ 50 struct { 51 __le16 mimo_antenna; /* MIMO antenna select */ 52 __le16 preload_size; /* Preload size */ 53 PAD_BYTES(2); 54 __le16 cookie; /* TX frame cookie */ 55 __le16 tx_status; /* TX status */ 56 __le16 max_n_mpdus; 57 __le16 max_a_bytes_mrt; 58 __le16 max_a_bytes_fbr; 59 __le16 min_m_bytes; 60 struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP header */ 61 __u8 rts_frame[16]; /* The RTS frame (if used) */ 62 PAD_BYTES(2); 63 struct b43_plcp_hdr6 plcp; /* Main PLCP header */ 64 } format_598 __packed; 65 66 /* Tested with 410.2160, 478.104 and 508.* */ 67 struct { 68 __le16 mimo_antenna; /* MIMO antenna select */ 69 __le16 preload_size; /* Preload size */ 70 PAD_BYTES(2); 71 __le16 cookie; /* TX frame cookie */ 72 __le16 tx_status; /* TX status */ 73 struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP header */ 74 __u8 rts_frame[16]; /* The RTS frame (if used) */ 75 PAD_BYTES(2); 76 struct b43_plcp_hdr6 plcp; /* Main PLCP header */ 77 } format_410 __packed; 78 79 /* Tested with 351.126 */ 80 struct { 81 PAD_BYTES(2); 82 __le16 cookie; /* TX frame cookie */ 83 __le16 tx_status; /* TX status */ 84 struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP header */ 85 __u8 rts_frame[16]; /* The RTS frame (if used) */ 86 PAD_BYTES(2); 87 struct b43_plcp_hdr6 plcp; /* Main PLCP header */ 88 } format_351 __packed; 89 90 } __packed; 91} __packed; 92 93struct b43_tx_legacy_rate_phy_ctl_entry { 94 u8 bitrate; 95 u16 coding_rate; 96 u16 modulation; 97}; 98 99/* MAC TX control */ 100#define B43_TXH_MAC_RTS_FB_SHORTPRMBL 0x80000000 /* RTS fallback preamble */ 101#define B43_TXH_MAC_RTS_SHORTPRMBL 0x40000000 /* RTS main rate preamble */ 102#define B43_TXH_MAC_FB_SHORTPRMBL 0x20000000 /* Main fallback preamble */ 103#define B43_TXH_MAC_USEFBR 0x10000000 /* Use fallback rate for this AMPDU */ 104#define B43_TXH_MAC_KEYIDX 0x0FF00000 /* Security key index */ 105#define B43_TXH_MAC_KEYIDX_SHIFT 20 106#define B43_TXH_MAC_ALT_TXPWR 0x00080000 /* Use alternate txpwr defined at loc. M_ALT_TXPWR_IDX */ 107#define B43_TXH_MAC_KEYALG 0x00070000 /* Security key algorithm */ 108#define B43_TXH_MAC_KEYALG_SHIFT 16 109#define B43_TXH_MAC_AMIC 0x00008000 /* AMIC */ 110#define B43_TXH_MAC_RIFS 0x00004000 /* Use RIFS */ 111#define B43_TXH_MAC_LIFETIME 0x00002000 /* Lifetime */ 112#define B43_TXH_MAC_FRAMEBURST 0x00001000 /* Frameburst */ 113#define B43_TXH_MAC_SENDCTS 0x00000800 /* Send CTS-to-self */ 114#define B43_TXH_MAC_AMPDU 0x00000600 /* AMPDU status */ 115#define B43_TXH_MAC_AMPDU_MPDU 0x00000000 /* Regular MPDU, not an AMPDU */ 116#define B43_TXH_MAC_AMPDU_FIRST 0x00000200 /* First MPDU or AMPDU */ 117#define B43_TXH_MAC_AMPDU_INTER 0x00000400 /* Intermediate MPDU or AMPDU */ 118#define B43_TXH_MAC_AMPDU_LAST 0x00000600 /* Last (or only) MPDU of AMPDU */ 119#define B43_TXH_MAC_40MHZ 0x00000100 /* Use 40 MHz bandwidth */ 120#define B43_TXH_MAC_5GHZ 0x00000080 /* 5GHz band */ 121#define B43_TXH_MAC_DFCS 0x00000040 /* DFCS */ 122#define B43_TXH_MAC_IGNPMQ 0x00000020 /* Ignore PMQ */ 123#define B43_TXH_MAC_HWSEQ 0x00000010 /* Use Hardware Sequence Number */ 124#define B43_TXH_MAC_STMSDU 0x00000008 /* Start MSDU */ 125#define B43_TXH_MAC_SENDRTS 0x00000004 /* Send RTS */ 126#define B43_TXH_MAC_LONGFRAME 0x00000002 /* Long frame */ 127#define B43_TXH_MAC_ACK 0x00000001 /* Immediate ACK */ 128 129/* Extra Frame Types */ 130#define B43_TXH_EFT_FB 0x03 /* Data frame fallback encoding */ 131#define B43_TXH_EFT_FB_CCK 0x00 /* CCK */ 132#define B43_TXH_EFT_FB_OFDM 0x01 /* OFDM */ 133#define B43_TXH_EFT_FB_HT 0x02 /* HT */ 134#define B43_TXH_EFT_FB_VHT 0x03 /* VHT */ 135#define B43_TXH_EFT_RTS 0x0C /* RTS/CTS encoding */ 136#define B43_TXH_EFT_RTS_CCK 0x00 /* CCK */ 137#define B43_TXH_EFT_RTS_OFDM 0x04 /* OFDM */ 138#define B43_TXH_EFT_RTS_HT 0x08 /* HT */ 139#define B43_TXH_EFT_RTS_VHT 0x0C /* VHT */ 140#define B43_TXH_EFT_RTSFB 0x30 /* RTS/CTS fallback encoding */ 141#define B43_TXH_EFT_RTSFB_CCK 0x00 /* CCK */ 142#define B43_TXH_EFT_RTSFB_OFDM 0x10 /* OFDM */ 143#define B43_TXH_EFT_RTSFB_HT 0x20 /* HT */ 144#define B43_TXH_EFT_RTSFB_VHT 0x30 /* VHT */ 145 146/* PHY TX control word */ 147#define B43_TXH_PHY_ENC 0x0003 /* Data frame encoding */ 148#define B43_TXH_PHY_ENC_CCK 0x0000 /* CCK */ 149#define B43_TXH_PHY_ENC_OFDM 0x0001 /* OFDM */ 150#define B43_TXH_PHY_ENC_HT 0x0002 /* HT */ 151#define B43_TXH_PHY_ENC_VHT 0x0003 /* VHT */ 152#define B43_TXH_PHY_SHORTPRMBL 0x0010 /* Use short preamble */ 153#define B43_TXH_PHY_ANT 0x03C0 /* Antenna selection */ 154#define B43_TXH_PHY_ANT0 0x0000 /* Use antenna 0 */ 155#define B43_TXH_PHY_ANT1 0x0040 /* Use antenna 1 */ 156#define B43_TXH_PHY_ANT01AUTO 0x00C0 /* Use antenna 0/1 auto */ 157#define B43_TXH_PHY_ANT2 0x0100 /* Use antenna 2 */ 158#define B43_TXH_PHY_ANT3 0x0200 /* Use antenna 3 */ 159#define B43_TXH_PHY_TXPWR 0xFC00 /* TX power */ 160#define B43_TXH_PHY_TXPWR_SHIFT 10 161 162/* PHY TX control word 1 */ 163#define B43_TXH_PHY1_BW 0x0007 /* Bandwidth */ 164#define B43_TXH_PHY1_BW_10 0x0000 /* 10 MHz */ 165#define B43_TXH_PHY1_BW_10U 0x0001 /* 10 MHz upper */ 166#define B43_TXH_PHY1_BW_20 0x0002 /* 20 MHz */ 167#define B43_TXH_PHY1_BW_20U 0x0003 /* 20 MHz upper */ 168#define B43_TXH_PHY1_BW_40 0x0004 /* 40 MHz */ 169#define B43_TXH_PHY1_BW_40DUP 0x0005 /* 40 MHz duplicate */ 170#define B43_TXH_PHY1_MODE 0x0038 /* Mode */ 171#define B43_TXH_PHY1_MODE_SISO 0x0000 /* SISO */ 172#define B43_TXH_PHY1_MODE_CDD 0x0008 /* CDD */ 173#define B43_TXH_PHY1_MODE_STBC 0x0010 /* STBC */ 174#define B43_TXH_PHY1_MODE_SDM 0x0018 /* SDM */ 175#define B43_TXH_PHY1_CRATE 0x0700 /* Coding rate */ 176#define B43_TXH_PHY1_CRATE_1_2 0x0000 /* 1/2 */ 177#define B43_TXH_PHY1_CRATE_2_3 0x0100 /* 2/3 */ 178#define B43_TXH_PHY1_CRATE_3_4 0x0200 /* 3/4 */ 179#define B43_TXH_PHY1_CRATE_4_5 0x0300 /* 4/5 */ 180#define B43_TXH_PHY1_CRATE_5_6 0x0400 /* 5/6 */ 181#define B43_TXH_PHY1_CRATE_7_8 0x0600 /* 7/8 */ 182#define B43_TXH_PHY1_MODUL 0x3800 /* Modulation scheme */ 183#define B43_TXH_PHY1_MODUL_BPSK 0x0000 /* BPSK */ 184#define B43_TXH_PHY1_MODUL_QPSK 0x0800 /* QPSK */ 185#define B43_TXH_PHY1_MODUL_QAM16 0x1000 /* QAM16 */ 186#define B43_TXH_PHY1_MODUL_QAM64 0x1800 /* QAM64 */ 187#define B43_TXH_PHY1_MODUL_QAM256 0x2000 /* QAM256 */ 188 189 190static inline 191size_t b43_txhdr_size(struct b43_wldev *dev) 192{ 193 switch (dev->fw.hdr_format) { 194 case B43_FW_HDR_598: 195 return 112 + sizeof(struct b43_plcp_hdr6); 196 case B43_FW_HDR_410: 197 return 104 + sizeof(struct b43_plcp_hdr6); 198 case B43_FW_HDR_351: 199 return 100 + sizeof(struct b43_plcp_hdr6); 200 } 201 return 0; 202} 203 204 205int b43_generate_txhdr(struct b43_wldev *dev, 206 u8 * txhdr, 207 struct sk_buff *skb_frag, 208 struct ieee80211_tx_info *txctl, u16 cookie); 209 210/* Transmit Status */ 211struct b43_txstatus { 212 u16 cookie; /* The cookie from the txhdr */ 213 u16 seq; /* Sequence number */ 214 u8 phy_stat; /* PHY TX status */ 215 u8 frame_count; /* Frame transmit count */ 216 u8 rts_count; /* RTS transmit count */ 217 u8 supp_reason; /* Suppression reason */ 218 /* flags */ 219 u8 pm_indicated; /* PM mode indicated to AP */ 220 u8 intermediate; /* Intermediate status notification (not final) */ 221 u8 for_ampdu; /* Status is for an AMPDU (afterburner) */ 222 u8 acked; /* Wireless ACK received */ 223}; 224 225/* txstatus supp_reason values */ 226enum { 227 B43_TXST_SUPP_NONE, /* Not suppressed */ 228 B43_TXST_SUPP_PMQ, /* Suppressed due to PMQ entry */ 229 B43_TXST_SUPP_FLUSH, /* Suppressed due to flush request */ 230 B43_TXST_SUPP_PREV, /* Previous fragment failed */ 231 B43_TXST_SUPP_CHAN, /* Channel mismatch */ 232 B43_TXST_SUPP_LIFE, /* Lifetime expired */ 233 B43_TXST_SUPP_UNDER, /* Buffer underflow */ 234 B43_TXST_SUPP_ABNACK, /* Afterburner NACK */ 235}; 236 237/* Receive header for v4 firmware. */ 238struct b43_rxhdr_fw4 { 239 __le16 frame_len; /* Frame length */ 240 PAD_BYTES(2); 241 __le16 phy_status0; /* PHY RX Status 0 */ 242 union { 243 /* RSSI for A/B/G-PHYs */ 244 struct { 245 __u8 jssi; /* PHY RX Status 1: JSSI */ 246 __u8 sig_qual; /* PHY RX Status 1: Signal Quality */ 247 } __packed; 248 249 /* RSSI for N-PHYs */ 250 struct { 251 __s8 power0; /* PHY RX Status 1: Power 0 */ 252 __s8 power1; /* PHY RX Status 1: Power 1 */ 253 } __packed; 254 } __packed; 255 union { 256 /* HT-PHY */ 257 struct { 258 PAD_BYTES(1); 259 __s8 phy_ht_power0; 260 } __packed; 261 262 /* RSSI for N-PHYs */ 263 struct { 264 __s8 power2; 265 PAD_BYTES(1); 266 } __packed; 267 268 __le16 phy_status2; /* PHY RX Status 2 */ 269 } __packed; 270 union { 271 /* HT-PHY */ 272 struct { 273 __s8 phy_ht_power1; 274 __s8 phy_ht_power2; 275 } __packed; 276 277 __le16 phy_status3; /* PHY RX Status 3 */ 278 } __packed; 279 union { 280 /* Tested with 598.314, 644.1001 and 666.2 */ 281 struct { 282 __le16 phy_status4; /* PHY RX Status 4 */ 283 __le16 phy_status5; /* PHY RX Status 5 */ 284 __le32 mac_status; /* MAC RX status */ 285 __le16 mac_time; 286 __le16 channel; 287 } format_598 __packed; 288 289 /* Tested with 351.126, 410.2160, 478.104 and 508.* */ 290 struct { 291 __le32 mac_status; /* MAC RX status */ 292 __le16 mac_time; 293 __le16 channel; 294 } format_351 __packed; 295 } __packed; 296} __packed; 297 298/* PHY RX Status 0 */ 299#define B43_RX_PHYST0_GAINCTL 0x4000 /* Gain Control */ 300#define B43_RX_PHYST0_PLCPHCF 0x0200 301#define B43_RX_PHYST0_PLCPFV 0x0100 302#define B43_RX_PHYST0_SHORTPRMBL 0x0080 /* Received with Short Preamble */ 303#define B43_RX_PHYST0_LCRS 0x0040 304#define B43_RX_PHYST0_ANT 0x0020 /* Antenna */ 305#define B43_RX_PHYST0_UNSRATE 0x0010 306#define B43_RX_PHYST0_CLIP 0x000C 307#define B43_RX_PHYST0_CLIP_SHIFT 2 308#define B43_RX_PHYST0_FTYPE 0x0003 /* Frame type */ 309#define B43_RX_PHYST0_CCK 0x0000 /* Frame type: CCK */ 310#define B43_RX_PHYST0_OFDM 0x0001 /* Frame type: OFDM */ 311#define B43_RX_PHYST0_PRE_N 0x0002 /* Pre-standard N-PHY frame */ 312#define B43_RX_PHYST0_STD_N 0x0003 /* Standard N-PHY frame */ 313 314/* PHY RX Status 2 */ 315#define B43_RX_PHYST2_LNAG 0xC000 /* LNA Gain */ 316#define B43_RX_PHYST2_LNAG_SHIFT 14 317#define B43_RX_PHYST2_PNAG 0x3C00 /* PNA Gain */ 318#define B43_RX_PHYST2_PNAG_SHIFT 10 319#define B43_RX_PHYST2_FOFF 0x03FF /* F offset */ 320 321/* PHY RX Status 3 */ 322#define B43_RX_PHYST3_DIGG 0x1800 /* DIG Gain */ 323#define B43_RX_PHYST3_DIGG_SHIFT 11 324#define B43_RX_PHYST3_TRSTATE 0x0400 /* TR state */ 325 326/* MAC RX Status */ 327#define B43_RX_MAC_RXST_VALID 0x01000000 /* PHY RXST valid */ 328#define B43_RX_MAC_TKIP_MICERR 0x00100000 /* TKIP MIC error */ 329#define B43_RX_MAC_TKIP_MICATT 0x00080000 /* TKIP MIC attempted */ 330#define B43_RX_MAC_AGGTYPE 0x00060000 /* Aggregation type */ 331#define B43_RX_MAC_AGGTYPE_SHIFT 17 332#define B43_RX_MAC_AMSDU 0x00010000 /* A-MSDU mask */ 333#define B43_RX_MAC_BEACONSENT 0x00008000 /* Beacon sent flag */ 334#define B43_RX_MAC_KEYIDX 0x000007E0 /* Key index */ 335#define B43_RX_MAC_KEYIDX_SHIFT 5 336#define B43_RX_MAC_DECERR 0x00000010 /* Decrypt error */ 337#define B43_RX_MAC_DEC 0x00000008 /* Decryption attempted */ 338#define B43_RX_MAC_PADDING 0x00000004 /* Pad bytes present */ 339#define B43_RX_MAC_RESP 0x00000002 /* Response frame transmitted */ 340#define B43_RX_MAC_FCSERR 0x00000001 /* FCS error */ 341 342/* RX channel */ 343#define B43_RX_CHAN_40MHZ 0x1000 /* 40 Mhz channel width */ 344#define B43_RX_CHAN_5GHZ 0x0800 /* 5 Ghz band */ 345#define B43_RX_CHAN_ID 0x07F8 /* Channel ID */ 346#define B43_RX_CHAN_ID_SHIFT 3 347#define B43_RX_CHAN_PHYTYPE 0x0007 /* PHY type */ 348 349 350u8 b43_plcp_get_ratecode_cck(const u8 bitrate); 351u8 b43_plcp_get_ratecode_ofdm(const u8 bitrate); 352 353void b43_generate_plcp_hdr(struct b43_plcp_hdr4 *plcp, 354 const u16 octets, const u8 bitrate); 355 356void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr); 357 358void b43_handle_txstatus(struct b43_wldev *dev, 359 const struct b43_txstatus *status); 360bool b43_fill_txstatus_report(struct b43_wldev *dev, 361 struct ieee80211_tx_info *report, 362 const struct b43_txstatus *status); 363 364void b43_tx_suspend(struct b43_wldev *dev); 365void b43_tx_resume(struct b43_wldev *dev); 366 367 368/* Helper functions for converting the key-table index from "firmware-format" 369 * to "raw-format" and back. The firmware API changed for this at some revision. 370 * We need to account for that here. */ 371static inline int b43_new_kidx_api(struct b43_wldev *dev) 372{ 373 /* FIXME: Not sure the change was at rev 351 */ 374 return (dev->fw.rev >= 351); 375} 376static inline u8 b43_kidx_to_fw(struct b43_wldev *dev, u8 raw_kidx) 377{ 378 u8 firmware_kidx; 379 if (b43_new_kidx_api(dev)) { 380 firmware_kidx = raw_kidx; 381 } else { 382 if (raw_kidx >= 4) /* Is per STA key? */ 383 firmware_kidx = raw_kidx - 4; 384 else 385 firmware_kidx = raw_kidx; /* TX default key */ 386 } 387 return firmware_kidx; 388} 389static inline u8 b43_kidx_to_raw(struct b43_wldev *dev, u8 firmware_kidx) 390{ 391 u8 raw_kidx; 392 if (b43_new_kidx_api(dev)) 393 raw_kidx = firmware_kidx; 394 else 395 raw_kidx = firmware_kidx + 4; /* RX default keys or per STA keys */ 396 return raw_kidx; 397} 398 399/* struct b43_private_tx_info - TX info private to b43. 400 * The structure is placed in (struct ieee80211_tx_info *)->rate_driver_data 401 * 402 * @bouncebuffer: DMA Bouncebuffer (if used) 403 */ 404struct b43_private_tx_info { 405 void *bouncebuffer; 406}; 407 408static inline struct b43_private_tx_info * 409b43_get_priv_tx_info(struct ieee80211_tx_info *info) 410{ 411 BUILD_BUG_ON(sizeof(struct b43_private_tx_info) > 412 sizeof(info->rate_driver_data)); 413 return (struct b43_private_tx_info *)info->rate_driver_data; 414} 415 416#endif /* B43_XMIT_H_ */ 417