1/******************************************************************************
2 *
3 * Copyright(c) 2009-2014  Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __RTL92E_PWRSEQ_H__
27#define __RTL92E_PWRSEQ_H__
28
29#include "../pwrseqcmd.h"
30/**
31 *	Check document WM-20110607-Paul-RTL8192E_Power_Architecture-R02.vsd
32 *	There are 6 HW Power States:
33 *	0: POFF--Power Off
34 *	1: PDN--Power Down
35 *	2: CARDEMU--Card Emulation
36 *	3: ACT--Active Mode
37 *	4: LPS--Low Power State
38 *	5: SUS--Suspend
39 *
40 *	The transision from different states are defined below
41 *	TRANS_CARDEMU_TO_ACT
42 *	TRANS_ACT_TO_CARDEMU
43 *	TRANS_CARDEMU_TO_SUS
44 *	TRANS_SUS_TO_CARDEMU
45 *	TRANS_CARDEMU_TO_PDN
46 *	TRANS_ACT_TO_LPS
47 *	TRANS_LPS_TO_ACT
48 *
49 *	TRANS_END
50 *	PWR SEQ Version: rtl8192E_PwrSeq_V09.h
51 */
52
53#define	RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS	18
54#define	RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS	18
55#define	RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS	18
56#define	RTL8192E_TRANS_SUS_TO_CARDEMU_STEPS	18
57#define	RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS	18
58#define	RTL8192E_TRANS_PDN_TO_CARDEMU_STEPS	18
59#define	RTL8192E_TRANS_ACT_TO_LPS_STEPS		23
60#define	RTL8192E_TRANS_LPS_TO_ACT_STEPS		23
61#define	RTL8192E_TRANS_END_STEPS		1
62
63#define RTL8192E_TRANS_CARDEMU_TO_ACT					\
64	/* format */							\
65	/* comments here */						\
66	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
67	/* disable HWPDN 0x04[15]=0*/					\
68	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
69	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0},			\
70	/* disable SW LPS 0x04[10]=0*/					\
71	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
72	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), 0},			\
73	/* disable WL suspend*/						\
74	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
75	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0},		\
76	/* wait till 0x04[17] = 1    power ready*/			\
77	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
78	 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(1), BIT(1)},		\
79	/* release WLON reset  0x04[16]=1*/				\
80	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
81	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)},		\
82	/* polling until return 0*/					\
83	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
84	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)},		\
85	/**/								\
86	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
87	 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(0), 0},
88
89#define RTL8192E_TRANS_ACT_TO_CARDEMU					\
90	/* format */							\
91	/* comments here */						\
92	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
93	/*0x1F[7:0] = 0 turn off RF*/					\
94	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
95	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0},			\
96	/*0x4C[23]=0x4E[7]=0, switch DPDT_SEL_P output from register 0x65[2] */\
97	{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
98	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0},			\
99	/*0x04[9] = 1 turn off MAC by HW state machine*/		\
100	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
101	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), BIT(1)},		\
102	/*wait till 0x04[9] = 0 polling until return 0 to disable*/	\
103	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
104	 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(1), 0},
105
106#define RTL8192E_TRANS_CARDEMU_TO_SUS					\
107	/* format */							\
108	/* comments here */						\
109	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
110	/*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/		\
111	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,	\
112	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))},\
113	/*0x04[12:11] = 2b'01 enable WL suspend*/			\
114	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,			\
115	 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC,	\
116	 PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)},				\
117	/*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/		\
118	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,	\
119	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},\
120	/*Set SDIO suspend local register*/				\
121	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
122	 PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), BIT(0)},		\
123	 /*wait power state to suspend*/				\
124	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
125	 PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), 0},
126
127#define RTL8192E_TRANS_SUS_TO_CARDEMU					\
128	/* format */							\
129	/* comments here */						\
130	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
131	/*Set SDIO suspend local register*/				\
132	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
133	 PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), 0},			\
134	/*wait power state to suspend*/					\
135	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
136	 PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), BIT(1)},		\
137	/*0x04[12:11] = 2b'01enable WL suspend*/			\
138	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
139	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
140
141#define RTL8192E_TRANS_CARDEMU_TO_CARDDIS				\
142	/* format */							\
143	/* comments here */						\
144	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
145	/*0x07=0x20 , SOP option to disable BG/MB*/			\
146	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
147	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x20},			\
148	/*Unlock small LDO Register*/					\
149	{0x00CC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
150	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), BIT(2)},		\
151	/*Disable small LDO*/						\
152	{0x0011, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
153	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0},			\
154	/*0x04[12:11] = 2b'01 enable WL suspend*/			\
155	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,			\
156	 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC,		\
157	 PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)},				\
158	/*0x04[10] = 1, enable SW LPS*/					\
159	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,	\
160	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), BIT(2)},		\
161	/*Set SDIO suspend local register*/				\
162	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
163	 PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), BIT(0)},		\
164	/*wait power state to suspend*/					\
165	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
166	 PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), 0},
167
168#define RTL8192E_TRANS_CARDDIS_TO_CARDEMU				\
169	/* format */							\
170	/* comments here */						\
171	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
172	/*Set SDIO suspend local register*/				\
173	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
174	 PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), 0},			\
175	/*wait power state to suspend*/					\
176	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
177	 PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), BIT(1)},		\
178	/*Enable small LDO*/						\
179	{0x0011, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
180	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)},		\
181	/*Lock small LDO Register*/					\
182	{0x00CC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
183	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), 0},			\
184	/*0x04[12:11] = 2b'01enable WL suspend*/			\
185	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
186	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
187
188#define RTL8192E_TRANS_CARDEMU_TO_PDN					\
189	/* format */							\
190	/* comments here */						\
191	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
192	/* 0x04[16] = 0*/						\
193	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
194	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0},			\
195	/* 0x04[15] = 1*/						\
196	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
197	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), BIT(7)},
198
199#define RTL8192E_TRANS_PDN_TO_CARDEMU					\
200	/* format */							\
201	/* comments here */						\
202	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
203	/* 0x04[15] = 0*/						\
204	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
205	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0},
206
207#define RTL8192E_TRANS_ACT_TO_LPS					\
208	/* format */							\
209	/* comments here */						\
210	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
211	/*PCIe DMA stop*/						\
212	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,	\
213	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF},			\
214	/*Tx Pause*/							\
215	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
216	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF},			\
217	/*Should be zero if no packet is transmitting*/			\
218	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
219	 PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0},			\
220	/*Should be zero if no packet is transmitting*/			\
221	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
222	 PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0},			\
223	/*Should be zero if no packet is transmitting*/			\
224	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
225	 PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0},			\
226	/*Should be zero if no packet is transmitting*/			\
227	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
228	 PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0},			\
229	/*CCK and OFDM are disabled,and clock are gated*/		\
230	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
231	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0},			\
232	/*Delay 1us*/							\
233	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
234	 PWR_BASEADDR_MAC , PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},		\
235	/*Whole BB is reset*/						\
236	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
237	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), 0},			\
238	/*Reset MAC TRX*/						\
239	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
240	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x03},			\
241	/*check if removed later*/					\
242	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
243	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), 0},			\
244	/*When driver enter Sus/ Disable, enable LOP for BT*/		\
245	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
246	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x00},			\
247	/*Respond TxOK to scheduler*/					\
248	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
249	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(5), BIT(5)},
250
251#define RTL8192E_TRANS_LPS_TO_ACT					\
252	/* format */							\
253	/* comments here */						\
254	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
255	/*SDIO RPWM, For Repeatly In and out, Taggle bit should be changed*/\
256	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
257	 PWR_BASEADDR_SDIO , PWR_CMD_WRITE, 0xFF, 0x84},		\
258	/*USB RPWM*/							\
259	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,	\
260	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x84},			\
261	/*PCIe RPWM*/							\
262	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,	\
263	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x84},			\
264	/*Delay*/							\
265	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
266	 PWR_BASEADDR_MAC , PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS},		\
267	/*0x08[4] = 0 switch TSF to 40M*/				\
268	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
269	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(4), 0},			\
270	/*Polling 0x109[7]=0  TSF in 40M*/				\
271	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
272	 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(7), 0},		\
273	/*0x101[1] = 1*/						\
274	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
275	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), BIT(1)},		\
276	/*0x100[7:0] = 0xFF  enable WMAC TRX*/				\
277	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
278	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF},			\
279	/* 0x02[1:0] = 2b'11 enable BB macro*/				\
280	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
281	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)},\
282	/*0x522 = 0*/							\
283	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
284	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0},			\
285	/*Clear ISR*/							\
286	{0x013D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
287	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF},
288
289#define RTL8192E_TRANS_END						\
290	/* format */							\
291	/* comments here */						\
292	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
293	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
294	 0, PWR_CMD_END, 0, 0},
295
296extern struct wlan_pwr_cfg rtl8192E_power_on_flow
297					[RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS +
298					 RTL8192E_TRANS_END_STEPS];
299extern struct wlan_pwr_cfg rtl8192E_radio_off_flow
300					[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
301					 RTL8192E_TRANS_END_STEPS];
302extern struct wlan_pwr_cfg rtl8192E_card_disable_flow
303					[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
304					 RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
305					 RTL8192E_TRANS_END_STEPS];
306extern struct wlan_pwr_cfg rtl8192E_card_enable_flow
307					[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
308					 RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
309					 RTL8192E_TRANS_END_STEPS];
310extern struct wlan_pwr_cfg rtl8192E_suspend_flow
311					[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
312					 RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS +
313					 RTL8192E_TRANS_END_STEPS];
314extern struct wlan_pwr_cfg rtl8192E_resume_flow
315					[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
316					 RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS +
317					 RTL8192E_TRANS_END_STEPS];
318extern struct wlan_pwr_cfg rtl8192E_hwpdn_flow
319					[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
320					 RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
321					 RTL8192E_TRANS_END_STEPS];
322extern struct wlan_pwr_cfg rtl8192E_enter_lps_flow
323					[RTL8192E_TRANS_ACT_TO_LPS_STEPS +
324					 RTL8192E_TRANS_END_STEPS];
325extern struct wlan_pwr_cfg rtl8192E_leave_lps_flow
326					[RTL8192E_TRANS_LPS_TO_ACT_STEPS +
327					 RTL8192E_TRANS_END_STEPS];
328
329/* RTL8192EE Power Configuration CMDs for PCIe interface */
330#define RTL8192E_NIC_PWR_ON_FLOW	rtl8192E_power_on_flow
331#define RTL8192E_NIC_RF_OFF_FLOW	rtl8192E_radio_off_flow
332#define RTL8192E_NIC_DISABLE_FLOW	rtl8192E_card_disable_flow
333#define RTL8192E_NIC_ENABLE_FLOW	rtl8192E_card_enable_flow
334#define RTL8192E_NIC_SUSPEND_FLOW	rtl8192E_suspend_flow
335#define RTL8192E_NIC_RESUME_FLOW	rtl8192E_resume_flow
336#define RTL8192E_NIC_PDN_FLOW		rtl8192E_hwpdn_flow
337#define RTL8192E_NIC_LPS_ENTER_FLOW	rtl8192E_enter_lps_flow
338#define RTL8192E_NIC_LPS_LEAVE_FLOW	rtl8192E_leave_lps_flow
339
340#endif
341