1/* 2 * Driver for Broadcom BCM2835 SPI Controllers 3 * 4 * Copyright (C) 2012 Chris Boot 5 * Copyright (C) 2013 Stephen Warren 6 * Copyright (C) 2015 Martin Sperl 7 * 8 * This driver is inspired by: 9 * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org> 10 * spi-atmel.c, Copyright (C) 2006 Atmel Corporation 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 */ 22 23#include <linux/clk.h> 24#include <linux/completion.h> 25#include <linux/delay.h> 26#include <linux/err.h> 27#include <linux/interrupt.h> 28#include <linux/io.h> 29#include <linux/kernel.h> 30#include <linux/module.h> 31#include <linux/of.h> 32#include <linux/of_irq.h> 33#include <linux/of_gpio.h> 34#include <linux/of_device.h> 35#include <linux/spi/spi.h> 36 37/* SPI register offsets */ 38#define BCM2835_SPI_CS 0x00 39#define BCM2835_SPI_FIFO 0x04 40#define BCM2835_SPI_CLK 0x08 41#define BCM2835_SPI_DLEN 0x0c 42#define BCM2835_SPI_LTOH 0x10 43#define BCM2835_SPI_DC 0x14 44 45/* Bitfields in CS */ 46#define BCM2835_SPI_CS_LEN_LONG 0x02000000 47#define BCM2835_SPI_CS_DMA_LEN 0x01000000 48#define BCM2835_SPI_CS_CSPOL2 0x00800000 49#define BCM2835_SPI_CS_CSPOL1 0x00400000 50#define BCM2835_SPI_CS_CSPOL0 0x00200000 51#define BCM2835_SPI_CS_RXF 0x00100000 52#define BCM2835_SPI_CS_RXR 0x00080000 53#define BCM2835_SPI_CS_TXD 0x00040000 54#define BCM2835_SPI_CS_RXD 0x00020000 55#define BCM2835_SPI_CS_DONE 0x00010000 56#define BCM2835_SPI_CS_LEN 0x00002000 57#define BCM2835_SPI_CS_REN 0x00001000 58#define BCM2835_SPI_CS_ADCS 0x00000800 59#define BCM2835_SPI_CS_INTR 0x00000400 60#define BCM2835_SPI_CS_INTD 0x00000200 61#define BCM2835_SPI_CS_DMAEN 0x00000100 62#define BCM2835_SPI_CS_TA 0x00000080 63#define BCM2835_SPI_CS_CSPOL 0x00000040 64#define BCM2835_SPI_CS_CLEAR_RX 0x00000020 65#define BCM2835_SPI_CS_CLEAR_TX 0x00000010 66#define BCM2835_SPI_CS_CPOL 0x00000008 67#define BCM2835_SPI_CS_CPHA 0x00000004 68#define BCM2835_SPI_CS_CS_10 0x00000002 69#define BCM2835_SPI_CS_CS_01 0x00000001 70 71#define BCM2835_SPI_POLLING_LIMIT_US 30 72#define BCM2835_SPI_TIMEOUT_MS 30000 73#define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \ 74 | SPI_NO_CS | SPI_3WIRE) 75 76#define DRV_NAME "spi-bcm2835" 77 78struct bcm2835_spi { 79 void __iomem *regs; 80 struct clk *clk; 81 int irq; 82 const u8 *tx_buf; 83 u8 *rx_buf; 84 int tx_len; 85 int rx_len; 86}; 87 88static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg) 89{ 90 return readl(bs->regs + reg); 91} 92 93static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned reg, u32 val) 94{ 95 writel(val, bs->regs + reg); 96} 97 98static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs) 99{ 100 u8 byte; 101 102 while ((bs->rx_len) && 103 (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD)) { 104 byte = bcm2835_rd(bs, BCM2835_SPI_FIFO); 105 if (bs->rx_buf) 106 *bs->rx_buf++ = byte; 107 bs->rx_len--; 108 } 109} 110 111static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs) 112{ 113 u8 byte; 114 115 while ((bs->tx_len) && 116 (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD)) { 117 byte = bs->tx_buf ? *bs->tx_buf++ : 0; 118 bcm2835_wr(bs, BCM2835_SPI_FIFO, byte); 119 bs->tx_len--; 120 } 121} 122 123static void bcm2835_spi_reset_hw(struct spi_master *master) 124{ 125 struct bcm2835_spi *bs = spi_master_get_devdata(master); 126 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); 127 128 /* Disable SPI interrupts and transfer */ 129 cs &= ~(BCM2835_SPI_CS_INTR | 130 BCM2835_SPI_CS_INTD | 131 BCM2835_SPI_CS_TA); 132 /* and reset RX/TX FIFOS */ 133 cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX; 134 135 /* and reset the SPI_HW */ 136 bcm2835_wr(bs, BCM2835_SPI_CS, cs); 137} 138 139static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id) 140{ 141 struct spi_master *master = dev_id; 142 struct bcm2835_spi *bs = spi_master_get_devdata(master); 143 144 /* Read as many bytes as possible from FIFO */ 145 bcm2835_rd_fifo(bs); 146 /* Write as many bytes as possible to FIFO */ 147 bcm2835_wr_fifo(bs); 148 149 /* based on flags decide if we can finish the transfer */ 150 if (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE) { 151 /* Transfer complete - reset SPI HW */ 152 bcm2835_spi_reset_hw(master); 153 /* wake up the framework */ 154 complete(&master->xfer_completion); 155 } 156 157 return IRQ_HANDLED; 158} 159 160static int bcm2835_spi_transfer_one_poll(struct spi_master *master, 161 struct spi_device *spi, 162 struct spi_transfer *tfr, 163 u32 cs, 164 unsigned long xfer_time_us) 165{ 166 struct bcm2835_spi *bs = spi_master_get_devdata(master); 167 /* set timeout to 1 second of maximum polling */ 168 unsigned long timeout = jiffies + HZ; 169 170 /* enable HW block without interrupts */ 171 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA); 172 173 /* loop until finished the transfer */ 174 while (bs->rx_len) { 175 /* read from fifo as much as possible */ 176 bcm2835_rd_fifo(bs); 177 /* fill in tx fifo as much as possible */ 178 bcm2835_wr_fifo(bs); 179 /* if we still expect some data after the read, 180 * check for a possible timeout 181 */ 182 if (bs->rx_len && time_after(jiffies, timeout)) { 183 /* Transfer complete - reset SPI HW */ 184 bcm2835_spi_reset_hw(master); 185 /* and return timeout */ 186 return -ETIMEDOUT; 187 } 188 } 189 190 /* Transfer complete - reset SPI HW */ 191 bcm2835_spi_reset_hw(master); 192 /* and return without waiting for completion */ 193 return 0; 194} 195 196static int bcm2835_spi_transfer_one_irq(struct spi_master *master, 197 struct spi_device *spi, 198 struct spi_transfer *tfr, 199 u32 cs) 200{ 201 struct bcm2835_spi *bs = spi_master_get_devdata(master); 202 203 /* fill in fifo if we have gpio-cs 204 * note that there have been rare events where the native-CS 205 * flapped for <1us which may change the behaviour 206 * with gpio-cs this does not happen, so it is implemented 207 * only for this case 208 */ 209 if (gpio_is_valid(spi->cs_gpio)) { 210 /* enable HW block, but without interrupts enabled 211 * this would triggern an immediate interrupt 212 */ 213 bcm2835_wr(bs, BCM2835_SPI_CS, 214 cs | BCM2835_SPI_CS_TA); 215 /* fill in tx fifo as much as possible */ 216 bcm2835_wr_fifo(bs); 217 } 218 219 /* 220 * Enable the HW block. This will immediately trigger a DONE (TX 221 * empty) interrupt, upon which we will fill the TX FIFO with the 222 * first TX bytes. Pre-filling the TX FIFO here to avoid the 223 * interrupt doesn't work:-( 224 */ 225 cs |= BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA; 226 bcm2835_wr(bs, BCM2835_SPI_CS, cs); 227 228 /* signal that we need to wait for completion */ 229 return 1; 230} 231 232static int bcm2835_spi_transfer_one(struct spi_master *master, 233 struct spi_device *spi, 234 struct spi_transfer *tfr) 235{ 236 struct bcm2835_spi *bs = spi_master_get_devdata(master); 237 unsigned long spi_hz, clk_hz, cdiv; 238 unsigned long spi_used_hz, xfer_time_us; 239 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); 240 241 /* set clock */ 242 spi_hz = tfr->speed_hz; 243 clk_hz = clk_get_rate(bs->clk); 244 245 if (spi_hz >= clk_hz / 2) { 246 cdiv = 2; /* clk_hz/2 is the fastest we can go */ 247 } else if (spi_hz) { 248 /* CDIV must be a multiple of two */ 249 cdiv = DIV_ROUND_UP(clk_hz, spi_hz); 250 cdiv += (cdiv % 2); 251 252 if (cdiv >= 65536) 253 cdiv = 0; /* 0 is the slowest we can go */ 254 } else { 255 cdiv = 0; /* 0 is the slowest we can go */ 256 } 257 spi_used_hz = cdiv ? (clk_hz / cdiv) : (clk_hz / 65536); 258 bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv); 259 260 /* handle all the 3-wire mode */ 261 if ((spi->mode & SPI_3WIRE) && (tfr->rx_buf)) 262 cs |= BCM2835_SPI_CS_REN; 263 else 264 cs &= ~BCM2835_SPI_CS_REN; 265 266 /* for gpio_cs set dummy CS so that no HW-CS get changed 267 * we can not run this in bcm2835_spi_set_cs, as it does 268 * not get called for cs_gpio cases, so we need to do it here 269 */ 270 if (gpio_is_valid(spi->cs_gpio) || (spi->mode & SPI_NO_CS)) 271 cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01; 272 273 /* set transmit buffers and length */ 274 bs->tx_buf = tfr->tx_buf; 275 bs->rx_buf = tfr->rx_buf; 276 bs->tx_len = tfr->len; 277 bs->rx_len = tfr->len; 278 279 /* calculate the estimated time in us the transfer runs */ 280 xfer_time_us = tfr->len 281 * 9 /* clocks/byte - SPI-HW waits 1 clock after each byte */ 282 * 1000000 / spi_used_hz; 283 284 /* for short requests run polling*/ 285 if (xfer_time_us <= BCM2835_SPI_POLLING_LIMIT_US) 286 return bcm2835_spi_transfer_one_poll(master, spi, tfr, 287 cs, xfer_time_us); 288 289 return bcm2835_spi_transfer_one_irq(master, spi, tfr, cs); 290} 291 292static int bcm2835_spi_prepare_message(struct spi_master *master, 293 struct spi_message *msg) 294{ 295 struct spi_device *spi = msg->spi; 296 struct bcm2835_spi *bs = spi_master_get_devdata(master); 297 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); 298 299 cs &= ~(BCM2835_SPI_CS_CPOL | BCM2835_SPI_CS_CPHA); 300 301 if (spi->mode & SPI_CPOL) 302 cs |= BCM2835_SPI_CS_CPOL; 303 if (spi->mode & SPI_CPHA) 304 cs |= BCM2835_SPI_CS_CPHA; 305 306 bcm2835_wr(bs, BCM2835_SPI_CS, cs); 307 308 return 0; 309} 310 311static void bcm2835_spi_handle_err(struct spi_master *master, 312 struct spi_message *msg) 313{ 314 bcm2835_spi_reset_hw(master); 315} 316 317static void bcm2835_spi_set_cs(struct spi_device *spi, bool gpio_level) 318{ 319 /* 320 * we can assume that we are "native" as per spi_set_cs 321 * calling us ONLY when cs_gpio is not set 322 * we can also assume that we are CS < 3 as per bcm2835_spi_setup 323 * we would not get called because of error handling there. 324 * the level passed is the electrical level not enabled/disabled 325 * so it has to get translated back to enable/disable 326 * see spi_set_cs in spi.c for the implementation 327 */ 328 329 struct spi_master *master = spi->master; 330 struct bcm2835_spi *bs = spi_master_get_devdata(master); 331 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); 332 bool enable; 333 334 /* calculate the enable flag from the passed gpio_level */ 335 enable = (spi->mode & SPI_CS_HIGH) ? gpio_level : !gpio_level; 336 337 /* set flags for "reverse" polarity in the registers */ 338 if (spi->mode & SPI_CS_HIGH) { 339 /* set the correct CS-bits */ 340 cs |= BCM2835_SPI_CS_CSPOL; 341 cs |= BCM2835_SPI_CS_CSPOL0 << spi->chip_select; 342 } else { 343 /* clean the CS-bits */ 344 cs &= ~BCM2835_SPI_CS_CSPOL; 345 cs &= ~(BCM2835_SPI_CS_CSPOL0 << spi->chip_select); 346 } 347 348 /* select the correct chip_select depending on disabled/enabled */ 349 if (enable) { 350 /* set cs correctly */ 351 if (spi->mode & SPI_NO_CS) { 352 /* use the "undefined" chip-select */ 353 cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01; 354 } else { 355 /* set the chip select */ 356 cs &= ~(BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01); 357 cs |= spi->chip_select; 358 } 359 } else { 360 /* disable CSPOL which puts HW-CS into deselected state */ 361 cs &= ~BCM2835_SPI_CS_CSPOL; 362 /* use the "undefined" chip-select as precaution */ 363 cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01; 364 } 365 366 /* finally set the calculated flags in SPI_CS */ 367 bcm2835_wr(bs, BCM2835_SPI_CS, cs); 368} 369 370static int chip_match_name(struct gpio_chip *chip, void *data) 371{ 372 return !strcmp(chip->label, data); 373} 374 375static int bcm2835_spi_setup(struct spi_device *spi) 376{ 377 int err; 378 struct gpio_chip *chip; 379 /* 380 * sanity checking the native-chipselects 381 */ 382 if (spi->mode & SPI_NO_CS) 383 return 0; 384 if (gpio_is_valid(spi->cs_gpio)) 385 return 0; 386 if (spi->chip_select > 1) { 387 /* error in the case of native CS requested with CS > 1 388 * officially there is a CS2, but it is not documented 389 * which GPIO is connected with that... 390 */ 391 dev_err(&spi->dev, 392 "setup: only two native chip-selects are supported\n"); 393 return -EINVAL; 394 } 395 /* now translate native cs to GPIO */ 396 397 /* get the gpio chip for the base */ 398 chip = gpiochip_find("pinctrl-bcm2835", chip_match_name); 399 if (!chip) 400 return 0; 401 402 /* and calculate the real CS */ 403 spi->cs_gpio = chip->base + 8 - spi->chip_select; 404 405 /* and set up the "mode" and level */ 406 dev_info(&spi->dev, "setting up native-CS%i as GPIO %i\n", 407 spi->chip_select, spi->cs_gpio); 408 409 /* set up GPIO as output and pull to the correct level */ 410 err = gpio_direction_output(spi->cs_gpio, 411 (spi->mode & SPI_CS_HIGH) ? 0 : 1); 412 if (err) { 413 dev_err(&spi->dev, 414 "could not set CS%i gpio %i as output: %i", 415 spi->chip_select, spi->cs_gpio, err); 416 return err; 417 } 418 /* the implementation of pinctrl-bcm2835 currently does not 419 * set the GPIO value when using gpio_direction_output 420 * so we are setting it here explicitly 421 */ 422 gpio_set_value(spi->cs_gpio, (spi->mode & SPI_CS_HIGH) ? 0 : 1); 423 424 return 0; 425} 426 427static int bcm2835_spi_probe(struct platform_device *pdev) 428{ 429 struct spi_master *master; 430 struct bcm2835_spi *bs; 431 struct resource *res; 432 int err; 433 434 master = spi_alloc_master(&pdev->dev, sizeof(*bs)); 435 if (!master) { 436 dev_err(&pdev->dev, "spi_alloc_master() failed\n"); 437 return -ENOMEM; 438 } 439 440 platform_set_drvdata(pdev, master); 441 442 master->mode_bits = BCM2835_SPI_MODE_BITS; 443 master->bits_per_word_mask = SPI_BPW_MASK(8); 444 master->num_chipselect = 3; 445 master->setup = bcm2835_spi_setup; 446 master->set_cs = bcm2835_spi_set_cs; 447 master->transfer_one = bcm2835_spi_transfer_one; 448 master->handle_err = bcm2835_spi_handle_err; 449 master->prepare_message = bcm2835_spi_prepare_message; 450 master->dev.of_node = pdev->dev.of_node; 451 452 bs = spi_master_get_devdata(master); 453 454 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 455 bs->regs = devm_ioremap_resource(&pdev->dev, res); 456 if (IS_ERR(bs->regs)) { 457 err = PTR_ERR(bs->regs); 458 goto out_master_put; 459 } 460 461 bs->clk = devm_clk_get(&pdev->dev, NULL); 462 if (IS_ERR(bs->clk)) { 463 err = PTR_ERR(bs->clk); 464 dev_err(&pdev->dev, "could not get clk: %d\n", err); 465 goto out_master_put; 466 } 467 468 bs->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 469 if (bs->irq <= 0) { 470 dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq); 471 err = bs->irq ? bs->irq : -ENODEV; 472 goto out_master_put; 473 } 474 475 clk_prepare_enable(bs->clk); 476 477 err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0, 478 dev_name(&pdev->dev), master); 479 if (err) { 480 dev_err(&pdev->dev, "could not request IRQ: %d\n", err); 481 goto out_clk_disable; 482 } 483 484 /* initialise the hardware with the default polarities */ 485 bcm2835_wr(bs, BCM2835_SPI_CS, 486 BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX); 487 488 err = devm_spi_register_master(&pdev->dev, master); 489 if (err) { 490 dev_err(&pdev->dev, "could not register SPI master: %d\n", err); 491 goto out_clk_disable; 492 } 493 494 return 0; 495 496out_clk_disable: 497 clk_disable_unprepare(bs->clk); 498out_master_put: 499 spi_master_put(master); 500 return err; 501} 502 503static int bcm2835_spi_remove(struct platform_device *pdev) 504{ 505 struct spi_master *master = platform_get_drvdata(pdev); 506 struct bcm2835_spi *bs = spi_master_get_devdata(master); 507 508 /* Clear FIFOs, and disable the HW block */ 509 bcm2835_wr(bs, BCM2835_SPI_CS, 510 BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX); 511 512 clk_disable_unprepare(bs->clk); 513 514 return 0; 515} 516 517static const struct of_device_id bcm2835_spi_match[] = { 518 { .compatible = "brcm,bcm2835-spi", }, 519 {} 520}; 521MODULE_DEVICE_TABLE(of, bcm2835_spi_match); 522 523static struct platform_driver bcm2835_spi_driver = { 524 .driver = { 525 .name = DRV_NAME, 526 .of_match_table = bcm2835_spi_match, 527 }, 528 .probe = bcm2835_spi_probe, 529 .remove = bcm2835_spi_remove, 530}; 531module_platform_driver(bcm2835_spi_driver); 532 533MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835"); 534MODULE_AUTHOR("Chris Boot <bootc@bootc.net>"); 535MODULE_LICENSE("GPL v2"); 536