1/* 2 * Freescale eSPI controller driver. 3 * 4 * Copyright 2010 Freescale Semiconductor, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11#include <linux/delay.h> 12#include <linux/err.h> 13#include <linux/fsl_devices.h> 14#include <linux/interrupt.h> 15#include <linux/irq.h> 16#include <linux/module.h> 17#include <linux/mm.h> 18#include <linux/of.h> 19#include <linux/of_address.h> 20#include <linux/of_irq.h> 21#include <linux/of_platform.h> 22#include <linux/platform_device.h> 23#include <linux/spi/spi.h> 24#include <sysdev/fsl_soc.h> 25 26#include "spi-fsl-lib.h" 27 28/* eSPI Controller registers */ 29struct fsl_espi_reg { 30 __be32 mode; /* 0x000 - eSPI mode register */ 31 __be32 event; /* 0x004 - eSPI event register */ 32 __be32 mask; /* 0x008 - eSPI mask register */ 33 __be32 command; /* 0x00c - eSPI command register */ 34 __be32 transmit; /* 0x010 - eSPI transmit FIFO access register*/ 35 __be32 receive; /* 0x014 - eSPI receive FIFO access register*/ 36 u8 res[8]; /* 0x018 - 0x01c reserved */ 37 __be32 csmode[4]; /* 0x020 - 0x02c eSPI cs mode register */ 38}; 39 40struct fsl_espi_transfer { 41 const void *tx_buf; 42 void *rx_buf; 43 unsigned len; 44 unsigned n_tx; 45 unsigned n_rx; 46 unsigned actual_length; 47 int status; 48}; 49 50/* eSPI Controller mode register definitions */ 51#define SPMODE_ENABLE (1 << 31) 52#define SPMODE_LOOP (1 << 30) 53#define SPMODE_TXTHR(x) ((x) << 8) 54#define SPMODE_RXTHR(x) ((x) << 0) 55 56/* eSPI Controller CS mode register definitions */ 57#define CSMODE_CI_INACTIVEHIGH (1 << 31) 58#define CSMODE_CP_BEGIN_EDGECLK (1 << 30) 59#define CSMODE_REV (1 << 29) 60#define CSMODE_DIV16 (1 << 28) 61#define CSMODE_PM(x) ((x) << 24) 62#define CSMODE_POL_1 (1 << 20) 63#define CSMODE_LEN(x) ((x) << 16) 64#define CSMODE_BEF(x) ((x) << 12) 65#define CSMODE_AFT(x) ((x) << 8) 66#define CSMODE_CG(x) ((x) << 3) 67 68/* Default mode/csmode for eSPI controller */ 69#define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3)) 70#define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \ 71 | CSMODE_AFT(0) | CSMODE_CG(1)) 72 73/* SPIE register values */ 74#define SPIE_NE 0x00000200 /* Not empty */ 75#define SPIE_NF 0x00000100 /* Not full */ 76 77/* SPIM register values */ 78#define SPIM_NE 0x00000200 /* Not empty */ 79#define SPIM_NF 0x00000100 /* Not full */ 80#define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F) 81#define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F) 82 83/* SPCOM register values */ 84#define SPCOM_CS(x) ((x) << 30) 85#define SPCOM_TRANLEN(x) ((x) << 0) 86#define SPCOM_TRANLEN_MAX 0xFFFF /* Max transaction length */ 87 88static void fsl_espi_change_mode(struct spi_device *spi) 89{ 90 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); 91 struct spi_mpc8xxx_cs *cs = spi->controller_state; 92 struct fsl_espi_reg *reg_base = mspi->reg_base; 93 __be32 __iomem *mode = ®_base->csmode[spi->chip_select]; 94 __be32 __iomem *espi_mode = ®_base->mode; 95 u32 tmp; 96 unsigned long flags; 97 98 /* Turn off IRQs locally to minimize time that SPI is disabled. */ 99 local_irq_save(flags); 100 101 /* Turn off SPI unit prior changing mode */ 102 tmp = mpc8xxx_spi_read_reg(espi_mode); 103 mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE); 104 mpc8xxx_spi_write_reg(mode, cs->hw_mode); 105 mpc8xxx_spi_write_reg(espi_mode, tmp); 106 107 local_irq_restore(flags); 108} 109 110static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi) 111{ 112 u32 data; 113 u16 data_h; 114 u16 data_l; 115 const u32 *tx = mpc8xxx_spi->tx; 116 117 if (!tx) 118 return 0; 119 120 data = *tx++ << mpc8xxx_spi->tx_shift; 121 data_l = data & 0xffff; 122 data_h = (data >> 16) & 0xffff; 123 swab16s(&data_l); 124 swab16s(&data_h); 125 data = data_h | data_l; 126 127 mpc8xxx_spi->tx = tx; 128 return data; 129} 130 131static int fsl_espi_setup_transfer(struct spi_device *spi, 132 struct spi_transfer *t) 133{ 134 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); 135 int bits_per_word = 0; 136 u8 pm; 137 u32 hz = 0; 138 struct spi_mpc8xxx_cs *cs = spi->controller_state; 139 140 if (t) { 141 bits_per_word = t->bits_per_word; 142 hz = t->speed_hz; 143 } 144 145 /* spi_transfer level calls that work per-word */ 146 if (!bits_per_word) 147 bits_per_word = spi->bits_per_word; 148 149 if (!hz) 150 hz = spi->max_speed_hz; 151 152 cs->rx_shift = 0; 153 cs->tx_shift = 0; 154 cs->get_rx = mpc8xxx_spi_rx_buf_u32; 155 cs->get_tx = mpc8xxx_spi_tx_buf_u32; 156 if (bits_per_word <= 8) { 157 cs->rx_shift = 8 - bits_per_word; 158 } else { 159 cs->rx_shift = 16 - bits_per_word; 160 if (spi->mode & SPI_LSB_FIRST) 161 cs->get_tx = fsl_espi_tx_buf_lsb; 162 } 163 164 mpc8xxx_spi->rx_shift = cs->rx_shift; 165 mpc8xxx_spi->tx_shift = cs->tx_shift; 166 mpc8xxx_spi->get_rx = cs->get_rx; 167 mpc8xxx_spi->get_tx = cs->get_tx; 168 169 bits_per_word = bits_per_word - 1; 170 171 /* mask out bits we are going to set */ 172 cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF)); 173 174 cs->hw_mode |= CSMODE_LEN(bits_per_word); 175 176 if ((mpc8xxx_spi->spibrg / hz) > 64) { 177 cs->hw_mode |= CSMODE_DIV16; 178 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4); 179 180 WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. " 181 "Will use %d Hz instead.\n", dev_name(&spi->dev), 182 hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1))); 183 if (pm > 33) 184 pm = 33; 185 } else { 186 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4); 187 } 188 if (pm) 189 pm--; 190 if (pm < 2) 191 pm = 2; 192 193 cs->hw_mode |= CSMODE_PM(pm); 194 195 fsl_espi_change_mode(spi); 196 return 0; 197} 198 199static int fsl_espi_cpu_bufs(struct mpc8xxx_spi *mspi, struct spi_transfer *t, 200 unsigned int len) 201{ 202 u32 word; 203 struct fsl_espi_reg *reg_base = mspi->reg_base; 204 205 mspi->count = len; 206 207 /* enable rx ints */ 208 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE); 209 210 /* transmit word */ 211 word = mspi->get_tx(mspi); 212 mpc8xxx_spi_write_reg(®_base->transmit, word); 213 214 return 0; 215} 216 217static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t) 218{ 219 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); 220 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base; 221 unsigned int len = t->len; 222 int ret; 223 224 mpc8xxx_spi->len = t->len; 225 len = roundup(len, 4) / 4; 226 227 mpc8xxx_spi->tx = t->tx_buf; 228 mpc8xxx_spi->rx = t->rx_buf; 229 230 reinit_completion(&mpc8xxx_spi->done); 231 232 /* Set SPCOM[CS] and SPCOM[TRANLEN] field */ 233 if ((t->len - 1) > SPCOM_TRANLEN_MAX) { 234 dev_err(mpc8xxx_spi->dev, "Transaction length (%d)" 235 " beyond the SPCOM[TRANLEN] field\n", t->len); 236 return -EINVAL; 237 } 238 mpc8xxx_spi_write_reg(®_base->command, 239 (SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1))); 240 241 ret = fsl_espi_cpu_bufs(mpc8xxx_spi, t, len); 242 if (ret) 243 return ret; 244 245 wait_for_completion(&mpc8xxx_spi->done); 246 247 /* disable rx ints */ 248 mpc8xxx_spi_write_reg(®_base->mask, 0); 249 250 return mpc8xxx_spi->count; 251} 252 253static inline void fsl_espi_addr2cmd(unsigned int addr, u8 *cmd) 254{ 255 if (cmd) { 256 cmd[1] = (u8)(addr >> 16); 257 cmd[2] = (u8)(addr >> 8); 258 cmd[3] = (u8)(addr >> 0); 259 } 260} 261 262static inline unsigned int fsl_espi_cmd2addr(u8 *cmd) 263{ 264 if (cmd) 265 return cmd[1] << 16 | cmd[2] << 8 | cmd[3] << 0; 266 267 return 0; 268} 269 270static void fsl_espi_do_trans(struct spi_message *m, 271 struct fsl_espi_transfer *tr) 272{ 273 struct spi_device *spi = m->spi; 274 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); 275 struct fsl_espi_transfer *espi_trans = tr; 276 struct spi_message message; 277 struct spi_transfer *t, *first, trans; 278 int status = 0; 279 280 spi_message_init(&message); 281 memset(&trans, 0, sizeof(trans)); 282 283 first = list_first_entry(&m->transfers, struct spi_transfer, 284 transfer_list); 285 list_for_each_entry(t, &m->transfers, transfer_list) { 286 if ((first->bits_per_word != t->bits_per_word) || 287 (first->speed_hz != t->speed_hz)) { 288 espi_trans->status = -EINVAL; 289 dev_err(mspi->dev, 290 "bits_per_word/speed_hz should be same for the same SPI transfer\n"); 291 return; 292 } 293 294 trans.speed_hz = t->speed_hz; 295 trans.bits_per_word = t->bits_per_word; 296 trans.delay_usecs = max(first->delay_usecs, t->delay_usecs); 297 } 298 299 trans.len = espi_trans->len; 300 trans.tx_buf = espi_trans->tx_buf; 301 trans.rx_buf = espi_trans->rx_buf; 302 spi_message_add_tail(&trans, &message); 303 304 list_for_each_entry(t, &message.transfers, transfer_list) { 305 if (t->bits_per_word || t->speed_hz) { 306 status = -EINVAL; 307 308 status = fsl_espi_setup_transfer(spi, t); 309 if (status < 0) 310 break; 311 } 312 313 if (t->len) 314 status = fsl_espi_bufs(spi, t); 315 316 if (status) { 317 status = -EMSGSIZE; 318 break; 319 } 320 321 if (t->delay_usecs) 322 udelay(t->delay_usecs); 323 } 324 325 espi_trans->status = status; 326 fsl_espi_setup_transfer(spi, NULL); 327} 328 329static void fsl_espi_cmd_trans(struct spi_message *m, 330 struct fsl_espi_transfer *trans, u8 *rx_buff) 331{ 332 struct spi_transfer *t; 333 u8 *local_buf; 334 int i = 0; 335 struct fsl_espi_transfer *espi_trans = trans; 336 337 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL); 338 if (!local_buf) { 339 espi_trans->status = -ENOMEM; 340 return; 341 } 342 343 list_for_each_entry(t, &m->transfers, transfer_list) { 344 if (t->tx_buf) { 345 memcpy(local_buf + i, t->tx_buf, t->len); 346 i += t->len; 347 } 348 } 349 350 espi_trans->tx_buf = local_buf; 351 espi_trans->rx_buf = local_buf; 352 fsl_espi_do_trans(m, espi_trans); 353 354 espi_trans->actual_length = espi_trans->len; 355 kfree(local_buf); 356} 357 358static void fsl_espi_rw_trans(struct spi_message *m, 359 struct fsl_espi_transfer *trans, u8 *rx_buff) 360{ 361 struct fsl_espi_transfer *espi_trans = trans; 362 unsigned int total_len = espi_trans->len; 363 struct spi_transfer *t; 364 u8 *local_buf; 365 u8 *rx_buf = rx_buff; 366 unsigned int trans_len; 367 unsigned int addr; 368 unsigned int tx_only; 369 unsigned int rx_pos = 0; 370 unsigned int pos; 371 int i, loop; 372 373 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL); 374 if (!local_buf) { 375 espi_trans->status = -ENOMEM; 376 return; 377 } 378 379 for (pos = 0, loop = 0; pos < total_len; pos += trans_len, loop++) { 380 trans_len = total_len - pos; 381 382 i = 0; 383 tx_only = 0; 384 list_for_each_entry(t, &m->transfers, transfer_list) { 385 if (t->tx_buf) { 386 memcpy(local_buf + i, t->tx_buf, t->len); 387 i += t->len; 388 if (!t->rx_buf) 389 tx_only += t->len; 390 } 391 } 392 393 /* Add additional TX bytes to compensate SPCOM_TRANLEN_MAX */ 394 if (loop > 0) 395 trans_len += tx_only; 396 397 if (trans_len > SPCOM_TRANLEN_MAX) 398 trans_len = SPCOM_TRANLEN_MAX; 399 400 /* Update device offset */ 401 if (pos > 0) { 402 addr = fsl_espi_cmd2addr(local_buf); 403 addr += rx_pos; 404 fsl_espi_addr2cmd(addr, local_buf); 405 } 406 407 espi_trans->len = trans_len; 408 espi_trans->tx_buf = local_buf; 409 espi_trans->rx_buf = local_buf; 410 fsl_espi_do_trans(m, espi_trans); 411 412 /* If there is at least one RX byte then copy it to rx_buf */ 413 if (tx_only < SPCOM_TRANLEN_MAX) 414 memcpy(rx_buf + rx_pos, espi_trans->rx_buf + tx_only, 415 trans_len - tx_only); 416 417 rx_pos += trans_len - tx_only; 418 419 if (loop > 0) 420 espi_trans->actual_length += espi_trans->len - tx_only; 421 else 422 espi_trans->actual_length += espi_trans->len; 423 } 424 425 kfree(local_buf); 426} 427 428static int fsl_espi_do_one_msg(struct spi_master *master, 429 struct spi_message *m) 430{ 431 struct spi_transfer *t; 432 u8 *rx_buf = NULL; 433 unsigned int n_tx = 0; 434 unsigned int n_rx = 0; 435 unsigned int xfer_len = 0; 436 struct fsl_espi_transfer espi_trans; 437 438 list_for_each_entry(t, &m->transfers, transfer_list) { 439 if (t->tx_buf) 440 n_tx += t->len; 441 if (t->rx_buf) { 442 n_rx += t->len; 443 rx_buf = t->rx_buf; 444 } 445 if ((t->tx_buf) || (t->rx_buf)) 446 xfer_len += t->len; 447 } 448 449 espi_trans.n_tx = n_tx; 450 espi_trans.n_rx = n_rx; 451 espi_trans.len = xfer_len; 452 espi_trans.actual_length = 0; 453 espi_trans.status = 0; 454 455 if (!rx_buf) 456 fsl_espi_cmd_trans(m, &espi_trans, NULL); 457 else 458 fsl_espi_rw_trans(m, &espi_trans, rx_buf); 459 460 m->actual_length = espi_trans.actual_length; 461 m->status = espi_trans.status; 462 spi_finalize_current_message(master); 463 return 0; 464} 465 466static int fsl_espi_setup(struct spi_device *spi) 467{ 468 struct mpc8xxx_spi *mpc8xxx_spi; 469 struct fsl_espi_reg *reg_base; 470 int retval; 471 u32 hw_mode; 472 u32 loop_mode; 473 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); 474 475 if (!spi->max_speed_hz) 476 return -EINVAL; 477 478 if (!cs) { 479 cs = kzalloc(sizeof(*cs), GFP_KERNEL); 480 if (!cs) 481 return -ENOMEM; 482 spi_set_ctldata(spi, cs); 483 } 484 485 mpc8xxx_spi = spi_master_get_devdata(spi->master); 486 reg_base = mpc8xxx_spi->reg_base; 487 488 hw_mode = cs->hw_mode; /* Save original settings */ 489 cs->hw_mode = mpc8xxx_spi_read_reg( 490 ®_base->csmode[spi->chip_select]); 491 /* mask out bits we are going to set */ 492 cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH 493 | CSMODE_REV); 494 495 if (spi->mode & SPI_CPHA) 496 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK; 497 if (spi->mode & SPI_CPOL) 498 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH; 499 if (!(spi->mode & SPI_LSB_FIRST)) 500 cs->hw_mode |= CSMODE_REV; 501 502 /* Handle the loop mode */ 503 loop_mode = mpc8xxx_spi_read_reg(®_base->mode); 504 loop_mode &= ~SPMODE_LOOP; 505 if (spi->mode & SPI_LOOP) 506 loop_mode |= SPMODE_LOOP; 507 mpc8xxx_spi_write_reg(®_base->mode, loop_mode); 508 509 retval = fsl_espi_setup_transfer(spi, NULL); 510 if (retval < 0) { 511 cs->hw_mode = hw_mode; /* Restore settings */ 512 return retval; 513 } 514 return 0; 515} 516 517static void fsl_espi_cleanup(struct spi_device *spi) 518{ 519 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); 520 521 kfree(cs); 522 spi_set_ctldata(spi, NULL); 523} 524 525void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) 526{ 527 struct fsl_espi_reg *reg_base = mspi->reg_base; 528 529 /* We need handle RX first */ 530 if (events & SPIE_NE) { 531 u32 rx_data, tmp; 532 u8 rx_data_8; 533 534 /* Spin until RX is done */ 535 while (SPIE_RXCNT(events) < min(4, mspi->len)) { 536 cpu_relax(); 537 events = mpc8xxx_spi_read_reg(®_base->event); 538 } 539 540 if (mspi->len >= 4) { 541 rx_data = mpc8xxx_spi_read_reg(®_base->receive); 542 } else { 543 tmp = mspi->len; 544 rx_data = 0; 545 while (tmp--) { 546 rx_data_8 = in_8((u8 *)®_base->receive); 547 rx_data |= (rx_data_8 << (tmp * 8)); 548 } 549 550 rx_data <<= (4 - mspi->len) * 8; 551 } 552 553 mspi->len -= 4; 554 555 if (mspi->rx) 556 mspi->get_rx(rx_data, mspi); 557 } 558 559 if (!(events & SPIE_NF)) { 560 int ret; 561 562 /* spin until TX is done */ 563 ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg( 564 ®_base->event)) & SPIE_NF) == 0, 1000, 0); 565 if (!ret) { 566 dev_err(mspi->dev, "tired waiting for SPIE_NF\n"); 567 return; 568 } 569 } 570 571 /* Clear the events */ 572 mpc8xxx_spi_write_reg(®_base->event, events); 573 574 mspi->count -= 1; 575 if (mspi->count) { 576 u32 word = mspi->get_tx(mspi); 577 578 mpc8xxx_spi_write_reg(®_base->transmit, word); 579 } else { 580 complete(&mspi->done); 581 } 582} 583 584static irqreturn_t fsl_espi_irq(s32 irq, void *context_data) 585{ 586 struct mpc8xxx_spi *mspi = context_data; 587 struct fsl_espi_reg *reg_base = mspi->reg_base; 588 irqreturn_t ret = IRQ_NONE; 589 u32 events; 590 591 /* Get interrupt events(tx/rx) */ 592 events = mpc8xxx_spi_read_reg(®_base->event); 593 if (events) 594 ret = IRQ_HANDLED; 595 596 dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events); 597 598 fsl_espi_cpu_irq(mspi, events); 599 600 return ret; 601} 602 603static void fsl_espi_remove(struct mpc8xxx_spi *mspi) 604{ 605 iounmap(mspi->reg_base); 606} 607 608static int fsl_espi_suspend(struct spi_master *master) 609{ 610 struct mpc8xxx_spi *mpc8xxx_spi; 611 struct fsl_espi_reg *reg_base; 612 u32 regval; 613 614 mpc8xxx_spi = spi_master_get_devdata(master); 615 reg_base = mpc8xxx_spi->reg_base; 616 617 regval = mpc8xxx_spi_read_reg(®_base->mode); 618 regval &= ~SPMODE_ENABLE; 619 mpc8xxx_spi_write_reg(®_base->mode, regval); 620 621 return 0; 622} 623 624static int fsl_espi_resume(struct spi_master *master) 625{ 626 struct mpc8xxx_spi *mpc8xxx_spi; 627 struct fsl_espi_reg *reg_base; 628 u32 regval; 629 630 mpc8xxx_spi = spi_master_get_devdata(master); 631 reg_base = mpc8xxx_spi->reg_base; 632 633 regval = mpc8xxx_spi_read_reg(®_base->mode); 634 regval |= SPMODE_ENABLE; 635 mpc8xxx_spi_write_reg(®_base->mode, regval); 636 637 return 0; 638} 639 640static struct spi_master * fsl_espi_probe(struct device *dev, 641 struct resource *mem, unsigned int irq) 642{ 643 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); 644 struct spi_master *master; 645 struct mpc8xxx_spi *mpc8xxx_spi; 646 struct fsl_espi_reg *reg_base; 647 struct device_node *nc; 648 const __be32 *prop; 649 u32 regval, csmode; 650 int i, len, ret = 0; 651 652 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi)); 653 if (!master) { 654 ret = -ENOMEM; 655 goto err; 656 } 657 658 dev_set_drvdata(dev, master); 659 660 mpc8xxx_spi_probe(dev, mem, irq); 661 662 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); 663 master->setup = fsl_espi_setup; 664 master->cleanup = fsl_espi_cleanup; 665 master->transfer_one_message = fsl_espi_do_one_msg; 666 master->prepare_transfer_hardware = fsl_espi_resume; 667 master->unprepare_transfer_hardware = fsl_espi_suspend; 668 669 mpc8xxx_spi = spi_master_get_devdata(master); 670 mpc8xxx_spi->spi_remove = fsl_espi_remove; 671 672 mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem)); 673 if (!mpc8xxx_spi->reg_base) { 674 ret = -ENOMEM; 675 goto err_probe; 676 } 677 678 reg_base = mpc8xxx_spi->reg_base; 679 680 /* Register for SPI Interrupt */ 681 ret = request_irq(mpc8xxx_spi->irq, fsl_espi_irq, 682 0, "fsl_espi", mpc8xxx_spi); 683 if (ret) 684 goto free_irq; 685 686 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) { 687 mpc8xxx_spi->rx_shift = 16; 688 mpc8xxx_spi->tx_shift = 24; 689 } 690 691 /* SPI controller initializations */ 692 mpc8xxx_spi_write_reg(®_base->mode, 0); 693 mpc8xxx_spi_write_reg(®_base->mask, 0); 694 mpc8xxx_spi_write_reg(®_base->command, 0); 695 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff); 696 697 /* Init eSPI CS mode register */ 698 for_each_available_child_of_node(master->dev.of_node, nc) { 699 /* get chip select */ 700 prop = of_get_property(nc, "reg", &len); 701 if (!prop || len < sizeof(*prop)) 702 continue; 703 i = be32_to_cpup(prop); 704 if (i < 0 || i >= pdata->max_chipselect) 705 continue; 706 707 csmode = CSMODE_INIT_VAL; 708 /* check if CSBEF is set in device tree */ 709 prop = of_get_property(nc, "fsl,csbef", &len); 710 if (prop && len >= sizeof(*prop)) { 711 csmode &= ~(CSMODE_BEF(0xf)); 712 csmode |= CSMODE_BEF(be32_to_cpup(prop)); 713 } 714 /* check if CSAFT is set in device tree */ 715 prop = of_get_property(nc, "fsl,csaft", &len); 716 if (prop && len >= sizeof(*prop)) { 717 csmode &= ~(CSMODE_AFT(0xf)); 718 csmode |= CSMODE_AFT(be32_to_cpup(prop)); 719 } 720 mpc8xxx_spi_write_reg(®_base->csmode[i], csmode); 721 722 dev_info(dev, "cs=%d, init_csmode=0x%x\n", i, csmode); 723 } 724 725 /* Enable SPI interface */ 726 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; 727 728 mpc8xxx_spi_write_reg(®_base->mode, regval); 729 730 ret = spi_register_master(master); 731 if (ret < 0) 732 goto unreg_master; 733 734 dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq); 735 736 return master; 737 738unreg_master: 739 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi); 740free_irq: 741 iounmap(mpc8xxx_spi->reg_base); 742err_probe: 743 spi_master_put(master); 744err: 745 return ERR_PTR(ret); 746} 747 748static int of_fsl_espi_get_chipselects(struct device *dev) 749{ 750 struct device_node *np = dev->of_node; 751 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); 752 const u32 *prop; 753 int len; 754 755 prop = of_get_property(np, "fsl,espi-num-chipselects", &len); 756 if (!prop || len < sizeof(*prop)) { 757 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n"); 758 return -EINVAL; 759 } 760 761 pdata->max_chipselect = *prop; 762 pdata->cs_control = NULL; 763 764 return 0; 765} 766 767static int of_fsl_espi_probe(struct platform_device *ofdev) 768{ 769 struct device *dev = &ofdev->dev; 770 struct device_node *np = ofdev->dev.of_node; 771 struct spi_master *master; 772 struct resource mem; 773 unsigned int irq; 774 int ret = -ENOMEM; 775 776 ret = of_mpc8xxx_spi_probe(ofdev); 777 if (ret) 778 return ret; 779 780 ret = of_fsl_espi_get_chipselects(dev); 781 if (ret) 782 goto err; 783 784 ret = of_address_to_resource(np, 0, &mem); 785 if (ret) 786 goto err; 787 788 irq = irq_of_parse_and_map(np, 0); 789 if (!irq) { 790 ret = -EINVAL; 791 goto err; 792 } 793 794 master = fsl_espi_probe(dev, &mem, irq); 795 if (IS_ERR(master)) { 796 ret = PTR_ERR(master); 797 goto err; 798 } 799 800 return 0; 801 802err: 803 return ret; 804} 805 806static int of_fsl_espi_remove(struct platform_device *dev) 807{ 808 return mpc8xxx_spi_remove(&dev->dev); 809} 810 811#ifdef CONFIG_PM_SLEEP 812static int of_fsl_espi_suspend(struct device *dev) 813{ 814 struct spi_master *master = dev_get_drvdata(dev); 815 int ret; 816 817 ret = spi_master_suspend(master); 818 if (ret) { 819 dev_warn(dev, "cannot suspend master\n"); 820 return ret; 821 } 822 823 return fsl_espi_suspend(master); 824} 825 826static int of_fsl_espi_resume(struct device *dev) 827{ 828 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); 829 struct spi_master *master = dev_get_drvdata(dev); 830 struct mpc8xxx_spi *mpc8xxx_spi; 831 struct fsl_espi_reg *reg_base; 832 u32 regval; 833 int i; 834 835 mpc8xxx_spi = spi_master_get_devdata(master); 836 reg_base = mpc8xxx_spi->reg_base; 837 838 /* SPI controller initializations */ 839 mpc8xxx_spi_write_reg(®_base->mode, 0); 840 mpc8xxx_spi_write_reg(®_base->mask, 0); 841 mpc8xxx_spi_write_reg(®_base->command, 0); 842 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff); 843 844 /* Init eSPI CS mode register */ 845 for (i = 0; i < pdata->max_chipselect; i++) 846 mpc8xxx_spi_write_reg(®_base->csmode[i], CSMODE_INIT_VAL); 847 848 /* Enable SPI interface */ 849 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; 850 851 mpc8xxx_spi_write_reg(®_base->mode, regval); 852 853 return spi_master_resume(master); 854} 855#endif /* CONFIG_PM_SLEEP */ 856 857static const struct dev_pm_ops espi_pm = { 858 SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume) 859}; 860 861static const struct of_device_id of_fsl_espi_match[] = { 862 { .compatible = "fsl,mpc8536-espi" }, 863 {} 864}; 865MODULE_DEVICE_TABLE(of, of_fsl_espi_match); 866 867static struct platform_driver fsl_espi_driver = { 868 .driver = { 869 .name = "fsl_espi", 870 .of_match_table = of_fsl_espi_match, 871 .pm = &espi_pm, 872 }, 873 .probe = of_fsl_espi_probe, 874 .remove = of_fsl_espi_remove, 875}; 876module_platform_driver(fsl_espi_driver); 877 878MODULE_AUTHOR("Mingkai Hu"); 879MODULE_DESCRIPTION("Enhanced Freescale SPI Driver"); 880MODULE_LICENSE("GPL"); 881