1/* 2 * Marvell Orion SPI controller driver 3 * 4 * Author: Shadi Ammouri <shadi@marvell.com> 5 * Copyright (C) 2007-2008 Marvell Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12#include <linux/interrupt.h> 13#include <linux/delay.h> 14#include <linux/platform_device.h> 15#include <linux/err.h> 16#include <linux/io.h> 17#include <linux/spi/spi.h> 18#include <linux/module.h> 19#include <linux/pm_runtime.h> 20#include <linux/of.h> 21#include <linux/of_device.h> 22#include <linux/clk.h> 23#include <linux/sizes.h> 24#include <asm/unaligned.h> 25 26#define DRIVER_NAME "orion_spi" 27 28/* Runtime PM autosuspend timeout: PM is fairly light on this driver */ 29#define SPI_AUTOSUSPEND_TIMEOUT 200 30 31/* Some SoCs using this driver support up to 8 chip selects. 32 * It is up to the implementer to only use the chip selects 33 * that are available. 34 */ 35#define ORION_NUM_CHIPSELECTS 8 36 37#define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */ 38 39#define ORION_SPI_IF_CTRL_REG 0x00 40#define ORION_SPI_IF_CONFIG_REG 0x04 41#define ORION_SPI_DATA_OUT_REG 0x08 42#define ORION_SPI_DATA_IN_REG 0x0c 43#define ORION_SPI_INT_CAUSE_REG 0x10 44 45#define ORION_SPI_MODE_CPOL (1 << 11) 46#define ORION_SPI_MODE_CPHA (1 << 12) 47#define ORION_SPI_IF_8_16_BIT_MODE (1 << 5) 48#define ORION_SPI_CLK_PRESCALE_MASK 0x1F 49#define ARMADA_SPI_CLK_PRESCALE_MASK 0xDF 50#define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \ 51 ORION_SPI_MODE_CPHA) 52#define ORION_SPI_CS_MASK 0x1C 53#define ORION_SPI_CS_SHIFT 2 54#define ORION_SPI_CS(cs) ((cs << ORION_SPI_CS_SHIFT) & \ 55 ORION_SPI_CS_MASK) 56 57enum orion_spi_type { 58 ORION_SPI, 59 ARMADA_SPI, 60}; 61 62struct orion_spi_dev { 63 enum orion_spi_type typ; 64 /* 65 * min_divisor and max_hz should be exclusive, the only we can 66 * have both is for managing the armada-370-spi case with old 67 * device tree 68 */ 69 unsigned long max_hz; 70 unsigned int min_divisor; 71 unsigned int max_divisor; 72 u32 prescale_mask; 73}; 74 75struct orion_spi { 76 struct spi_master *master; 77 void __iomem *base; 78 struct clk *clk; 79 const struct orion_spi_dev *devdata; 80}; 81 82static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg) 83{ 84 return orion_spi->base + reg; 85} 86 87static inline void 88orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask) 89{ 90 void __iomem *reg_addr = spi_reg(orion_spi, reg); 91 u32 val; 92 93 val = readl(reg_addr); 94 val |= mask; 95 writel(val, reg_addr); 96} 97 98static inline void 99orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask) 100{ 101 void __iomem *reg_addr = spi_reg(orion_spi, reg); 102 u32 val; 103 104 val = readl(reg_addr); 105 val &= ~mask; 106 writel(val, reg_addr); 107} 108 109static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed) 110{ 111 u32 tclk_hz; 112 u32 rate; 113 u32 prescale; 114 u32 reg; 115 struct orion_spi *orion_spi; 116 const struct orion_spi_dev *devdata; 117 118 orion_spi = spi_master_get_devdata(spi->master); 119 devdata = orion_spi->devdata; 120 121 tclk_hz = clk_get_rate(orion_spi->clk); 122 123 if (devdata->typ == ARMADA_SPI) { 124 unsigned int clk, spr, sppr, sppr2, err; 125 unsigned int best_spr, best_sppr, best_err; 126 127 best_err = speed; 128 best_spr = 0; 129 best_sppr = 0; 130 131 /* Iterate over the valid range looking for best fit */ 132 for (sppr = 0; sppr < 8; sppr++) { 133 sppr2 = 0x1 << sppr; 134 135 spr = tclk_hz / sppr2; 136 spr = DIV_ROUND_UP(spr, speed); 137 if ((spr == 0) || (spr > 15)) 138 continue; 139 140 clk = tclk_hz / (spr * sppr2); 141 err = speed - clk; 142 143 if (err < best_err) { 144 best_spr = spr; 145 best_sppr = sppr; 146 best_err = err; 147 } 148 } 149 150 if ((best_sppr == 0) && (best_spr == 0)) 151 return -EINVAL; 152 153 prescale = ((best_sppr & 0x6) << 5) | 154 ((best_sppr & 0x1) << 4) | best_spr; 155 } else { 156 /* 157 * the supported rates are: 4,6,8...30 158 * round up as we look for equal or less speed 159 */ 160 rate = DIV_ROUND_UP(tclk_hz, speed); 161 rate = roundup(rate, 2); 162 163 /* check if requested speed is too small */ 164 if (rate > 30) 165 return -EINVAL; 166 167 if (rate < 4) 168 rate = 4; 169 170 /* Convert the rate to SPI clock divisor value. */ 171 prescale = 0x10 + rate/2; 172 } 173 174 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); 175 reg = ((reg & ~devdata->prescale_mask) | prescale); 176 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); 177 178 return 0; 179} 180 181static void 182orion_spi_mode_set(struct spi_device *spi) 183{ 184 u32 reg; 185 struct orion_spi *orion_spi; 186 187 orion_spi = spi_master_get_devdata(spi->master); 188 189 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); 190 reg &= ~ORION_SPI_MODE_MASK; 191 if (spi->mode & SPI_CPOL) 192 reg |= ORION_SPI_MODE_CPOL; 193 if (spi->mode & SPI_CPHA) 194 reg |= ORION_SPI_MODE_CPHA; 195 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); 196} 197 198/* 199 * called only when no transfer is active on the bus 200 */ 201static int 202orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) 203{ 204 struct orion_spi *orion_spi; 205 unsigned int speed = spi->max_speed_hz; 206 unsigned int bits_per_word = spi->bits_per_word; 207 int rc; 208 209 orion_spi = spi_master_get_devdata(spi->master); 210 211 if ((t != NULL) && t->speed_hz) 212 speed = t->speed_hz; 213 214 if ((t != NULL) && t->bits_per_word) 215 bits_per_word = t->bits_per_word; 216 217 orion_spi_mode_set(spi); 218 219 rc = orion_spi_baudrate_set(spi, speed); 220 if (rc) 221 return rc; 222 223 if (bits_per_word == 16) 224 orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG, 225 ORION_SPI_IF_8_16_BIT_MODE); 226 else 227 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG, 228 ORION_SPI_IF_8_16_BIT_MODE); 229 230 return 0; 231} 232 233static void orion_spi_set_cs(struct spi_device *spi, bool enable) 234{ 235 struct orion_spi *orion_spi; 236 237 orion_spi = spi_master_get_devdata(spi->master); 238 239 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, ORION_SPI_CS_MASK); 240 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 241 ORION_SPI_CS(spi->chip_select)); 242 243 /* Chip select logic is inverted from spi_set_cs */ 244 if (!enable) 245 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); 246 else 247 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); 248} 249 250static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi) 251{ 252 int i; 253 254 for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) { 255 if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG))) 256 return 1; 257 258 udelay(1); 259 } 260 261 return -1; 262} 263 264static inline int 265orion_spi_write_read_8bit(struct spi_device *spi, 266 const u8 **tx_buf, u8 **rx_buf) 267{ 268 void __iomem *tx_reg, *rx_reg, *int_reg; 269 struct orion_spi *orion_spi; 270 271 orion_spi = spi_master_get_devdata(spi->master); 272 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG); 273 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG); 274 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG); 275 276 /* clear the interrupt cause register */ 277 writel(0x0, int_reg); 278 279 if (tx_buf && *tx_buf) 280 writel(*(*tx_buf)++, tx_reg); 281 else 282 writel(0, tx_reg); 283 284 if (orion_spi_wait_till_ready(orion_spi) < 0) { 285 dev_err(&spi->dev, "TXS timed out\n"); 286 return -1; 287 } 288 289 if (rx_buf && *rx_buf) 290 *(*rx_buf)++ = readl(rx_reg); 291 292 return 1; 293} 294 295static inline int 296orion_spi_write_read_16bit(struct spi_device *spi, 297 const u16 **tx_buf, u16 **rx_buf) 298{ 299 void __iomem *tx_reg, *rx_reg, *int_reg; 300 struct orion_spi *orion_spi; 301 302 orion_spi = spi_master_get_devdata(spi->master); 303 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG); 304 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG); 305 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG); 306 307 /* clear the interrupt cause register */ 308 writel(0x0, int_reg); 309 310 if (tx_buf && *tx_buf) 311 writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg); 312 else 313 writel(0, tx_reg); 314 315 if (orion_spi_wait_till_ready(orion_spi) < 0) { 316 dev_err(&spi->dev, "TXS timed out\n"); 317 return -1; 318 } 319 320 if (rx_buf && *rx_buf) 321 put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++); 322 323 return 1; 324} 325 326static unsigned int 327orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer) 328{ 329 unsigned int count; 330 int word_len; 331 332 word_len = spi->bits_per_word; 333 count = xfer->len; 334 335 if (word_len == 8) { 336 const u8 *tx = xfer->tx_buf; 337 u8 *rx = xfer->rx_buf; 338 339 do { 340 if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0) 341 goto out; 342 count--; 343 } while (count); 344 } else if (word_len == 16) { 345 const u16 *tx = xfer->tx_buf; 346 u16 *rx = xfer->rx_buf; 347 348 do { 349 if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0) 350 goto out; 351 count -= 2; 352 } while (count); 353 } 354 355out: 356 return xfer->len - count; 357} 358 359static int orion_spi_transfer_one(struct spi_master *master, 360 struct spi_device *spi, 361 struct spi_transfer *t) 362{ 363 int status = 0; 364 365 status = orion_spi_setup_transfer(spi, t); 366 if (status < 0) 367 return status; 368 369 if (t->len) 370 orion_spi_write_read(spi, t); 371 372 return status; 373} 374 375static int orion_spi_setup(struct spi_device *spi) 376{ 377 return orion_spi_setup_transfer(spi, NULL); 378} 379 380static int orion_spi_reset(struct orion_spi *orion_spi) 381{ 382 /* Verify that the CS is deasserted */ 383 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); 384 return 0; 385} 386 387static const struct orion_spi_dev orion_spi_dev_data = { 388 .typ = ORION_SPI, 389 .min_divisor = 4, 390 .max_divisor = 30, 391 .prescale_mask = ORION_SPI_CLK_PRESCALE_MASK, 392}; 393 394static const struct orion_spi_dev armada_spi_dev_data = { 395 .typ = ARMADA_SPI, 396 .min_divisor = 4, 397 .max_divisor = 1920, 398 .max_hz = 50000000, 399 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, 400}; 401 402static const struct of_device_id orion_spi_of_match_table[] = { 403 { .compatible = "marvell,orion-spi", .data = &orion_spi_dev_data, }, 404 { .compatible = "marvell,armada-370-spi", .data = &armada_spi_dev_data, }, 405 {} 406}; 407MODULE_DEVICE_TABLE(of, orion_spi_of_match_table); 408 409static int orion_spi_probe(struct platform_device *pdev) 410{ 411 const struct of_device_id *of_id; 412 const struct orion_spi_dev *devdata; 413 struct spi_master *master; 414 struct orion_spi *spi; 415 struct resource *r; 416 unsigned long tclk_hz; 417 int status = 0; 418 419 master = spi_alloc_master(&pdev->dev, sizeof(*spi)); 420 if (master == NULL) { 421 dev_dbg(&pdev->dev, "master allocation failed\n"); 422 return -ENOMEM; 423 } 424 425 if (pdev->id != -1) 426 master->bus_num = pdev->id; 427 if (pdev->dev.of_node) { 428 u32 cell_index; 429 430 if (!of_property_read_u32(pdev->dev.of_node, "cell-index", 431 &cell_index)) 432 master->bus_num = cell_index; 433 } 434 435 /* we support only mode 0, and no options */ 436 master->mode_bits = SPI_CPHA | SPI_CPOL; 437 master->set_cs = orion_spi_set_cs; 438 master->transfer_one = orion_spi_transfer_one; 439 master->num_chipselect = ORION_NUM_CHIPSELECTS; 440 master->setup = orion_spi_setup; 441 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); 442 master->auto_runtime_pm = true; 443 444 platform_set_drvdata(pdev, master); 445 446 spi = spi_master_get_devdata(master); 447 spi->master = master; 448 449 of_id = of_match_device(orion_spi_of_match_table, &pdev->dev); 450 devdata = (of_id) ? of_id->data : &orion_spi_dev_data; 451 spi->devdata = devdata; 452 453 spi->clk = devm_clk_get(&pdev->dev, NULL); 454 if (IS_ERR(spi->clk)) { 455 status = PTR_ERR(spi->clk); 456 goto out; 457 } 458 459 status = clk_prepare_enable(spi->clk); 460 if (status) 461 goto out; 462 463 tclk_hz = clk_get_rate(spi->clk); 464 465 /* 466 * With old device tree, armada-370-spi could be used with 467 * Armada XP, however for this SoC the maximum frequency is 468 * 50MHz instead of tclk/4. On Armada 370, tclk cannot be 469 * higher than 200MHz. So, in order to be able to handle both 470 * SoCs, we can take the minimum of 50MHz and tclk/4. 471 */ 472 if (of_device_is_compatible(pdev->dev.of_node, 473 "marvell,armada-370-spi")) 474 master->max_speed_hz = min(devdata->max_hz, 475 DIV_ROUND_UP(tclk_hz, devdata->min_divisor)); 476 else 477 master->max_speed_hz = 478 DIV_ROUND_UP(tclk_hz, devdata->min_divisor); 479 master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor); 480 481 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 482 spi->base = devm_ioremap_resource(&pdev->dev, r); 483 if (IS_ERR(spi->base)) { 484 status = PTR_ERR(spi->base); 485 goto out_rel_clk; 486 } 487 488 pm_runtime_set_active(&pdev->dev); 489 pm_runtime_use_autosuspend(&pdev->dev); 490 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); 491 pm_runtime_enable(&pdev->dev); 492 493 status = orion_spi_reset(spi); 494 if (status < 0) 495 goto out_rel_pm; 496 497 pm_runtime_mark_last_busy(&pdev->dev); 498 pm_runtime_put_autosuspend(&pdev->dev); 499 500 master->dev.of_node = pdev->dev.of_node; 501 status = spi_register_master(master); 502 if (status < 0) 503 goto out_rel_pm; 504 505 return status; 506 507out_rel_pm: 508 pm_runtime_disable(&pdev->dev); 509out_rel_clk: 510 clk_disable_unprepare(spi->clk); 511out: 512 spi_master_put(master); 513 return status; 514} 515 516 517static int orion_spi_remove(struct platform_device *pdev) 518{ 519 struct spi_master *master = platform_get_drvdata(pdev); 520 struct orion_spi *spi = spi_master_get_devdata(master); 521 522 pm_runtime_get_sync(&pdev->dev); 523 clk_disable_unprepare(spi->clk); 524 525 spi_unregister_master(master); 526 pm_runtime_disable(&pdev->dev); 527 528 return 0; 529} 530 531MODULE_ALIAS("platform:" DRIVER_NAME); 532 533#ifdef CONFIG_PM 534static int orion_spi_runtime_suspend(struct device *dev) 535{ 536 struct spi_master *master = dev_get_drvdata(dev); 537 struct orion_spi *spi = spi_master_get_devdata(master); 538 539 clk_disable_unprepare(spi->clk); 540 return 0; 541} 542 543static int orion_spi_runtime_resume(struct device *dev) 544{ 545 struct spi_master *master = dev_get_drvdata(dev); 546 struct orion_spi *spi = spi_master_get_devdata(master); 547 548 return clk_prepare_enable(spi->clk); 549} 550#endif 551 552static const struct dev_pm_ops orion_spi_pm_ops = { 553 SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend, 554 orion_spi_runtime_resume, 555 NULL) 556}; 557 558static struct platform_driver orion_spi_driver = { 559 .driver = { 560 .name = DRIVER_NAME, 561 .pm = &orion_spi_pm_ops, 562 .of_match_table = of_match_ptr(orion_spi_of_match_table), 563 }, 564 .probe = orion_spi_probe, 565 .remove = orion_spi_remove, 566}; 567 568module_platform_driver(orion_spi_driver); 569 570MODULE_DESCRIPTION("Orion SPI driver"); 571MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>"); 572MODULE_LICENSE("GPL"); 573