1/* 2 * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit) 3 * 4 * Copyright (C) 2014 Samsung Electronics 5 * Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> 6 * Lukasz Majewski <l.majewski@samsung.com> 7 * 8 * Copyright (C) 2011 Samsung Electronics 9 * Donggeun Kim <dg77.kim@samsung.com> 10 * Amit Daniel Kachhap <amit.kachhap@linaro.org> 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 * 26 */ 27 28#include <linux/clk.h> 29#include <linux/io.h> 30#include <linux/interrupt.h> 31#include <linux/module.h> 32#include <linux/of.h> 33#include <linux/of_address.h> 34#include <linux/of_irq.h> 35#include <linux/platform_device.h> 36#include <linux/regulator/consumer.h> 37 38#include "exynos_tmu.h" 39#include "../thermal_core.h" 40 41/* Exynos generic registers */ 42#define EXYNOS_TMU_REG_TRIMINFO 0x0 43#define EXYNOS_TMU_REG_CONTROL 0x20 44#define EXYNOS_TMU_REG_STATUS 0x28 45#define EXYNOS_TMU_REG_CURRENT_TEMP 0x40 46#define EXYNOS_TMU_REG_INTEN 0x70 47#define EXYNOS_TMU_REG_INTSTAT 0x74 48#define EXYNOS_TMU_REG_INTCLEAR 0x78 49 50#define EXYNOS_TMU_TEMP_MASK 0xff 51#define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24 52#define EXYNOS_TMU_REF_VOLTAGE_MASK 0x1f 53#define EXYNOS_TMU_BUF_SLOPE_SEL_MASK 0xf 54#define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8 55#define EXYNOS_TMU_CORE_EN_SHIFT 0 56 57/* Exynos3250 specific registers */ 58#define EXYNOS_TMU_TRIMINFO_CON1 0x10 59 60/* Exynos4210 specific registers */ 61#define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44 62#define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50 63 64/* Exynos5250, Exynos4412, Exynos3250 specific registers */ 65#define EXYNOS_TMU_TRIMINFO_CON2 0x14 66#define EXYNOS_THD_TEMP_RISE 0x50 67#define EXYNOS_THD_TEMP_FALL 0x54 68#define EXYNOS_EMUL_CON 0x80 69 70#define EXYNOS_TRIMINFO_RELOAD_ENABLE 1 71#define EXYNOS_TRIMINFO_25_SHIFT 0 72#define EXYNOS_TRIMINFO_85_SHIFT 8 73#define EXYNOS_TMU_TRIP_MODE_SHIFT 13 74#define EXYNOS_TMU_TRIP_MODE_MASK 0x7 75#define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12 76 77#define EXYNOS_TMU_INTEN_RISE0_SHIFT 0 78#define EXYNOS_TMU_INTEN_RISE1_SHIFT 4 79#define EXYNOS_TMU_INTEN_RISE2_SHIFT 8 80#define EXYNOS_TMU_INTEN_RISE3_SHIFT 12 81#define EXYNOS_TMU_INTEN_FALL0_SHIFT 16 82 83#define EXYNOS_EMUL_TIME 0x57F0 84#define EXYNOS_EMUL_TIME_MASK 0xffff 85#define EXYNOS_EMUL_TIME_SHIFT 16 86#define EXYNOS_EMUL_DATA_SHIFT 8 87#define EXYNOS_EMUL_DATA_MASK 0xFF 88#define EXYNOS_EMUL_ENABLE 0x1 89 90/* Exynos5260 specific */ 91#define EXYNOS5260_TMU_REG_INTEN 0xC0 92#define EXYNOS5260_TMU_REG_INTSTAT 0xC4 93#define EXYNOS5260_TMU_REG_INTCLEAR 0xC8 94#define EXYNOS5260_EMUL_CON 0x100 95 96/* Exynos4412 specific */ 97#define EXYNOS4412_MUX_ADDR_VALUE 6 98#define EXYNOS4412_MUX_ADDR_SHIFT 20 99 100/*exynos5440 specific registers*/ 101#define EXYNOS5440_TMU_S0_7_TRIM 0x000 102#define EXYNOS5440_TMU_S0_7_CTRL 0x020 103#define EXYNOS5440_TMU_S0_7_DEBUG 0x040 104#define EXYNOS5440_TMU_S0_7_TEMP 0x0f0 105#define EXYNOS5440_TMU_S0_7_TH0 0x110 106#define EXYNOS5440_TMU_S0_7_TH1 0x130 107#define EXYNOS5440_TMU_S0_7_TH2 0x150 108#define EXYNOS5440_TMU_S0_7_IRQEN 0x210 109#define EXYNOS5440_TMU_S0_7_IRQ 0x230 110/* exynos5440 common registers */ 111#define EXYNOS5440_TMU_IRQ_STATUS 0x000 112#define EXYNOS5440_TMU_PMIN 0x004 113 114#define EXYNOS5440_TMU_INTEN_RISE0_SHIFT 0 115#define EXYNOS5440_TMU_INTEN_RISE1_SHIFT 1 116#define EXYNOS5440_TMU_INTEN_RISE2_SHIFT 2 117#define EXYNOS5440_TMU_INTEN_RISE3_SHIFT 3 118#define EXYNOS5440_TMU_INTEN_FALL0_SHIFT 4 119#define EXYNOS5440_TMU_TH_RISE4_SHIFT 24 120#define EXYNOS5440_EFUSE_SWAP_OFFSET 8 121 122/* Exynos7 specific registers */ 123#define EXYNOS7_THD_TEMP_RISE7_6 0x50 124#define EXYNOS7_THD_TEMP_FALL7_6 0x60 125#define EXYNOS7_TMU_REG_INTEN 0x110 126#define EXYNOS7_TMU_REG_INTPEND 0x118 127#define EXYNOS7_TMU_REG_EMUL_CON 0x160 128 129#define EXYNOS7_TMU_TEMP_MASK 0x1ff 130#define EXYNOS7_PD_DET_EN_SHIFT 23 131#define EXYNOS7_TMU_INTEN_RISE0_SHIFT 0 132#define EXYNOS7_TMU_INTEN_RISE1_SHIFT 1 133#define EXYNOS7_TMU_INTEN_RISE2_SHIFT 2 134#define EXYNOS7_TMU_INTEN_RISE3_SHIFT 3 135#define EXYNOS7_TMU_INTEN_RISE4_SHIFT 4 136#define EXYNOS7_TMU_INTEN_RISE5_SHIFT 5 137#define EXYNOS7_TMU_INTEN_RISE6_SHIFT 6 138#define EXYNOS7_TMU_INTEN_RISE7_SHIFT 7 139#define EXYNOS7_EMUL_DATA_SHIFT 7 140#define EXYNOS7_EMUL_DATA_MASK 0x1ff 141 142#define MCELSIUS 1000 143/** 144 * struct exynos_tmu_data : A structure to hold the private data of the TMU 145 driver 146 * @id: identifier of the one instance of the TMU controller. 147 * @pdata: pointer to the tmu platform/configuration data 148 * @base: base address of the single instance of the TMU controller. 149 * @base_second: base address of the common registers of the TMU controller. 150 * @irq: irq number of the TMU controller. 151 * @soc: id of the SOC type. 152 * @irq_work: pointer to the irq work structure. 153 * @lock: lock to implement synchronization. 154 * @clk: pointer to the clock structure. 155 * @clk_sec: pointer to the clock structure for accessing the base_second. 156 * @sclk: pointer to the clock structure for accessing the tmu special clk. 157 * @temp_error1: fused value of the first point trim. 158 * @temp_error2: fused value of the second point trim. 159 * @regulator: pointer to the TMU regulator structure. 160 * @reg_conf: pointer to structure to register with core thermal. 161 * @tmu_initialize: SoC specific TMU initialization method 162 * @tmu_control: SoC specific TMU control method 163 * @tmu_read: SoC specific TMU temperature read method 164 * @tmu_set_emulation: SoC specific TMU emulation setting method 165 * @tmu_clear_irqs: SoC specific TMU interrupts clearing method 166 */ 167struct exynos_tmu_data { 168 int id; 169 struct exynos_tmu_platform_data *pdata; 170 void __iomem *base; 171 void __iomem *base_second; 172 int irq; 173 enum soc_type soc; 174 struct work_struct irq_work; 175 struct mutex lock; 176 struct clk *clk, *clk_sec, *sclk; 177 u16 temp_error1, temp_error2; 178 struct regulator *regulator; 179 struct thermal_zone_device *tzd; 180 181 int (*tmu_initialize)(struct platform_device *pdev); 182 void (*tmu_control)(struct platform_device *pdev, bool on); 183 int (*tmu_read)(struct exynos_tmu_data *data); 184 void (*tmu_set_emulation)(struct exynos_tmu_data *data, 185 unsigned long temp); 186 void (*tmu_clear_irqs)(struct exynos_tmu_data *data); 187}; 188 189static void exynos_report_trigger(struct exynos_tmu_data *p) 190{ 191 char data[10], *envp[] = { data, NULL }; 192 struct thermal_zone_device *tz = p->tzd; 193 unsigned long temp; 194 unsigned int i; 195 196 if (!tz) { 197 pr_err("No thermal zone device defined\n"); 198 return; 199 } 200 201 thermal_zone_device_update(tz); 202 203 mutex_lock(&tz->lock); 204 /* Find the level for which trip happened */ 205 for (i = 0; i < of_thermal_get_ntrips(tz); i++) { 206 tz->ops->get_trip_temp(tz, i, &temp); 207 if (tz->last_temperature < temp) 208 break; 209 } 210 211 snprintf(data, sizeof(data), "%u", i); 212 kobject_uevent_env(&tz->device.kobj, KOBJ_CHANGE, envp); 213 mutex_unlock(&tz->lock); 214} 215 216/* 217 * TMU treats temperature as a mapped temperature code. 218 * The temperature is converted differently depending on the calibration type. 219 */ 220static int temp_to_code(struct exynos_tmu_data *data, u8 temp) 221{ 222 struct exynos_tmu_platform_data *pdata = data->pdata; 223 int temp_code; 224 225 switch (pdata->cal_type) { 226 case TYPE_TWO_POINT_TRIMMING: 227 temp_code = (temp - pdata->first_point_trim) * 228 (data->temp_error2 - data->temp_error1) / 229 (pdata->second_point_trim - pdata->first_point_trim) + 230 data->temp_error1; 231 break; 232 case TYPE_ONE_POINT_TRIMMING: 233 temp_code = temp + data->temp_error1 - pdata->first_point_trim; 234 break; 235 default: 236 temp_code = temp + pdata->default_temp_offset; 237 break; 238 } 239 240 return temp_code; 241} 242 243/* 244 * Calculate a temperature value from a temperature code. 245 * The unit of the temperature is degree Celsius. 246 */ 247static int code_to_temp(struct exynos_tmu_data *data, u16 temp_code) 248{ 249 struct exynos_tmu_platform_data *pdata = data->pdata; 250 int temp; 251 252 switch (pdata->cal_type) { 253 case TYPE_TWO_POINT_TRIMMING: 254 temp = (temp_code - data->temp_error1) * 255 (pdata->second_point_trim - pdata->first_point_trim) / 256 (data->temp_error2 - data->temp_error1) + 257 pdata->first_point_trim; 258 break; 259 case TYPE_ONE_POINT_TRIMMING: 260 temp = temp_code - data->temp_error1 + pdata->first_point_trim; 261 break; 262 default: 263 temp = temp_code - pdata->default_temp_offset; 264 break; 265 } 266 267 return temp; 268} 269 270static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info) 271{ 272 struct exynos_tmu_platform_data *pdata = data->pdata; 273 274 data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK; 275 data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) & 276 EXYNOS_TMU_TEMP_MASK); 277 278 if (!data->temp_error1 || 279 (pdata->min_efuse_value > data->temp_error1) || 280 (data->temp_error1 > pdata->max_efuse_value)) 281 data->temp_error1 = pdata->efuse_value & EXYNOS_TMU_TEMP_MASK; 282 283 if (!data->temp_error2) 284 data->temp_error2 = 285 (pdata->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) & 286 EXYNOS_TMU_TEMP_MASK; 287} 288 289static u32 get_th_reg(struct exynos_tmu_data *data, u32 threshold, bool falling) 290{ 291 struct thermal_zone_device *tz = data->tzd; 292 const struct thermal_trip * const trips = 293 of_thermal_get_trip_points(tz); 294 unsigned long temp; 295 int i; 296 297 if (!trips) { 298 pr_err("%s: Cannot get trip points from of-thermal.c!\n", 299 __func__); 300 return 0; 301 } 302 303 for (i = 0; i < of_thermal_get_ntrips(tz); i++) { 304 if (trips[i].type == THERMAL_TRIP_CRITICAL) 305 continue; 306 307 temp = trips[i].temperature / MCELSIUS; 308 if (falling) 309 temp -= (trips[i].hysteresis / MCELSIUS); 310 else 311 threshold &= ~(0xff << 8 * i); 312 313 threshold |= temp_to_code(data, temp) << 8 * i; 314 } 315 316 return threshold; 317} 318 319static int exynos_tmu_initialize(struct platform_device *pdev) 320{ 321 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 322 int ret; 323 324 mutex_lock(&data->lock); 325 clk_enable(data->clk); 326 if (!IS_ERR(data->clk_sec)) 327 clk_enable(data->clk_sec); 328 ret = data->tmu_initialize(pdev); 329 clk_disable(data->clk); 330 mutex_unlock(&data->lock); 331 if (!IS_ERR(data->clk_sec)) 332 clk_disable(data->clk_sec); 333 334 return ret; 335} 336 337static u32 get_con_reg(struct exynos_tmu_data *data, u32 con) 338{ 339 struct exynos_tmu_platform_data *pdata = data->pdata; 340 341 if (data->soc == SOC_ARCH_EXYNOS4412 || 342 data->soc == SOC_ARCH_EXYNOS3250) 343 con |= (EXYNOS4412_MUX_ADDR_VALUE << EXYNOS4412_MUX_ADDR_SHIFT); 344 345 con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK << EXYNOS_TMU_REF_VOLTAGE_SHIFT); 346 con |= pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT; 347 348 con &= ~(EXYNOS_TMU_BUF_SLOPE_SEL_MASK << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT); 349 con |= (pdata->gain << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT); 350 351 if (pdata->noise_cancel_mode) { 352 con &= ~(EXYNOS_TMU_TRIP_MODE_MASK << EXYNOS_TMU_TRIP_MODE_SHIFT); 353 con |= (pdata->noise_cancel_mode << EXYNOS_TMU_TRIP_MODE_SHIFT); 354 } 355 356 return con; 357} 358 359static void exynos_tmu_control(struct platform_device *pdev, bool on) 360{ 361 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 362 363 mutex_lock(&data->lock); 364 clk_enable(data->clk); 365 data->tmu_control(pdev, on); 366 clk_disable(data->clk); 367 mutex_unlock(&data->lock); 368} 369 370static int exynos4210_tmu_initialize(struct platform_device *pdev) 371{ 372 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 373 struct thermal_zone_device *tz = data->tzd; 374 const struct thermal_trip * const trips = 375 of_thermal_get_trip_points(tz); 376 int ret = 0, threshold_code, i; 377 unsigned long reference, temp; 378 unsigned int status; 379 380 if (!trips) { 381 pr_err("%s: Cannot get trip points from of-thermal.c!\n", 382 __func__); 383 ret = -ENODEV; 384 goto out; 385 } 386 387 status = readb(data->base + EXYNOS_TMU_REG_STATUS); 388 if (!status) { 389 ret = -EBUSY; 390 goto out; 391 } 392 393 sanitize_temp_error(data, readl(data->base + EXYNOS_TMU_REG_TRIMINFO)); 394 395 /* Write temperature code for threshold */ 396 reference = trips[0].temperature / MCELSIUS; 397 threshold_code = temp_to_code(data, reference); 398 if (threshold_code < 0) { 399 ret = threshold_code; 400 goto out; 401 } 402 writeb(threshold_code, data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP); 403 404 for (i = 0; i < of_thermal_get_ntrips(tz); i++) { 405 temp = trips[i].temperature / MCELSIUS; 406 writeb(temp - reference, data->base + 407 EXYNOS4210_TMU_REG_TRIG_LEVEL0 + i * 4); 408 } 409 410 data->tmu_clear_irqs(data); 411out: 412 return ret; 413} 414 415static int exynos4412_tmu_initialize(struct platform_device *pdev) 416{ 417 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 418 const struct thermal_trip * const trips = 419 of_thermal_get_trip_points(data->tzd); 420 unsigned int status, trim_info, con, ctrl, rising_threshold; 421 int ret = 0, threshold_code, i; 422 unsigned long crit_temp = 0; 423 424 status = readb(data->base + EXYNOS_TMU_REG_STATUS); 425 if (!status) { 426 ret = -EBUSY; 427 goto out; 428 } 429 430 if (data->soc == SOC_ARCH_EXYNOS3250 || 431 data->soc == SOC_ARCH_EXYNOS4412 || 432 data->soc == SOC_ARCH_EXYNOS5250) { 433 if (data->soc == SOC_ARCH_EXYNOS3250) { 434 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON1); 435 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE; 436 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON1); 437 } 438 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON2); 439 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE; 440 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON2); 441 } 442 443 /* On exynos5420 the triminfo register is in the shared space */ 444 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) 445 trim_info = readl(data->base_second + EXYNOS_TMU_REG_TRIMINFO); 446 else 447 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); 448 449 sanitize_temp_error(data, trim_info); 450 451 /* Write temperature code for rising and falling threshold */ 452 rising_threshold = readl(data->base + EXYNOS_THD_TEMP_RISE); 453 rising_threshold = get_th_reg(data, rising_threshold, false); 454 writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE); 455 writel(get_th_reg(data, 0, true), data->base + EXYNOS_THD_TEMP_FALL); 456 457 data->tmu_clear_irqs(data); 458 459 /* if last threshold limit is also present */ 460 for (i = 0; i < of_thermal_get_ntrips(data->tzd); i++) { 461 if (trips[i].type == THERMAL_TRIP_CRITICAL) { 462 crit_temp = trips[i].temperature; 463 break; 464 } 465 } 466 467 if (i == of_thermal_get_ntrips(data->tzd)) { 468 pr_err("%s: No CRITICAL trip point defined at of-thermal.c!\n", 469 __func__); 470 ret = -EINVAL; 471 goto out; 472 } 473 474 threshold_code = temp_to_code(data, crit_temp / MCELSIUS); 475 /* 1-4 level to be assigned in th0 reg */ 476 rising_threshold &= ~(0xff << 8 * i); 477 rising_threshold |= threshold_code << 8 * i; 478 writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE); 479 con = readl(data->base + EXYNOS_TMU_REG_CONTROL); 480 con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT); 481 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 482 483out: 484 return ret; 485} 486 487static int exynos5440_tmu_initialize(struct platform_device *pdev) 488{ 489 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 490 unsigned int trim_info = 0, con, rising_threshold; 491 int ret = 0, threshold_code; 492 unsigned long crit_temp = 0; 493 494 /* 495 * For exynos5440 soc triminfo value is swapped between TMU0 and 496 * TMU2, so the below logic is needed. 497 */ 498 switch (data->id) { 499 case 0: 500 trim_info = readl(data->base + EXYNOS5440_EFUSE_SWAP_OFFSET + 501 EXYNOS5440_TMU_S0_7_TRIM); 502 break; 503 case 1: 504 trim_info = readl(data->base + EXYNOS5440_TMU_S0_7_TRIM); 505 break; 506 case 2: 507 trim_info = readl(data->base - EXYNOS5440_EFUSE_SWAP_OFFSET + 508 EXYNOS5440_TMU_S0_7_TRIM); 509 } 510 sanitize_temp_error(data, trim_info); 511 512 /* Write temperature code for rising and falling threshold */ 513 rising_threshold = readl(data->base + EXYNOS5440_TMU_S0_7_TH0); 514 rising_threshold = get_th_reg(data, rising_threshold, false); 515 writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH0); 516 writel(0, data->base + EXYNOS5440_TMU_S0_7_TH1); 517 518 data->tmu_clear_irqs(data); 519 520 /* if last threshold limit is also present */ 521 if (!data->tzd->ops->get_crit_temp(data->tzd, &crit_temp)) { 522 threshold_code = temp_to_code(data, crit_temp / MCELSIUS); 523 /* 5th level to be assigned in th2 reg */ 524 rising_threshold = 525 threshold_code << EXYNOS5440_TMU_TH_RISE4_SHIFT; 526 writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH2); 527 con = readl(data->base + EXYNOS5440_TMU_S0_7_CTRL); 528 con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT); 529 writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL); 530 } 531 /* Clear the PMIN in the common TMU register */ 532 if (!data->id) 533 writel(0, data->base_second + EXYNOS5440_TMU_PMIN); 534 return ret; 535} 536 537static int exynos7_tmu_initialize(struct platform_device *pdev) 538{ 539 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 540 struct thermal_zone_device *tz = data->tzd; 541 struct exynos_tmu_platform_data *pdata = data->pdata; 542 unsigned int status, trim_info; 543 unsigned int rising_threshold = 0, falling_threshold = 0; 544 int ret = 0, threshold_code, i; 545 unsigned long temp, temp_hist; 546 unsigned int reg_off, bit_off; 547 548 status = readb(data->base + EXYNOS_TMU_REG_STATUS); 549 if (!status) { 550 ret = -EBUSY; 551 goto out; 552 } 553 554 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); 555 556 data->temp_error1 = trim_info & EXYNOS7_TMU_TEMP_MASK; 557 if (!data->temp_error1 || 558 (pdata->min_efuse_value > data->temp_error1) || 559 (data->temp_error1 > pdata->max_efuse_value)) 560 data->temp_error1 = pdata->efuse_value & EXYNOS_TMU_TEMP_MASK; 561 562 /* Write temperature code for rising and falling threshold */ 563 for (i = (of_thermal_get_ntrips(tz) - 1); i >= 0; i--) { 564 /* 565 * On exynos7 there are 4 rising and 4 falling threshold 566 * registers (0x50-0x5c and 0x60-0x6c respectively). Each 567 * register holds the value of two threshold levels (at bit 568 * offsets 0 and 16). Based on the fact that there are atmost 569 * eight possible trigger levels, calculate the register and 570 * bit offsets where the threshold levels are to be written. 571 * 572 * e.g. EXYNOS7_THD_TEMP_RISE7_6 (0x50) 573 * [24:16] - Threshold level 7 574 * [8:0] - Threshold level 6 575 * e.g. EXYNOS7_THD_TEMP_RISE5_4 (0x54) 576 * [24:16] - Threshold level 5 577 * [8:0] - Threshold level 4 578 * 579 * and similarly for falling thresholds. 580 * 581 * Based on the above, calculate the register and bit offsets 582 * for rising/falling threshold levels and populate them. 583 */ 584 reg_off = ((7 - i) / 2) * 4; 585 bit_off = ((8 - i) % 2); 586 587 tz->ops->get_trip_temp(tz, i, &temp); 588 temp /= MCELSIUS; 589 590 tz->ops->get_trip_hyst(tz, i, &temp_hist); 591 temp_hist = temp - (temp_hist / MCELSIUS); 592 593 /* Set 9-bit temperature code for rising threshold levels */ 594 threshold_code = temp_to_code(data, temp); 595 rising_threshold = readl(data->base + 596 EXYNOS7_THD_TEMP_RISE7_6 + reg_off); 597 rising_threshold &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off)); 598 rising_threshold |= threshold_code << (16 * bit_off); 599 writel(rising_threshold, 600 data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off); 601 602 /* Set 9-bit temperature code for falling threshold levels */ 603 threshold_code = temp_to_code(data, temp_hist); 604 falling_threshold &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off)); 605 falling_threshold |= threshold_code << (16 * bit_off); 606 writel(falling_threshold, 607 data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off); 608 } 609 610 data->tmu_clear_irqs(data); 611out: 612 return ret; 613} 614 615static void exynos4210_tmu_control(struct platform_device *pdev, bool on) 616{ 617 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 618 struct thermal_zone_device *tz = data->tzd; 619 unsigned int con, interrupt_en; 620 621 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); 622 623 if (on) { 624 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); 625 interrupt_en = 626 (of_thermal_is_trip_valid(tz, 3) 627 << EXYNOS_TMU_INTEN_RISE3_SHIFT) | 628 (of_thermal_is_trip_valid(tz, 2) 629 << EXYNOS_TMU_INTEN_RISE2_SHIFT) | 630 (of_thermal_is_trip_valid(tz, 1) 631 << EXYNOS_TMU_INTEN_RISE1_SHIFT) | 632 (of_thermal_is_trip_valid(tz, 0) 633 << EXYNOS_TMU_INTEN_RISE0_SHIFT); 634 635 if (data->soc != SOC_ARCH_EXYNOS4210) 636 interrupt_en |= 637 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; 638 } else { 639 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); 640 interrupt_en = 0; /* Disable all interrupts */ 641 } 642 writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN); 643 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 644} 645 646static void exynos5440_tmu_control(struct platform_device *pdev, bool on) 647{ 648 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 649 struct thermal_zone_device *tz = data->tzd; 650 unsigned int con, interrupt_en; 651 652 con = get_con_reg(data, readl(data->base + EXYNOS5440_TMU_S0_7_CTRL)); 653 654 if (on) { 655 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); 656 interrupt_en = 657 (of_thermal_is_trip_valid(tz, 3) 658 << EXYNOS5440_TMU_INTEN_RISE3_SHIFT) | 659 (of_thermal_is_trip_valid(tz, 2) 660 << EXYNOS5440_TMU_INTEN_RISE2_SHIFT) | 661 (of_thermal_is_trip_valid(tz, 1) 662 << EXYNOS5440_TMU_INTEN_RISE1_SHIFT) | 663 (of_thermal_is_trip_valid(tz, 0) 664 << EXYNOS5440_TMU_INTEN_RISE0_SHIFT); 665 interrupt_en |= 666 interrupt_en << EXYNOS5440_TMU_INTEN_FALL0_SHIFT; 667 } else { 668 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); 669 interrupt_en = 0; /* Disable all interrupts */ 670 } 671 writel(interrupt_en, data->base + EXYNOS5440_TMU_S0_7_IRQEN); 672 writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL); 673} 674 675static void exynos7_tmu_control(struct platform_device *pdev, bool on) 676{ 677 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 678 struct thermal_zone_device *tz = data->tzd; 679 unsigned int con, interrupt_en; 680 681 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); 682 683 if (on) { 684 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); 685 con |= (1 << EXYNOS7_PD_DET_EN_SHIFT); 686 interrupt_en = 687 (of_thermal_is_trip_valid(tz, 7) 688 << EXYNOS7_TMU_INTEN_RISE7_SHIFT) | 689 (of_thermal_is_trip_valid(tz, 6) 690 << EXYNOS7_TMU_INTEN_RISE6_SHIFT) | 691 (of_thermal_is_trip_valid(tz, 5) 692 << EXYNOS7_TMU_INTEN_RISE5_SHIFT) | 693 (of_thermal_is_trip_valid(tz, 4) 694 << EXYNOS7_TMU_INTEN_RISE4_SHIFT) | 695 (of_thermal_is_trip_valid(tz, 3) 696 << EXYNOS7_TMU_INTEN_RISE3_SHIFT) | 697 (of_thermal_is_trip_valid(tz, 2) 698 << EXYNOS7_TMU_INTEN_RISE2_SHIFT) | 699 (of_thermal_is_trip_valid(tz, 1) 700 << EXYNOS7_TMU_INTEN_RISE1_SHIFT) | 701 (of_thermal_is_trip_valid(tz, 0) 702 << EXYNOS7_TMU_INTEN_RISE0_SHIFT); 703 704 interrupt_en |= 705 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; 706 } else { 707 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); 708 con &= ~(1 << EXYNOS7_PD_DET_EN_SHIFT); 709 interrupt_en = 0; /* Disable all interrupts */ 710 } 711 712 writel(interrupt_en, data->base + EXYNOS7_TMU_REG_INTEN); 713 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 714} 715 716static int exynos_get_temp(void *p, long *temp) 717{ 718 struct exynos_tmu_data *data = p; 719 720 if (!data || !data->tmu_read) 721 return -EINVAL; 722 723 mutex_lock(&data->lock); 724 clk_enable(data->clk); 725 726 *temp = code_to_temp(data, data->tmu_read(data)) * MCELSIUS; 727 728 clk_disable(data->clk); 729 mutex_unlock(&data->lock); 730 731 return 0; 732} 733 734#ifdef CONFIG_THERMAL_EMULATION 735static u32 get_emul_con_reg(struct exynos_tmu_data *data, unsigned int val, 736 unsigned long temp) 737{ 738 if (temp) { 739 temp /= MCELSIUS; 740 741 if (data->soc != SOC_ARCH_EXYNOS5440) { 742 val &= ~(EXYNOS_EMUL_TIME_MASK << EXYNOS_EMUL_TIME_SHIFT); 743 val |= (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT); 744 } 745 if (data->soc == SOC_ARCH_EXYNOS7) { 746 val &= ~(EXYNOS7_EMUL_DATA_MASK << 747 EXYNOS7_EMUL_DATA_SHIFT); 748 val |= (temp_to_code(data, temp) << 749 EXYNOS7_EMUL_DATA_SHIFT) | 750 EXYNOS_EMUL_ENABLE; 751 } else { 752 val &= ~(EXYNOS_EMUL_DATA_MASK << 753 EXYNOS_EMUL_DATA_SHIFT); 754 val |= (temp_to_code(data, temp) << 755 EXYNOS_EMUL_DATA_SHIFT) | 756 EXYNOS_EMUL_ENABLE; 757 } 758 } else { 759 val &= ~EXYNOS_EMUL_ENABLE; 760 } 761 762 return val; 763} 764 765static void exynos4412_tmu_set_emulation(struct exynos_tmu_data *data, 766 unsigned long temp) 767{ 768 unsigned int val; 769 u32 emul_con; 770 771 if (data->soc == SOC_ARCH_EXYNOS5260) 772 emul_con = EXYNOS5260_EMUL_CON; 773 else if (data->soc == SOC_ARCH_EXYNOS7) 774 emul_con = EXYNOS7_TMU_REG_EMUL_CON; 775 else 776 emul_con = EXYNOS_EMUL_CON; 777 778 val = readl(data->base + emul_con); 779 val = get_emul_con_reg(data, val, temp); 780 writel(val, data->base + emul_con); 781} 782 783static void exynos5440_tmu_set_emulation(struct exynos_tmu_data *data, 784 unsigned long temp) 785{ 786 unsigned int val; 787 788 val = readl(data->base + EXYNOS5440_TMU_S0_7_DEBUG); 789 val = get_emul_con_reg(data, val, temp); 790 writel(val, data->base + EXYNOS5440_TMU_S0_7_DEBUG); 791} 792 793static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp) 794{ 795 struct exynos_tmu_data *data = drv_data; 796 int ret = -EINVAL; 797 798 if (data->soc == SOC_ARCH_EXYNOS4210) 799 goto out; 800 801 if (temp && temp < MCELSIUS) 802 goto out; 803 804 mutex_lock(&data->lock); 805 clk_enable(data->clk); 806 data->tmu_set_emulation(data, temp); 807 clk_disable(data->clk); 808 mutex_unlock(&data->lock); 809 return 0; 810out: 811 return ret; 812} 813#else 814#define exynos4412_tmu_set_emulation NULL 815#define exynos5440_tmu_set_emulation NULL 816static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp) 817 { return -EINVAL; } 818#endif /* CONFIG_THERMAL_EMULATION */ 819 820static int exynos4210_tmu_read(struct exynos_tmu_data *data) 821{ 822 int ret = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP); 823 824 /* "temp_code" should range between 75 and 175 */ 825 return (ret < 75 || ret > 175) ? -ENODATA : ret; 826} 827 828static int exynos4412_tmu_read(struct exynos_tmu_data *data) 829{ 830 return readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP); 831} 832 833static int exynos5440_tmu_read(struct exynos_tmu_data *data) 834{ 835 return readb(data->base + EXYNOS5440_TMU_S0_7_TEMP); 836} 837 838static int exynos7_tmu_read(struct exynos_tmu_data *data) 839{ 840 return readw(data->base + EXYNOS_TMU_REG_CURRENT_TEMP) & 841 EXYNOS7_TMU_TEMP_MASK; 842} 843 844static void exynos_tmu_work(struct work_struct *work) 845{ 846 struct exynos_tmu_data *data = container_of(work, 847 struct exynos_tmu_data, irq_work); 848 unsigned int val_type; 849 850 if (!IS_ERR(data->clk_sec)) 851 clk_enable(data->clk_sec); 852 /* Find which sensor generated this interrupt */ 853 if (data->soc == SOC_ARCH_EXYNOS5440) { 854 val_type = readl(data->base_second + EXYNOS5440_TMU_IRQ_STATUS); 855 if (!((val_type >> data->id) & 0x1)) 856 goto out; 857 } 858 if (!IS_ERR(data->clk_sec)) 859 clk_disable(data->clk_sec); 860 861 exynos_report_trigger(data); 862 mutex_lock(&data->lock); 863 clk_enable(data->clk); 864 865 /* TODO: take action based on particular interrupt */ 866 data->tmu_clear_irqs(data); 867 868 clk_disable(data->clk); 869 mutex_unlock(&data->lock); 870out: 871 enable_irq(data->irq); 872} 873 874static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data) 875{ 876 unsigned int val_irq; 877 u32 tmu_intstat, tmu_intclear; 878 879 if (data->soc == SOC_ARCH_EXYNOS5260) { 880 tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT; 881 tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR; 882 } else if (data->soc == SOC_ARCH_EXYNOS7) { 883 tmu_intstat = EXYNOS7_TMU_REG_INTPEND; 884 tmu_intclear = EXYNOS7_TMU_REG_INTPEND; 885 } else { 886 tmu_intstat = EXYNOS_TMU_REG_INTSTAT; 887 tmu_intclear = EXYNOS_TMU_REG_INTCLEAR; 888 } 889 890 val_irq = readl(data->base + tmu_intstat); 891 /* 892 * Clear the interrupts. Please note that the documentation for 893 * Exynos3250, Exynos4412, Exynos5250 and Exynos5260 incorrectly 894 * states that INTCLEAR register has a different placing of bits 895 * responsible for FALL IRQs than INTSTAT register. Exynos5420 896 * and Exynos5440 documentation is correct (Exynos4210 doesn't 897 * support FALL IRQs at all). 898 */ 899 writel(val_irq, data->base + tmu_intclear); 900} 901 902static void exynos5440_tmu_clear_irqs(struct exynos_tmu_data *data) 903{ 904 unsigned int val_irq; 905 906 val_irq = readl(data->base + EXYNOS5440_TMU_S0_7_IRQ); 907 /* clear the interrupts */ 908 writel(val_irq, data->base + EXYNOS5440_TMU_S0_7_IRQ); 909} 910 911static irqreturn_t exynos_tmu_irq(int irq, void *id) 912{ 913 struct exynos_tmu_data *data = id; 914 915 disable_irq_nosync(irq); 916 schedule_work(&data->irq_work); 917 918 return IRQ_HANDLED; 919} 920 921static const struct of_device_id exynos_tmu_match[] = { 922 { .compatible = "samsung,exynos3250-tmu", }, 923 { .compatible = "samsung,exynos4210-tmu", }, 924 { .compatible = "samsung,exynos4412-tmu", }, 925 { .compatible = "samsung,exynos5250-tmu", }, 926 { .compatible = "samsung,exynos5260-tmu", }, 927 { .compatible = "samsung,exynos5420-tmu", }, 928 { .compatible = "samsung,exynos5420-tmu-ext-triminfo", }, 929 { .compatible = "samsung,exynos5440-tmu", }, 930 { .compatible = "samsung,exynos7-tmu", }, 931 { /* sentinel */ }, 932}; 933MODULE_DEVICE_TABLE(of, exynos_tmu_match); 934 935static int exynos_of_get_soc_type(struct device_node *np) 936{ 937 if (of_device_is_compatible(np, "samsung,exynos3250-tmu")) 938 return SOC_ARCH_EXYNOS3250; 939 else if (of_device_is_compatible(np, "samsung,exynos4210-tmu")) 940 return SOC_ARCH_EXYNOS4210; 941 else if (of_device_is_compatible(np, "samsung,exynos4412-tmu")) 942 return SOC_ARCH_EXYNOS4412; 943 else if (of_device_is_compatible(np, "samsung,exynos5250-tmu")) 944 return SOC_ARCH_EXYNOS5250; 945 else if (of_device_is_compatible(np, "samsung,exynos5260-tmu")) 946 return SOC_ARCH_EXYNOS5260; 947 else if (of_device_is_compatible(np, "samsung,exynos5420-tmu")) 948 return SOC_ARCH_EXYNOS5420; 949 else if (of_device_is_compatible(np, 950 "samsung,exynos5420-tmu-ext-triminfo")) 951 return SOC_ARCH_EXYNOS5420_TRIMINFO; 952 else if (of_device_is_compatible(np, "samsung,exynos5440-tmu")) 953 return SOC_ARCH_EXYNOS5440; 954 else if (of_device_is_compatible(np, "samsung,exynos7-tmu")) 955 return SOC_ARCH_EXYNOS7; 956 957 return -EINVAL; 958} 959 960static int exynos_of_sensor_conf(struct device_node *np, 961 struct exynos_tmu_platform_data *pdata) 962{ 963 u32 value; 964 int ret; 965 966 of_node_get(np); 967 968 ret = of_property_read_u32(np, "samsung,tmu_gain", &value); 969 pdata->gain = (u8)value; 970 of_property_read_u32(np, "samsung,tmu_reference_voltage", &value); 971 pdata->reference_voltage = (u8)value; 972 of_property_read_u32(np, "samsung,tmu_noise_cancel_mode", &value); 973 pdata->noise_cancel_mode = (u8)value; 974 975 of_property_read_u32(np, "samsung,tmu_efuse_value", 976 &pdata->efuse_value); 977 of_property_read_u32(np, "samsung,tmu_min_efuse_value", 978 &pdata->min_efuse_value); 979 of_property_read_u32(np, "samsung,tmu_max_efuse_value", 980 &pdata->max_efuse_value); 981 982 of_property_read_u32(np, "samsung,tmu_first_point_trim", &value); 983 pdata->first_point_trim = (u8)value; 984 of_property_read_u32(np, "samsung,tmu_second_point_trim", &value); 985 pdata->second_point_trim = (u8)value; 986 of_property_read_u32(np, "samsung,tmu_default_temp_offset", &value); 987 pdata->default_temp_offset = (u8)value; 988 989 of_property_read_u32(np, "samsung,tmu_cal_type", &pdata->cal_type); 990 of_property_read_u32(np, "samsung,tmu_cal_mode", &pdata->cal_mode); 991 992 of_node_put(np); 993 return 0; 994} 995 996static int exynos_map_dt_data(struct platform_device *pdev) 997{ 998 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 999 struct exynos_tmu_platform_data *pdata; 1000 struct resource res; 1001 int ret; 1002 1003 if (!data || !pdev->dev.of_node) 1004 return -ENODEV; 1005 1006 /* 1007 * Try enabling the regulator if found 1008 * TODO: Add regulator as an SOC feature, so that regulator enable 1009 * is a compulsory call. 1010 */ 1011 data->regulator = devm_regulator_get(&pdev->dev, "vtmu"); 1012 if (!IS_ERR(data->regulator)) { 1013 ret = regulator_enable(data->regulator); 1014 if (ret) { 1015 dev_err(&pdev->dev, "failed to enable vtmu\n"); 1016 return ret; 1017 } 1018 } else { 1019 dev_info(&pdev->dev, "Regulator node (vtmu) not found\n"); 1020 } 1021 1022 data->id = of_alias_get_id(pdev->dev.of_node, "tmuctrl"); 1023 if (data->id < 0) 1024 data->id = 0; 1025 1026 data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 1027 if (data->irq <= 0) { 1028 dev_err(&pdev->dev, "failed to get IRQ\n"); 1029 return -ENODEV; 1030 } 1031 1032 if (of_address_to_resource(pdev->dev.of_node, 0, &res)) { 1033 dev_err(&pdev->dev, "failed to get Resource 0\n"); 1034 return -ENODEV; 1035 } 1036 1037 data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res)); 1038 if (!data->base) { 1039 dev_err(&pdev->dev, "Failed to ioremap memory\n"); 1040 return -EADDRNOTAVAIL; 1041 } 1042 1043 pdata = devm_kzalloc(&pdev->dev, 1044 sizeof(struct exynos_tmu_platform_data), 1045 GFP_KERNEL); 1046 if (!pdata) 1047 return -ENOMEM; 1048 1049 exynos_of_sensor_conf(pdev->dev.of_node, pdata); 1050 data->pdata = pdata; 1051 data->soc = exynos_of_get_soc_type(pdev->dev.of_node); 1052 1053 switch (data->soc) { 1054 case SOC_ARCH_EXYNOS4210: 1055 data->tmu_initialize = exynos4210_tmu_initialize; 1056 data->tmu_control = exynos4210_tmu_control; 1057 data->tmu_read = exynos4210_tmu_read; 1058 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 1059 break; 1060 case SOC_ARCH_EXYNOS3250: 1061 case SOC_ARCH_EXYNOS4412: 1062 case SOC_ARCH_EXYNOS5250: 1063 case SOC_ARCH_EXYNOS5260: 1064 case SOC_ARCH_EXYNOS5420: 1065 case SOC_ARCH_EXYNOS5420_TRIMINFO: 1066 data->tmu_initialize = exynos4412_tmu_initialize; 1067 data->tmu_control = exynos4210_tmu_control; 1068 data->tmu_read = exynos4412_tmu_read; 1069 data->tmu_set_emulation = exynos4412_tmu_set_emulation; 1070 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 1071 break; 1072 case SOC_ARCH_EXYNOS5440: 1073 data->tmu_initialize = exynos5440_tmu_initialize; 1074 data->tmu_control = exynos5440_tmu_control; 1075 data->tmu_read = exynos5440_tmu_read; 1076 data->tmu_set_emulation = exynos5440_tmu_set_emulation; 1077 data->tmu_clear_irqs = exynos5440_tmu_clear_irqs; 1078 break; 1079 case SOC_ARCH_EXYNOS7: 1080 data->tmu_initialize = exynos7_tmu_initialize; 1081 data->tmu_control = exynos7_tmu_control; 1082 data->tmu_read = exynos7_tmu_read; 1083 data->tmu_set_emulation = exynos4412_tmu_set_emulation; 1084 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 1085 break; 1086 default: 1087 dev_err(&pdev->dev, "Platform not supported\n"); 1088 return -EINVAL; 1089 } 1090 1091 /* 1092 * Check if the TMU shares some registers and then try to map the 1093 * memory of common registers. 1094 */ 1095 if (data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO && 1096 data->soc != SOC_ARCH_EXYNOS5440) 1097 return 0; 1098 1099 if (of_address_to_resource(pdev->dev.of_node, 1, &res)) { 1100 dev_err(&pdev->dev, "failed to get Resource 1\n"); 1101 return -ENODEV; 1102 } 1103 1104 data->base_second = devm_ioremap(&pdev->dev, res.start, 1105 resource_size(&res)); 1106 if (!data->base_second) { 1107 dev_err(&pdev->dev, "Failed to ioremap memory\n"); 1108 return -ENOMEM; 1109 } 1110 1111 return 0; 1112} 1113 1114static struct thermal_zone_of_device_ops exynos_sensor_ops = { 1115 .get_temp = exynos_get_temp, 1116 .set_emul_temp = exynos_tmu_set_emulation, 1117}; 1118 1119static int exynos_tmu_probe(struct platform_device *pdev) 1120{ 1121 struct exynos_tmu_platform_data *pdata; 1122 struct exynos_tmu_data *data; 1123 int ret; 1124 1125 data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data), 1126 GFP_KERNEL); 1127 if (!data) 1128 return -ENOMEM; 1129 1130 platform_set_drvdata(pdev, data); 1131 mutex_init(&data->lock); 1132 1133 data->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, data, 1134 &exynos_sensor_ops); 1135 if (IS_ERR(data->tzd)) { 1136 pr_err("thermal: tz: %p ERROR\n", data->tzd); 1137 return PTR_ERR(data->tzd); 1138 } 1139 ret = exynos_map_dt_data(pdev); 1140 if (ret) 1141 goto err_sensor; 1142 1143 pdata = data->pdata; 1144 1145 INIT_WORK(&data->irq_work, exynos_tmu_work); 1146 1147 data->clk = devm_clk_get(&pdev->dev, "tmu_apbif"); 1148 if (IS_ERR(data->clk)) { 1149 dev_err(&pdev->dev, "Failed to get clock\n"); 1150 ret = PTR_ERR(data->clk); 1151 goto err_sensor; 1152 } 1153 1154 data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif"); 1155 if (IS_ERR(data->clk_sec)) { 1156 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) { 1157 dev_err(&pdev->dev, "Failed to get triminfo clock\n"); 1158 ret = PTR_ERR(data->clk_sec); 1159 goto err_sensor; 1160 } 1161 } else { 1162 ret = clk_prepare(data->clk_sec); 1163 if (ret) { 1164 dev_err(&pdev->dev, "Failed to get clock\n"); 1165 goto err_sensor; 1166 } 1167 } 1168 1169 ret = clk_prepare(data->clk); 1170 if (ret) { 1171 dev_err(&pdev->dev, "Failed to get clock\n"); 1172 goto err_clk_sec; 1173 } 1174 1175 if (data->soc == SOC_ARCH_EXYNOS7) { 1176 data->sclk = devm_clk_get(&pdev->dev, "tmu_sclk"); 1177 if (IS_ERR(data->sclk)) { 1178 dev_err(&pdev->dev, "Failed to get sclk\n"); 1179 goto err_clk; 1180 } else { 1181 ret = clk_prepare_enable(data->sclk); 1182 if (ret) { 1183 dev_err(&pdev->dev, "Failed to enable sclk\n"); 1184 goto err_clk; 1185 } 1186 } 1187 } 1188 1189 ret = exynos_tmu_initialize(pdev); 1190 if (ret) { 1191 dev_err(&pdev->dev, "Failed to initialize TMU\n"); 1192 goto err_sclk; 1193 } 1194 1195 ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq, 1196 IRQF_TRIGGER_RISING | IRQF_SHARED, dev_name(&pdev->dev), data); 1197 if (ret) { 1198 dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq); 1199 goto err_sclk; 1200 } 1201 1202 exynos_tmu_control(pdev, true); 1203 return 0; 1204err_sclk: 1205 clk_disable_unprepare(data->sclk); 1206err_clk: 1207 clk_unprepare(data->clk); 1208err_clk_sec: 1209 if (!IS_ERR(data->clk_sec)) 1210 clk_unprepare(data->clk_sec); 1211err_sensor: 1212 if (!IS_ERR_OR_NULL(data->regulator)) 1213 regulator_disable(data->regulator); 1214 thermal_zone_of_sensor_unregister(&pdev->dev, data->tzd); 1215 1216 return ret; 1217} 1218 1219static int exynos_tmu_remove(struct platform_device *pdev) 1220{ 1221 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 1222 struct thermal_zone_device *tzd = data->tzd; 1223 1224 thermal_zone_of_sensor_unregister(&pdev->dev, tzd); 1225 exynos_tmu_control(pdev, false); 1226 1227 clk_disable_unprepare(data->sclk); 1228 clk_unprepare(data->clk); 1229 if (!IS_ERR(data->clk_sec)) 1230 clk_unprepare(data->clk_sec); 1231 1232 if (!IS_ERR(data->regulator)) 1233 regulator_disable(data->regulator); 1234 1235 return 0; 1236} 1237 1238#ifdef CONFIG_PM_SLEEP 1239static int exynos_tmu_suspend(struct device *dev) 1240{ 1241 exynos_tmu_control(to_platform_device(dev), false); 1242 1243 return 0; 1244} 1245 1246static int exynos_tmu_resume(struct device *dev) 1247{ 1248 struct platform_device *pdev = to_platform_device(dev); 1249 1250 exynos_tmu_initialize(pdev); 1251 exynos_tmu_control(pdev, true); 1252 1253 return 0; 1254} 1255 1256static SIMPLE_DEV_PM_OPS(exynos_tmu_pm, 1257 exynos_tmu_suspend, exynos_tmu_resume); 1258#define EXYNOS_TMU_PM (&exynos_tmu_pm) 1259#else 1260#define EXYNOS_TMU_PM NULL 1261#endif 1262 1263static struct platform_driver exynos_tmu_driver = { 1264 .driver = { 1265 .name = "exynos-tmu", 1266 .pm = EXYNOS_TMU_PM, 1267 .of_match_table = exynos_tmu_match, 1268 }, 1269 .probe = exynos_tmu_probe, 1270 .remove = exynos_tmu_remove, 1271}; 1272 1273module_platform_driver(exynos_tmu_driver); 1274 1275MODULE_DESCRIPTION("EXYNOS TMU Driver"); 1276MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>"); 1277MODULE_LICENSE("GPL"); 1278MODULE_ALIAS("platform:exynos-tmu"); 1279