1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Derived from many drivers using generic_serial interface. 7 * 8 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> 9 * 10 * Serial driver for BCM63xx integrated UART. 11 * 12 * Hardware flow control was _not_ tested since I only have RX/TX on 13 * my board. 14 */ 15 16#if defined(CONFIG_SERIAL_BCM63XX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 17#define SUPPORT_SYSRQ 18#endif 19 20#include <linux/kernel.h> 21#include <linux/platform_device.h> 22#include <linux/init.h> 23#include <linux/delay.h> 24#include <linux/module.h> 25#include <linux/console.h> 26#include <linux/clk.h> 27#include <linux/tty.h> 28#include <linux/tty_flip.h> 29#include <linux/sysrq.h> 30#include <linux/serial.h> 31#include <linux/serial_core.h> 32#include <linux/serial_bcm63xx.h> 33#include <linux/io.h> 34#include <linux/of.h> 35 36#define BCM63XX_NR_UARTS 2 37 38static struct uart_port ports[BCM63XX_NR_UARTS]; 39 40/* 41 * rx interrupt mask / stat 42 * 43 * mask: 44 * - rx fifo full 45 * - rx fifo above threshold 46 * - rx fifo not empty for too long 47 */ 48#define UART_RX_INT_MASK (UART_IR_MASK(UART_IR_RXOVER) | \ 49 UART_IR_MASK(UART_IR_RXTHRESH) | \ 50 UART_IR_MASK(UART_IR_RXTIMEOUT)) 51 52#define UART_RX_INT_STAT (UART_IR_STAT(UART_IR_RXOVER) | \ 53 UART_IR_STAT(UART_IR_RXTHRESH) | \ 54 UART_IR_STAT(UART_IR_RXTIMEOUT)) 55 56/* 57 * tx interrupt mask / stat 58 * 59 * mask: 60 * - tx fifo empty 61 * - tx fifo below threshold 62 */ 63#define UART_TX_INT_MASK (UART_IR_MASK(UART_IR_TXEMPTY) | \ 64 UART_IR_MASK(UART_IR_TXTRESH)) 65 66#define UART_TX_INT_STAT (UART_IR_STAT(UART_IR_TXEMPTY) | \ 67 UART_IR_STAT(UART_IR_TXTRESH)) 68 69/* 70 * external input interrupt 71 * 72 * mask: any edge on CTS, DCD 73 */ 74#define UART_EXTINP_INT_MASK (UART_EXTINP_IRMASK(UART_EXTINP_IR_CTS) | \ 75 UART_EXTINP_IRMASK(UART_EXTINP_IR_DCD)) 76 77/* 78 * handy uart register accessor 79 */ 80static inline unsigned int bcm_uart_readl(struct uart_port *port, 81 unsigned int offset) 82{ 83 return __raw_readl(port->membase + offset); 84} 85 86static inline void bcm_uart_writel(struct uart_port *port, 87 unsigned int value, unsigned int offset) 88{ 89 __raw_writel(value, port->membase + offset); 90} 91 92/* 93 * serial core request to check if uart tx fifo is empty 94 */ 95static unsigned int bcm_uart_tx_empty(struct uart_port *port) 96{ 97 unsigned int val; 98 99 val = bcm_uart_readl(port, UART_IR_REG); 100 return (val & UART_IR_STAT(UART_IR_TXEMPTY)) ? 1 : 0; 101} 102 103/* 104 * serial core request to set RTS and DTR pin state and loopback mode 105 */ 106static void bcm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 107{ 108 unsigned int val; 109 110 val = bcm_uart_readl(port, UART_MCTL_REG); 111 val &= ~(UART_MCTL_DTR_MASK | UART_MCTL_RTS_MASK); 112 /* invert of written value is reflected on the pin */ 113 if (!(mctrl & TIOCM_DTR)) 114 val |= UART_MCTL_DTR_MASK; 115 if (!(mctrl & TIOCM_RTS)) 116 val |= UART_MCTL_RTS_MASK; 117 bcm_uart_writel(port, val, UART_MCTL_REG); 118 119 val = bcm_uart_readl(port, UART_CTL_REG); 120 if (mctrl & TIOCM_LOOP) 121 val |= UART_CTL_LOOPBACK_MASK; 122 else 123 val &= ~UART_CTL_LOOPBACK_MASK; 124 bcm_uart_writel(port, val, UART_CTL_REG); 125} 126 127/* 128 * serial core request to return RI, CTS, DCD and DSR pin state 129 */ 130static unsigned int bcm_uart_get_mctrl(struct uart_port *port) 131{ 132 unsigned int val, mctrl; 133 134 mctrl = 0; 135 val = bcm_uart_readl(port, UART_EXTINP_REG); 136 if (val & UART_EXTINP_RI_MASK) 137 mctrl |= TIOCM_RI; 138 if (val & UART_EXTINP_CTS_MASK) 139 mctrl |= TIOCM_CTS; 140 if (val & UART_EXTINP_DCD_MASK) 141 mctrl |= TIOCM_CD; 142 if (val & UART_EXTINP_DSR_MASK) 143 mctrl |= TIOCM_DSR; 144 return mctrl; 145} 146 147/* 148 * serial core request to disable tx ASAP (used for flow control) 149 */ 150static void bcm_uart_stop_tx(struct uart_port *port) 151{ 152 unsigned int val; 153 154 val = bcm_uart_readl(port, UART_CTL_REG); 155 val &= ~(UART_CTL_TXEN_MASK); 156 bcm_uart_writel(port, val, UART_CTL_REG); 157 158 val = bcm_uart_readl(port, UART_IR_REG); 159 val &= ~UART_TX_INT_MASK; 160 bcm_uart_writel(port, val, UART_IR_REG); 161} 162 163/* 164 * serial core request to (re)enable tx 165 */ 166static void bcm_uart_start_tx(struct uart_port *port) 167{ 168 unsigned int val; 169 170 val = bcm_uart_readl(port, UART_IR_REG); 171 val |= UART_TX_INT_MASK; 172 bcm_uart_writel(port, val, UART_IR_REG); 173 174 val = bcm_uart_readl(port, UART_CTL_REG); 175 val |= UART_CTL_TXEN_MASK; 176 bcm_uart_writel(port, val, UART_CTL_REG); 177} 178 179/* 180 * serial core request to stop rx, called before port shutdown 181 */ 182static void bcm_uart_stop_rx(struct uart_port *port) 183{ 184 unsigned int val; 185 186 val = bcm_uart_readl(port, UART_IR_REG); 187 val &= ~UART_RX_INT_MASK; 188 bcm_uart_writel(port, val, UART_IR_REG); 189} 190 191/* 192 * serial core request to enable modem status interrupt reporting 193 */ 194static void bcm_uart_enable_ms(struct uart_port *port) 195{ 196 unsigned int val; 197 198 val = bcm_uart_readl(port, UART_IR_REG); 199 val |= UART_IR_MASK(UART_IR_EXTIP); 200 bcm_uart_writel(port, val, UART_IR_REG); 201} 202 203/* 204 * serial core request to start/stop emitting break char 205 */ 206static void bcm_uart_break_ctl(struct uart_port *port, int ctl) 207{ 208 unsigned long flags; 209 unsigned int val; 210 211 spin_lock_irqsave(&port->lock, flags); 212 213 val = bcm_uart_readl(port, UART_CTL_REG); 214 if (ctl) 215 val |= UART_CTL_XMITBRK_MASK; 216 else 217 val &= ~UART_CTL_XMITBRK_MASK; 218 bcm_uart_writel(port, val, UART_CTL_REG); 219 220 spin_unlock_irqrestore(&port->lock, flags); 221} 222 223/* 224 * return port type in string format 225 */ 226static const char *bcm_uart_type(struct uart_port *port) 227{ 228 return (port->type == PORT_BCM63XX) ? "bcm63xx_uart" : NULL; 229} 230 231/* 232 * read all chars in rx fifo and send them to core 233 */ 234static void bcm_uart_do_rx(struct uart_port *port) 235{ 236 struct tty_port *tty_port = &port->state->port; 237 unsigned int max_count; 238 239 /* limit number of char read in interrupt, should not be 240 * higher than fifo size anyway since we're much faster than 241 * serial port */ 242 max_count = 32; 243 do { 244 unsigned int iestat, c, cstat; 245 char flag; 246 247 /* get overrun/fifo empty information from ier 248 * register */ 249 iestat = bcm_uart_readl(port, UART_IR_REG); 250 251 if (unlikely(iestat & UART_IR_STAT(UART_IR_RXOVER))) { 252 unsigned int val; 253 254 /* fifo reset is required to clear 255 * interrupt */ 256 val = bcm_uart_readl(port, UART_CTL_REG); 257 val |= UART_CTL_RSTRXFIFO_MASK; 258 bcm_uart_writel(port, val, UART_CTL_REG); 259 260 port->icount.overrun++; 261 tty_insert_flip_char(tty_port, 0, TTY_OVERRUN); 262 } 263 264 if (!(iestat & UART_IR_STAT(UART_IR_RXNOTEMPTY))) 265 break; 266 267 cstat = c = bcm_uart_readl(port, UART_FIFO_REG); 268 port->icount.rx++; 269 flag = TTY_NORMAL; 270 c &= 0xff; 271 272 if (unlikely((cstat & UART_FIFO_ANYERR_MASK))) { 273 /* do stats first */ 274 if (cstat & UART_FIFO_BRKDET_MASK) { 275 port->icount.brk++; 276 if (uart_handle_break(port)) 277 continue; 278 } 279 280 if (cstat & UART_FIFO_PARERR_MASK) 281 port->icount.parity++; 282 if (cstat & UART_FIFO_FRAMEERR_MASK) 283 port->icount.frame++; 284 285 /* update flag wrt read_status_mask */ 286 cstat &= port->read_status_mask; 287 if (cstat & UART_FIFO_BRKDET_MASK) 288 flag = TTY_BREAK; 289 if (cstat & UART_FIFO_FRAMEERR_MASK) 290 flag = TTY_FRAME; 291 if (cstat & UART_FIFO_PARERR_MASK) 292 flag = TTY_PARITY; 293 } 294 295 if (uart_handle_sysrq_char(port, c)) 296 continue; 297 298 299 if ((cstat & port->ignore_status_mask) == 0) 300 tty_insert_flip_char(tty_port, c, flag); 301 302 } while (--max_count); 303 304 spin_unlock(&port->lock); 305 tty_flip_buffer_push(tty_port); 306 spin_lock(&port->lock); 307} 308 309/* 310 * fill tx fifo with chars to send, stop when fifo is about to be full 311 * or when all chars have been sent. 312 */ 313static void bcm_uart_do_tx(struct uart_port *port) 314{ 315 struct circ_buf *xmit; 316 unsigned int val, max_count; 317 318 if (port->x_char) { 319 bcm_uart_writel(port, port->x_char, UART_FIFO_REG); 320 port->icount.tx++; 321 port->x_char = 0; 322 return; 323 } 324 325 if (uart_tx_stopped(port)) { 326 bcm_uart_stop_tx(port); 327 return; 328 } 329 330 xmit = &port->state->xmit; 331 if (uart_circ_empty(xmit)) 332 goto txq_empty; 333 334 val = bcm_uart_readl(port, UART_MCTL_REG); 335 val = (val & UART_MCTL_TXFIFOFILL_MASK) >> UART_MCTL_TXFIFOFILL_SHIFT; 336 max_count = port->fifosize - val; 337 338 while (max_count--) { 339 unsigned int c; 340 341 c = xmit->buf[xmit->tail]; 342 bcm_uart_writel(port, c, UART_FIFO_REG); 343 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 344 port->icount.tx++; 345 if (uart_circ_empty(xmit)) 346 break; 347 } 348 349 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 350 uart_write_wakeup(port); 351 352 if (uart_circ_empty(xmit)) 353 goto txq_empty; 354 return; 355 356txq_empty: 357 /* nothing to send, disable transmit interrupt */ 358 val = bcm_uart_readl(port, UART_IR_REG); 359 val &= ~UART_TX_INT_MASK; 360 bcm_uart_writel(port, val, UART_IR_REG); 361 return; 362} 363 364/* 365 * process uart interrupt 366 */ 367static irqreturn_t bcm_uart_interrupt(int irq, void *dev_id) 368{ 369 struct uart_port *port; 370 unsigned int irqstat; 371 372 port = dev_id; 373 spin_lock(&port->lock); 374 375 irqstat = bcm_uart_readl(port, UART_IR_REG); 376 if (irqstat & UART_RX_INT_STAT) 377 bcm_uart_do_rx(port); 378 379 if (irqstat & UART_TX_INT_STAT) 380 bcm_uart_do_tx(port); 381 382 if (irqstat & UART_IR_MASK(UART_IR_EXTIP)) { 383 unsigned int estat; 384 385 estat = bcm_uart_readl(port, UART_EXTINP_REG); 386 if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_CTS)) 387 uart_handle_cts_change(port, 388 estat & UART_EXTINP_CTS_MASK); 389 if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_DCD)) 390 uart_handle_dcd_change(port, 391 estat & UART_EXTINP_DCD_MASK); 392 } 393 394 spin_unlock(&port->lock); 395 return IRQ_HANDLED; 396} 397 398/* 399 * enable rx & tx operation on uart 400 */ 401static void bcm_uart_enable(struct uart_port *port) 402{ 403 unsigned int val; 404 405 val = bcm_uart_readl(port, UART_CTL_REG); 406 val |= (UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK); 407 bcm_uart_writel(port, val, UART_CTL_REG); 408} 409 410/* 411 * disable rx & tx operation on uart 412 */ 413static void bcm_uart_disable(struct uart_port *port) 414{ 415 unsigned int val; 416 417 val = bcm_uart_readl(port, UART_CTL_REG); 418 val &= ~(UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK | 419 UART_CTL_RXEN_MASK); 420 bcm_uart_writel(port, val, UART_CTL_REG); 421} 422 423/* 424 * clear all unread data in rx fifo and unsent data in tx fifo 425 */ 426static void bcm_uart_flush(struct uart_port *port) 427{ 428 unsigned int val; 429 430 /* empty rx and tx fifo */ 431 val = bcm_uart_readl(port, UART_CTL_REG); 432 val |= UART_CTL_RSTRXFIFO_MASK | UART_CTL_RSTTXFIFO_MASK; 433 bcm_uart_writel(port, val, UART_CTL_REG); 434 435 /* read any pending char to make sure all irq status are 436 * cleared */ 437 (void)bcm_uart_readl(port, UART_FIFO_REG); 438} 439 440/* 441 * serial core request to initialize uart and start rx operation 442 */ 443static int bcm_uart_startup(struct uart_port *port) 444{ 445 unsigned int val; 446 int ret; 447 448 /* mask all irq and flush port */ 449 bcm_uart_disable(port); 450 bcm_uart_writel(port, 0, UART_IR_REG); 451 bcm_uart_flush(port); 452 453 /* clear any pending external input interrupt */ 454 (void)bcm_uart_readl(port, UART_EXTINP_REG); 455 456 /* set rx/tx fifo thresh to fifo half size */ 457 val = bcm_uart_readl(port, UART_MCTL_REG); 458 val &= ~(UART_MCTL_RXFIFOTHRESH_MASK | UART_MCTL_TXFIFOTHRESH_MASK); 459 val |= (port->fifosize / 2) << UART_MCTL_RXFIFOTHRESH_SHIFT; 460 val |= (port->fifosize / 2) << UART_MCTL_TXFIFOTHRESH_SHIFT; 461 bcm_uart_writel(port, val, UART_MCTL_REG); 462 463 /* set rx fifo timeout to 1 char time */ 464 val = bcm_uart_readl(port, UART_CTL_REG); 465 val &= ~UART_CTL_RXTMOUTCNT_MASK; 466 val |= 1 << UART_CTL_RXTMOUTCNT_SHIFT; 467 bcm_uart_writel(port, val, UART_CTL_REG); 468 469 /* report any edge on dcd and cts */ 470 val = UART_EXTINP_INT_MASK; 471 val |= UART_EXTINP_DCD_NOSENSE_MASK; 472 val |= UART_EXTINP_CTS_NOSENSE_MASK; 473 bcm_uart_writel(port, val, UART_EXTINP_REG); 474 475 /* register irq and enable rx interrupts */ 476 ret = request_irq(port->irq, bcm_uart_interrupt, 0, 477 bcm_uart_type(port), port); 478 if (ret) 479 return ret; 480 bcm_uart_writel(port, UART_RX_INT_MASK, UART_IR_REG); 481 bcm_uart_enable(port); 482 return 0; 483} 484 485/* 486 * serial core request to flush & disable uart 487 */ 488static void bcm_uart_shutdown(struct uart_port *port) 489{ 490 unsigned long flags; 491 492 spin_lock_irqsave(&port->lock, flags); 493 bcm_uart_writel(port, 0, UART_IR_REG); 494 spin_unlock_irqrestore(&port->lock, flags); 495 496 bcm_uart_disable(port); 497 bcm_uart_flush(port); 498 free_irq(port->irq, port); 499} 500 501/* 502 * serial core request to change current uart setting 503 */ 504static void bcm_uart_set_termios(struct uart_port *port, 505 struct ktermios *new, 506 struct ktermios *old) 507{ 508 unsigned int ctl, baud, quot, ier; 509 unsigned long flags; 510 511 spin_lock_irqsave(&port->lock, flags); 512 513 /* disable uart while changing speed */ 514 bcm_uart_disable(port); 515 bcm_uart_flush(port); 516 517 /* update Control register */ 518 ctl = bcm_uart_readl(port, UART_CTL_REG); 519 ctl &= ~UART_CTL_BITSPERSYM_MASK; 520 521 switch (new->c_cflag & CSIZE) { 522 case CS5: 523 ctl |= (0 << UART_CTL_BITSPERSYM_SHIFT); 524 break; 525 case CS6: 526 ctl |= (1 << UART_CTL_BITSPERSYM_SHIFT); 527 break; 528 case CS7: 529 ctl |= (2 << UART_CTL_BITSPERSYM_SHIFT); 530 break; 531 default: 532 ctl |= (3 << UART_CTL_BITSPERSYM_SHIFT); 533 break; 534 } 535 536 ctl &= ~UART_CTL_STOPBITS_MASK; 537 if (new->c_cflag & CSTOPB) 538 ctl |= UART_CTL_STOPBITS_2; 539 else 540 ctl |= UART_CTL_STOPBITS_1; 541 542 ctl &= ~(UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK); 543 if (new->c_cflag & PARENB) 544 ctl |= (UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK); 545 ctl &= ~(UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK); 546 if (new->c_cflag & PARODD) 547 ctl |= (UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK); 548 bcm_uart_writel(port, ctl, UART_CTL_REG); 549 550 /* update Baudword register */ 551 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); 552 quot = uart_get_divisor(port, baud) - 1; 553 bcm_uart_writel(port, quot, UART_BAUD_REG); 554 555 /* update Interrupt register */ 556 ier = bcm_uart_readl(port, UART_IR_REG); 557 558 ier &= ~UART_IR_MASK(UART_IR_EXTIP); 559 if (UART_ENABLE_MS(port, new->c_cflag)) 560 ier |= UART_IR_MASK(UART_IR_EXTIP); 561 562 bcm_uart_writel(port, ier, UART_IR_REG); 563 564 /* update read/ignore mask */ 565 port->read_status_mask = UART_FIFO_VALID_MASK; 566 if (new->c_iflag & INPCK) { 567 port->read_status_mask |= UART_FIFO_FRAMEERR_MASK; 568 port->read_status_mask |= UART_FIFO_PARERR_MASK; 569 } 570 if (new->c_iflag & (IGNBRK | BRKINT)) 571 port->read_status_mask |= UART_FIFO_BRKDET_MASK; 572 573 port->ignore_status_mask = 0; 574 if (new->c_iflag & IGNPAR) 575 port->ignore_status_mask |= UART_FIFO_PARERR_MASK; 576 if (new->c_iflag & IGNBRK) 577 port->ignore_status_mask |= UART_FIFO_BRKDET_MASK; 578 if (!(new->c_cflag & CREAD)) 579 port->ignore_status_mask |= UART_FIFO_VALID_MASK; 580 581 uart_update_timeout(port, new->c_cflag, baud); 582 bcm_uart_enable(port); 583 spin_unlock_irqrestore(&port->lock, flags); 584} 585 586/* 587 * serial core request to claim uart iomem 588 */ 589static int bcm_uart_request_port(struct uart_port *port) 590{ 591 /* UARTs always present */ 592 return 0; 593} 594 595/* 596 * serial core request to release uart iomem 597 */ 598static void bcm_uart_release_port(struct uart_port *port) 599{ 600 /* Nothing to release ... */ 601} 602 603/* 604 * serial core request to do any port required autoconfiguration 605 */ 606static void bcm_uart_config_port(struct uart_port *port, int flags) 607{ 608 if (flags & UART_CONFIG_TYPE) { 609 if (bcm_uart_request_port(port)) 610 return; 611 port->type = PORT_BCM63XX; 612 } 613} 614 615/* 616 * serial core request to check that port information in serinfo are 617 * suitable 618 */ 619static int bcm_uart_verify_port(struct uart_port *port, 620 struct serial_struct *serinfo) 621{ 622 if (port->type != PORT_BCM63XX) 623 return -EINVAL; 624 if (port->irq != serinfo->irq) 625 return -EINVAL; 626 if (port->iotype != serinfo->io_type) 627 return -EINVAL; 628 if (port->mapbase != (unsigned long)serinfo->iomem_base) 629 return -EINVAL; 630 return 0; 631} 632 633/* serial core callbacks */ 634static struct uart_ops bcm_uart_ops = { 635 .tx_empty = bcm_uart_tx_empty, 636 .get_mctrl = bcm_uart_get_mctrl, 637 .set_mctrl = bcm_uart_set_mctrl, 638 .start_tx = bcm_uart_start_tx, 639 .stop_tx = bcm_uart_stop_tx, 640 .stop_rx = bcm_uart_stop_rx, 641 .enable_ms = bcm_uart_enable_ms, 642 .break_ctl = bcm_uart_break_ctl, 643 .startup = bcm_uart_startup, 644 .shutdown = bcm_uart_shutdown, 645 .set_termios = bcm_uart_set_termios, 646 .type = bcm_uart_type, 647 .release_port = bcm_uart_release_port, 648 .request_port = bcm_uart_request_port, 649 .config_port = bcm_uart_config_port, 650 .verify_port = bcm_uart_verify_port, 651}; 652 653 654 655#ifdef CONFIG_SERIAL_BCM63XX_CONSOLE 656static inline void wait_for_xmitr(struct uart_port *port) 657{ 658 unsigned int tmout; 659 660 /* Wait up to 10ms for the character(s) to be sent. */ 661 tmout = 10000; 662 while (--tmout) { 663 unsigned int val; 664 665 val = bcm_uart_readl(port, UART_IR_REG); 666 if (val & UART_IR_STAT(UART_IR_TXEMPTY)) 667 break; 668 udelay(1); 669 } 670 671 /* Wait up to 1s for flow control if necessary */ 672 if (port->flags & UPF_CONS_FLOW) { 673 tmout = 1000000; 674 while (--tmout) { 675 unsigned int val; 676 677 val = bcm_uart_readl(port, UART_EXTINP_REG); 678 if (val & UART_EXTINP_CTS_MASK) 679 break; 680 udelay(1); 681 } 682 } 683} 684 685/* 686 * output given char 687 */ 688static void bcm_console_putchar(struct uart_port *port, int ch) 689{ 690 wait_for_xmitr(port); 691 bcm_uart_writel(port, ch, UART_FIFO_REG); 692} 693 694/* 695 * console core request to output given string 696 */ 697static void bcm_console_write(struct console *co, const char *s, 698 unsigned int count) 699{ 700 struct uart_port *port; 701 unsigned long flags; 702 int locked; 703 704 port = &ports[co->index]; 705 706 local_irq_save(flags); 707 if (port->sysrq) { 708 /* bcm_uart_interrupt() already took the lock */ 709 locked = 0; 710 } else if (oops_in_progress) { 711 locked = spin_trylock(&port->lock); 712 } else { 713 spin_lock(&port->lock); 714 locked = 1; 715 } 716 717 /* call helper to deal with \r\n */ 718 uart_console_write(port, s, count, bcm_console_putchar); 719 720 /* and wait for char to be transmitted */ 721 wait_for_xmitr(port); 722 723 if (locked) 724 spin_unlock(&port->lock); 725 local_irq_restore(flags); 726} 727 728/* 729 * console core request to setup given console, find matching uart 730 * port and setup it. 731 */ 732static int bcm_console_setup(struct console *co, char *options) 733{ 734 struct uart_port *port; 735 int baud = 9600; 736 int bits = 8; 737 int parity = 'n'; 738 int flow = 'n'; 739 740 if (co->index < 0 || co->index >= BCM63XX_NR_UARTS) 741 return -EINVAL; 742 port = &ports[co->index]; 743 if (!port->membase) 744 return -ENODEV; 745 if (options) 746 uart_parse_options(options, &baud, &parity, &bits, &flow); 747 748 return uart_set_options(port, co, baud, parity, bits, flow); 749} 750 751static struct uart_driver bcm_uart_driver; 752 753static struct console bcm63xx_console = { 754 .name = "ttyS", 755 .write = bcm_console_write, 756 .device = uart_console_device, 757 .setup = bcm_console_setup, 758 .flags = CON_PRINTBUFFER, 759 .index = -1, 760 .data = &bcm_uart_driver, 761}; 762 763static int __init bcm63xx_console_init(void) 764{ 765 register_console(&bcm63xx_console); 766 return 0; 767} 768 769console_initcall(bcm63xx_console_init); 770 771static void bcm_early_write(struct console *con, const char *s, unsigned n) 772{ 773 struct earlycon_device *dev = con->data; 774 775 uart_console_write(&dev->port, s, n, bcm_console_putchar); 776 wait_for_xmitr(&dev->port); 777} 778 779static int __init bcm_early_console_setup(struct earlycon_device *device, 780 const char *opt) 781{ 782 if (!device->port.membase) 783 return -ENODEV; 784 785 device->con->write = bcm_early_write; 786 return 0; 787} 788 789OF_EARLYCON_DECLARE(bcm63xx_uart, "brcm,bcm6345-uart", bcm_early_console_setup); 790 791#define BCM63XX_CONSOLE (&bcm63xx_console) 792#else 793#define BCM63XX_CONSOLE NULL 794#endif /* CONFIG_SERIAL_BCM63XX_CONSOLE */ 795 796static struct uart_driver bcm_uart_driver = { 797 .owner = THIS_MODULE, 798 .driver_name = "bcm63xx_uart", 799 .dev_name = "ttyS", 800 .major = TTY_MAJOR, 801 .minor = 64, 802 .nr = BCM63XX_NR_UARTS, 803 .cons = BCM63XX_CONSOLE, 804}; 805 806/* 807 * platform driver probe/remove callback 808 */ 809static int bcm_uart_probe(struct platform_device *pdev) 810{ 811 struct resource *res_mem, *res_irq; 812 struct uart_port *port; 813 struct clk *clk; 814 int ret; 815 816 if (pdev->dev.of_node) 817 pdev->id = of_alias_get_id(pdev->dev.of_node, "uart"); 818 819 if (pdev->id < 0 || pdev->id >= BCM63XX_NR_UARTS) 820 return -EINVAL; 821 822 port = &ports[pdev->id]; 823 if (port->membase) 824 return -EBUSY; 825 memset(port, 0, sizeof(*port)); 826 827 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 828 if (!res_mem) 829 return -ENODEV; 830 831 port->mapbase = res_mem->start; 832 port->membase = devm_ioremap_resource(&pdev->dev, res_mem); 833 if (IS_ERR(port->membase)) 834 return PTR_ERR(port->membase); 835 836 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 837 if (!res_irq) 838 return -ENODEV; 839 840 clk = pdev->dev.of_node ? of_clk_get(pdev->dev.of_node, 0) : 841 clk_get(&pdev->dev, "periph"); 842 if (IS_ERR(clk)) 843 return -ENODEV; 844 845 port->iotype = UPIO_MEM; 846 port->irq = res_irq->start; 847 port->ops = &bcm_uart_ops; 848 port->flags = UPF_BOOT_AUTOCONF; 849 port->dev = &pdev->dev; 850 port->fifosize = 16; 851 port->uartclk = clk_get_rate(clk) / 2; 852 port->line = pdev->id; 853 clk_put(clk); 854 855 ret = uart_add_one_port(&bcm_uart_driver, port); 856 if (ret) { 857 ports[pdev->id].membase = NULL; 858 return ret; 859 } 860 platform_set_drvdata(pdev, port); 861 return 0; 862} 863 864static int bcm_uart_remove(struct platform_device *pdev) 865{ 866 struct uart_port *port; 867 868 port = platform_get_drvdata(pdev); 869 uart_remove_one_port(&bcm_uart_driver, port); 870 /* mark port as free */ 871 ports[pdev->id].membase = NULL; 872 return 0; 873} 874 875static const struct of_device_id bcm63xx_of_match[] = { 876 { .compatible = "brcm,bcm6345-uart" }, 877 { /* sentinel */ } 878}; 879MODULE_DEVICE_TABLE(of, bcm63xx_of_match); 880 881/* 882 * platform driver stuff 883 */ 884static struct platform_driver bcm_uart_platform_driver = { 885 .probe = bcm_uart_probe, 886 .remove = bcm_uart_remove, 887 .driver = { 888 .name = "bcm63xx_uart", 889 .of_match_table = bcm63xx_of_match, 890 }, 891}; 892 893static int __init bcm_uart_init(void) 894{ 895 int ret; 896 897 ret = uart_register_driver(&bcm_uart_driver); 898 if (ret) 899 return ret; 900 901 ret = platform_driver_register(&bcm_uart_platform_driver); 902 if (ret) 903 uart_unregister_driver(&bcm_uart_driver); 904 905 return ret; 906} 907 908static void __exit bcm_uart_exit(void) 909{ 910 platform_driver_unregister(&bcm_uart_platform_driver); 911 uart_unregister_driver(&bcm_uart_driver); 912} 913 914module_init(bcm_uart_init); 915module_exit(bcm_uart_exit); 916 917MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>"); 918MODULE_DESCRIPTION("Broadcom 63xx integrated uart driver"); 919MODULE_LICENSE("GPL"); 920