1/* 2 * Copyright (C) 2004,2012 Freescale Semiconductor, Inc 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 * 10 * Freescale USB device/endpoint management registers 11 */ 12#ifndef __FSL_USB2_UDC_H 13#define __FSL_USB2_UDC_H 14 15#include <linux/usb/ch9.h> 16#include <linux/usb/gadget.h> 17 18/* ### define USB registers here 19 */ 20#define USB_MAX_CTRL_PAYLOAD 64 21#define USB_DR_SYS_OFFSET 0x400 22 23 /* USB DR device mode registers (Little Endian) */ 24struct usb_dr_device { 25 /* Capability register */ 26 u8 res1[256]; 27 u16 caplength; /* Capability Register Length */ 28 u16 hciversion; /* Host Controller Interface Version */ 29 u32 hcsparams; /* Host Controller Structural Parameters */ 30 u32 hccparams; /* Host Controller Capability Parameters */ 31 u8 res2[20]; 32 u32 dciversion; /* Device Controller Interface Version */ 33 u32 dccparams; /* Device Controller Capability Parameters */ 34 u8 res3[24]; 35 /* Operation register */ 36 u32 usbcmd; /* USB Command Register */ 37 u32 usbsts; /* USB Status Register */ 38 u32 usbintr; /* USB Interrupt Enable Register */ 39 u32 frindex; /* Frame Index Register */ 40 u8 res4[4]; 41 u32 deviceaddr; /* Device Address */ 42 u32 endpointlistaddr; /* Endpoint List Address Register */ 43 u8 res5[4]; 44 u32 burstsize; /* Master Interface Data Burst Size Register */ 45 u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */ 46 u8 res6[24]; 47 u32 configflag; /* Configure Flag Register */ 48 u32 portsc1; /* Port 1 Status and Control Register */ 49 u8 res7[28]; 50 u32 otgsc; /* On-The-Go Status and Control */ 51 u32 usbmode; /* USB Mode Register */ 52 u32 endptsetupstat; /* Endpoint Setup Status Register */ 53 u32 endpointprime; /* Endpoint Initialization Register */ 54 u32 endptflush; /* Endpoint Flush Register */ 55 u32 endptstatus; /* Endpoint Status Register */ 56 u32 endptcomplete; /* Endpoint Complete Register */ 57 u32 endptctrl[6]; /* Endpoint Control Registers */ 58}; 59 60 /* USB DR host mode registers (Little Endian) */ 61struct usb_dr_host { 62 /* Capability register */ 63 u8 res1[256]; 64 u16 caplength; /* Capability Register Length */ 65 u16 hciversion; /* Host Controller Interface Version */ 66 u32 hcsparams; /* Host Controller Structural Parameters */ 67 u32 hccparams; /* Host Controller Capability Parameters */ 68 u8 res2[20]; 69 u32 dciversion; /* Device Controller Interface Version */ 70 u32 dccparams; /* Device Controller Capability Parameters */ 71 u8 res3[24]; 72 /* Operation register */ 73 u32 usbcmd; /* USB Command Register */ 74 u32 usbsts; /* USB Status Register */ 75 u32 usbintr; /* USB Interrupt Enable Register */ 76 u32 frindex; /* Frame Index Register */ 77 u8 res4[4]; 78 u32 periodiclistbase; /* Periodic Frame List Base Address Register */ 79 u32 asynclistaddr; /* Current Asynchronous List Address Register */ 80 u8 res5[4]; 81 u32 burstsize; /* Master Interface Data Burst Size Register */ 82 u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */ 83 u8 res6[24]; 84 u32 configflag; /* Configure Flag Register */ 85 u32 portsc1; /* Port 1 Status and Control Register */ 86 u8 res7[28]; 87 u32 otgsc; /* On-The-Go Status and Control */ 88 u32 usbmode; /* USB Mode Register */ 89 u32 endptsetupstat; /* Endpoint Setup Status Register */ 90 u32 endpointprime; /* Endpoint Initialization Register */ 91 u32 endptflush; /* Endpoint Flush Register */ 92 u32 endptstatus; /* Endpoint Status Register */ 93 u32 endptcomplete; /* Endpoint Complete Register */ 94 u32 endptctrl[6]; /* Endpoint Control Registers */ 95}; 96 97 /* non-EHCI USB system interface registers (Big Endian) */ 98struct usb_sys_interface { 99 u32 snoop1; 100 u32 snoop2; 101 u32 age_cnt_thresh; /* Age Count Threshold Register */ 102 u32 pri_ctrl; /* Priority Control Register */ 103 u32 si_ctrl; /* System Interface Control Register */ 104 u8 res[236]; 105 u32 control; /* General Purpose Control Register */ 106}; 107 108/* ep0 transfer state */ 109#define WAIT_FOR_SETUP 0 110#define DATA_STATE_XMIT 1 111#define DATA_STATE_NEED_ZLP 2 112#define WAIT_FOR_OUT_STATUS 3 113#define DATA_STATE_RECV 4 114 115/* Device Controller Capability Parameter register */ 116#define DCCPARAMS_DC 0x00000080 117#define DCCPARAMS_DEN_MASK 0x0000001f 118 119/* Frame Index Register Bit Masks */ 120#define USB_FRINDEX_MASKS 0x3fff 121/* USB CMD Register Bit Masks */ 122#define USB_CMD_RUN_STOP 0x00000001 123#define USB_CMD_CTRL_RESET 0x00000002 124#define USB_CMD_PERIODIC_SCHEDULE_EN 0x00000010 125#define USB_CMD_ASYNC_SCHEDULE_EN 0x00000020 126#define USB_CMD_INT_AA_DOORBELL 0x00000040 127#define USB_CMD_ASP 0x00000300 128#define USB_CMD_ASYNC_SCH_PARK_EN 0x00000800 129#define USB_CMD_SUTW 0x00002000 130#define USB_CMD_ATDTW 0x00004000 131#define USB_CMD_ITC 0x00FF0000 132 133/* bit 15,3,2 are frame list size */ 134#define USB_CMD_FRAME_SIZE_1024 0x00000000 135#define USB_CMD_FRAME_SIZE_512 0x00000004 136#define USB_CMD_FRAME_SIZE_256 0x00000008 137#define USB_CMD_FRAME_SIZE_128 0x0000000C 138#define USB_CMD_FRAME_SIZE_64 0x00008000 139#define USB_CMD_FRAME_SIZE_32 0x00008004 140#define USB_CMD_FRAME_SIZE_16 0x00008008 141#define USB_CMD_FRAME_SIZE_8 0x0000800C 142 143/* bit 9-8 are async schedule park mode count */ 144#define USB_CMD_ASP_00 0x00000000 145#define USB_CMD_ASP_01 0x00000100 146#define USB_CMD_ASP_10 0x00000200 147#define USB_CMD_ASP_11 0x00000300 148#define USB_CMD_ASP_BIT_POS 8 149 150/* bit 23-16 are interrupt threshold control */ 151#define USB_CMD_ITC_NO_THRESHOLD 0x00000000 152#define USB_CMD_ITC_1_MICRO_FRM 0x00010000 153#define USB_CMD_ITC_2_MICRO_FRM 0x00020000 154#define USB_CMD_ITC_4_MICRO_FRM 0x00040000 155#define USB_CMD_ITC_8_MICRO_FRM 0x00080000 156#define USB_CMD_ITC_16_MICRO_FRM 0x00100000 157#define USB_CMD_ITC_32_MICRO_FRM 0x00200000 158#define USB_CMD_ITC_64_MICRO_FRM 0x00400000 159#define USB_CMD_ITC_BIT_POS 16 160 161/* USB STS Register Bit Masks */ 162#define USB_STS_INT 0x00000001 163#define USB_STS_ERR 0x00000002 164#define USB_STS_PORT_CHANGE 0x00000004 165#define USB_STS_FRM_LST_ROLL 0x00000008 166#define USB_STS_SYS_ERR 0x00000010 167#define USB_STS_IAA 0x00000020 168#define USB_STS_RESET 0x00000040 169#define USB_STS_SOF 0x00000080 170#define USB_STS_SUSPEND 0x00000100 171#define USB_STS_HC_HALTED 0x00001000 172#define USB_STS_RCL 0x00002000 173#define USB_STS_PERIODIC_SCHEDULE 0x00004000 174#define USB_STS_ASYNC_SCHEDULE 0x00008000 175 176/* USB INTR Register Bit Masks */ 177#define USB_INTR_INT_EN 0x00000001 178#define USB_INTR_ERR_INT_EN 0x00000002 179#define USB_INTR_PTC_DETECT_EN 0x00000004 180#define USB_INTR_FRM_LST_ROLL_EN 0x00000008 181#define USB_INTR_SYS_ERR_EN 0x00000010 182#define USB_INTR_ASYN_ADV_EN 0x00000020 183#define USB_INTR_RESET_EN 0x00000040 184#define USB_INTR_SOF_EN 0x00000080 185#define USB_INTR_DEVICE_SUSPEND 0x00000100 186 187/* Device Address bit masks */ 188#define USB_DEVICE_ADDRESS_MASK 0xFE000000 189#define USB_DEVICE_ADDRESS_BIT_POS 25 190 191/* endpoint list address bit masks */ 192#define USB_EP_LIST_ADDRESS_MASK 0xfffff800 193 194/* PORTSCX Register Bit Masks */ 195#define PORTSCX_CURRENT_CONNECT_STATUS 0x00000001 196#define PORTSCX_CONNECT_STATUS_CHANGE 0x00000002 197#define PORTSCX_PORT_ENABLE 0x00000004 198#define PORTSCX_PORT_EN_DIS_CHANGE 0x00000008 199#define PORTSCX_OVER_CURRENT_ACT 0x00000010 200#define PORTSCX_OVER_CURRENT_CHG 0x00000020 201#define PORTSCX_PORT_FORCE_RESUME 0x00000040 202#define PORTSCX_PORT_SUSPEND 0x00000080 203#define PORTSCX_PORT_RESET 0x00000100 204#define PORTSCX_LINE_STATUS_BITS 0x00000C00 205#define PORTSCX_PORT_POWER 0x00001000 206#define PORTSCX_PORT_INDICTOR_CTRL 0x0000C000 207#define PORTSCX_PORT_TEST_CTRL 0x000F0000 208#define PORTSCX_WAKE_ON_CONNECT_EN 0x00100000 209#define PORTSCX_WAKE_ON_CONNECT_DIS 0x00200000 210#define PORTSCX_WAKE_ON_OVER_CURRENT 0x00400000 211#define PORTSCX_PHY_LOW_POWER_SPD 0x00800000 212#define PORTSCX_PORT_FORCE_FULL_SPEED 0x01000000 213#define PORTSCX_PORT_SPEED_MASK 0x0C000000 214#define PORTSCX_PORT_WIDTH 0x10000000 215#define PORTSCX_PHY_TYPE_SEL 0xC0000000 216 217/* bit 11-10 are line status */ 218#define PORTSCX_LINE_STATUS_SE0 0x00000000 219#define PORTSCX_LINE_STATUS_JSTATE 0x00000400 220#define PORTSCX_LINE_STATUS_KSTATE 0x00000800 221#define PORTSCX_LINE_STATUS_UNDEF 0x00000C00 222#define PORTSCX_LINE_STATUS_BIT_POS 10 223 224/* bit 15-14 are port indicator control */ 225#define PORTSCX_PIC_OFF 0x00000000 226#define PORTSCX_PIC_AMBER 0x00004000 227#define PORTSCX_PIC_GREEN 0x00008000 228#define PORTSCX_PIC_UNDEF 0x0000C000 229#define PORTSCX_PIC_BIT_POS 14 230 231/* bit 19-16 are port test control */ 232#define PORTSCX_PTC_DISABLE 0x00000000 233#define PORTSCX_PTC_JSTATE 0x00010000 234#define PORTSCX_PTC_KSTATE 0x00020000 235#define PORTSCX_PTC_SEQNAK 0x00030000 236#define PORTSCX_PTC_PACKET 0x00040000 237#define PORTSCX_PTC_FORCE_EN 0x00050000 238#define PORTSCX_PTC_BIT_POS 16 239 240/* bit 27-26 are port speed */ 241#define PORTSCX_PORT_SPEED_FULL 0x00000000 242#define PORTSCX_PORT_SPEED_LOW 0x04000000 243#define PORTSCX_PORT_SPEED_HIGH 0x08000000 244#define PORTSCX_PORT_SPEED_UNDEF 0x0C000000 245#define PORTSCX_SPEED_BIT_POS 26 246 247/* bit 28 is parallel transceiver width for UTMI interface */ 248#define PORTSCX_PTW 0x10000000 249#define PORTSCX_PTW_8BIT 0x00000000 250#define PORTSCX_PTW_16BIT 0x10000000 251 252/* bit 31-30 are port transceiver select */ 253#define PORTSCX_PTS_UTMI 0x00000000 254#define PORTSCX_PTS_ULPI 0x80000000 255#define PORTSCX_PTS_FSLS 0xC0000000 256#define PORTSCX_PTS_BIT_POS 30 257 258/* otgsc Register Bit Masks */ 259#define OTGSC_CTRL_VUSB_DISCHARGE 0x00000001 260#define OTGSC_CTRL_VUSB_CHARGE 0x00000002 261#define OTGSC_CTRL_OTG_TERM 0x00000008 262#define OTGSC_CTRL_DATA_PULSING 0x00000010 263#define OTGSC_STS_USB_ID 0x00000100 264#define OTGSC_STS_A_VBUS_VALID 0x00000200 265#define OTGSC_STS_A_SESSION_VALID 0x00000400 266#define OTGSC_STS_B_SESSION_VALID 0x00000800 267#define OTGSC_STS_B_SESSION_END 0x00001000 268#define OTGSC_STS_1MS_TOGGLE 0x00002000 269#define OTGSC_STS_DATA_PULSING 0x00004000 270#define OTGSC_INTSTS_USB_ID 0x00010000 271#define OTGSC_INTSTS_A_VBUS_VALID 0x00020000 272#define OTGSC_INTSTS_A_SESSION_VALID 0x00040000 273#define OTGSC_INTSTS_B_SESSION_VALID 0x00080000 274#define OTGSC_INTSTS_B_SESSION_END 0x00100000 275#define OTGSC_INTSTS_1MS 0x00200000 276#define OTGSC_INTSTS_DATA_PULSING 0x00400000 277#define OTGSC_INTR_USB_ID 0x01000000 278#define OTGSC_INTR_A_VBUS_VALID 0x02000000 279#define OTGSC_INTR_A_SESSION_VALID 0x04000000 280#define OTGSC_INTR_B_SESSION_VALID 0x08000000 281#define OTGSC_INTR_B_SESSION_END 0x10000000 282#define OTGSC_INTR_1MS_TIMER 0x20000000 283#define OTGSC_INTR_DATA_PULSING 0x40000000 284 285/* USB MODE Register Bit Masks */ 286#define USB_MODE_CTRL_MODE_IDLE 0x00000000 287#define USB_MODE_CTRL_MODE_DEVICE 0x00000002 288#define USB_MODE_CTRL_MODE_HOST 0x00000003 289#define USB_MODE_CTRL_MODE_MASK 0x00000003 290#define USB_MODE_CTRL_MODE_RSV 0x00000001 291#define USB_MODE_ES 0x00000004 /* Endian Select */ 292#define USB_MODE_SETUP_LOCK_OFF 0x00000008 293#define USB_MODE_STREAM_DISABLE 0x00000010 294/* Endpoint Flush Register */ 295#define EPFLUSH_TX_OFFSET 0x00010000 296#define EPFLUSH_RX_OFFSET 0x00000000 297 298/* Endpoint Setup Status bit masks */ 299#define EP_SETUP_STATUS_MASK 0x0000003F 300#define EP_SETUP_STATUS_EP0 0x00000001 301 302/* ENDPOINTCTRLx Register Bit Masks */ 303#define EPCTRL_TX_ENABLE 0x00800000 304#define EPCTRL_TX_DATA_TOGGLE_RST 0x00400000 /* Not EP0 */ 305#define EPCTRL_TX_DATA_TOGGLE_INH 0x00200000 /* Not EP0 */ 306#define EPCTRL_TX_TYPE 0x000C0000 307#define EPCTRL_TX_DATA_SOURCE 0x00020000 /* Not EP0 */ 308#define EPCTRL_TX_EP_STALL 0x00010000 309#define EPCTRL_RX_ENABLE 0x00000080 310#define EPCTRL_RX_DATA_TOGGLE_RST 0x00000040 /* Not EP0 */ 311#define EPCTRL_RX_DATA_TOGGLE_INH 0x00000020 /* Not EP0 */ 312#define EPCTRL_RX_TYPE 0x0000000C 313#define EPCTRL_RX_DATA_SINK 0x00000002 /* Not EP0 */ 314#define EPCTRL_RX_EP_STALL 0x00000001 315 316/* bit 19-18 and 3-2 are endpoint type */ 317#define EPCTRL_EP_TYPE_CONTROL 0 318#define EPCTRL_EP_TYPE_ISO 1 319#define EPCTRL_EP_TYPE_BULK 2 320#define EPCTRL_EP_TYPE_INTERRUPT 3 321#define EPCTRL_TX_EP_TYPE_SHIFT 18 322#define EPCTRL_RX_EP_TYPE_SHIFT 2 323 324/* SNOOPn Register Bit Masks */ 325#define SNOOP_ADDRESS_MASK 0xFFFFF000 326#define SNOOP_SIZE_ZERO 0x00 /* snooping disable */ 327#define SNOOP_SIZE_4KB 0x0B /* 4KB snoop size */ 328#define SNOOP_SIZE_8KB 0x0C 329#define SNOOP_SIZE_16KB 0x0D 330#define SNOOP_SIZE_32KB 0x0E 331#define SNOOP_SIZE_64KB 0x0F 332#define SNOOP_SIZE_128KB 0x10 333#define SNOOP_SIZE_256KB 0x11 334#define SNOOP_SIZE_512KB 0x12 335#define SNOOP_SIZE_1MB 0x13 336#define SNOOP_SIZE_2MB 0x14 337#define SNOOP_SIZE_4MB 0x15 338#define SNOOP_SIZE_8MB 0x16 339#define SNOOP_SIZE_16MB 0x17 340#define SNOOP_SIZE_32MB 0x18 341#define SNOOP_SIZE_64MB 0x19 342#define SNOOP_SIZE_128MB 0x1A 343#define SNOOP_SIZE_256MB 0x1B 344#define SNOOP_SIZE_512MB 0x1C 345#define SNOOP_SIZE_1GB 0x1D 346#define SNOOP_SIZE_2GB 0x1E /* 2GB snoop size */ 347 348/* pri_ctrl Register Bit Masks */ 349#define PRI_CTRL_PRI_LVL1 0x0000000C 350#define PRI_CTRL_PRI_LVL0 0x00000003 351 352/* si_ctrl Register Bit Masks */ 353#define SI_CTRL_ERR_DISABLE 0x00000010 354#define SI_CTRL_IDRC_DISABLE 0x00000008 355#define SI_CTRL_RD_SAFE_EN 0x00000004 356#define SI_CTRL_RD_PREFETCH_DISABLE 0x00000002 357#define SI_CTRL_RD_PREFEFETCH_VAL 0x00000001 358 359/* control Register Bit Masks */ 360#define USB_CTRL_IOENB 0x00000004 361#define USB_CTRL_ULPI_INT0EN 0x00000001 362#define USB_CTRL_UTMI_PHY_EN 0x00000200 363#define USB_CTRL_USB_EN 0x00000004 364#define USB_CTRL_ULPI_PHY_CLK_SEL 0x00000400 365 366/* Endpoint Queue Head data struct 367 * Rem: all the variables of qh are LittleEndian Mode 368 * and NEXT_POINTER_MASK should operate on a LittleEndian, Phy Addr 369 */ 370struct ep_queue_head { 371 u32 max_pkt_length; /* Mult(31-30) , Zlt(29) , Max Pkt len 372 and IOS(15) */ 373 u32 curr_dtd_ptr; /* Current dTD Pointer(31-5) */ 374 u32 next_dtd_ptr; /* Next dTD Pointer(31-5), T(0) */ 375 u32 size_ioc_int_sts; /* Total bytes (30-16), IOC (15), 376 MultO(11-10), STS (7-0) */ 377 u32 buff_ptr0; /* Buffer pointer Page 0 (31-12) */ 378 u32 buff_ptr1; /* Buffer pointer Page 1 (31-12) */ 379 u32 buff_ptr2; /* Buffer pointer Page 2 (31-12) */ 380 u32 buff_ptr3; /* Buffer pointer Page 3 (31-12) */ 381 u32 buff_ptr4; /* Buffer pointer Page 4 (31-12) */ 382 u32 res1; 383 u8 setup_buffer[8]; /* Setup data 8 bytes */ 384 u32 res2[4]; 385}; 386 387/* Endpoint Queue Head Bit Masks */ 388#define EP_QUEUE_HEAD_MULT_POS 30 389#define EP_QUEUE_HEAD_ZLT_SEL 0x20000000 390#define EP_QUEUE_HEAD_MAX_PKT_LEN_POS 16 391#define EP_QUEUE_HEAD_MAX_PKT_LEN(ep_info) (((ep_info)>>16)&0x07ff) 392#define EP_QUEUE_HEAD_IOS 0x00008000 393#define EP_QUEUE_HEAD_NEXT_TERMINATE 0x00000001 394#define EP_QUEUE_HEAD_IOC 0x00008000 395#define EP_QUEUE_HEAD_MULTO 0x00000C00 396#define EP_QUEUE_HEAD_STATUS_HALT 0x00000040 397#define EP_QUEUE_HEAD_STATUS_ACTIVE 0x00000080 398#define EP_QUEUE_CURRENT_OFFSET_MASK 0x00000FFF 399#define EP_QUEUE_HEAD_NEXT_POINTER_MASK 0xFFFFFFE0 400#define EP_QUEUE_FRINDEX_MASK 0x000007FF 401#define EP_MAX_LENGTH_TRANSFER 0x4000 402 403/* Endpoint Transfer Descriptor data struct */ 404/* Rem: all the variables of td are LittleEndian Mode */ 405struct ep_td_struct { 406 u32 next_td_ptr; /* Next TD pointer(31-5), T(0) set 407 indicate invalid */ 408 u32 size_ioc_sts; /* Total bytes (30-16), IOC (15), 409 MultO(11-10), STS (7-0) */ 410 u32 buff_ptr0; /* Buffer pointer Page 0 */ 411 u32 buff_ptr1; /* Buffer pointer Page 1 */ 412 u32 buff_ptr2; /* Buffer pointer Page 2 */ 413 u32 buff_ptr3; /* Buffer pointer Page 3 */ 414 u32 buff_ptr4; /* Buffer pointer Page 4 */ 415 u32 res; 416 /* 32 bytes */ 417 dma_addr_t td_dma; /* dma address for this td */ 418 /* virtual address of next td specified in next_td_ptr */ 419 struct ep_td_struct *next_td_virt; 420}; 421 422/* Endpoint Transfer Descriptor bit Masks */ 423#define DTD_NEXT_TERMINATE 0x00000001 424#define DTD_IOC 0x00008000 425#define DTD_STATUS_ACTIVE 0x00000080 426#define DTD_STATUS_HALTED 0x00000040 427#define DTD_STATUS_DATA_BUFF_ERR 0x00000020 428#define DTD_STATUS_TRANSACTION_ERR 0x00000008 429#define DTD_RESERVED_FIELDS 0x80007300 430#define DTD_ADDR_MASK 0xFFFFFFE0 431#define DTD_PACKET_SIZE 0x7FFF0000 432#define DTD_LENGTH_BIT_POS 16 433#define DTD_ERROR_MASK (DTD_STATUS_HALTED | \ 434 DTD_STATUS_DATA_BUFF_ERR | \ 435 DTD_STATUS_TRANSACTION_ERR) 436/* Alignment requirements; must be a power of two */ 437#define DTD_ALIGNMENT 0x20 438#define QH_ALIGNMENT 2048 439 440/* Controller dma boundary */ 441#define UDC_DMA_BOUNDARY 0x1000 442 443/*-------------------------------------------------------------------------*/ 444 445/* ### driver private data 446 */ 447struct fsl_req { 448 struct usb_request req; 449 struct list_head queue; 450 /* ep_queue() func will add 451 a request->queue into a udc_ep->queue 'd tail */ 452 struct fsl_ep *ep; 453 unsigned mapped:1; 454 455 struct ep_td_struct *head, *tail; /* For dTD List 456 cpu endian Virtual addr */ 457 unsigned int dtd_count; 458}; 459 460#define REQ_UNCOMPLETE 1 461 462struct fsl_ep { 463 struct usb_ep ep; 464 struct list_head queue; 465 struct fsl_udc *udc; 466 struct ep_queue_head *qh; 467 struct usb_gadget *gadget; 468 469 char name[14]; 470 unsigned stopped:1; 471}; 472 473#define EP_DIR_IN 1 474#define EP_DIR_OUT 0 475 476struct fsl_udc { 477 struct usb_gadget gadget; 478 struct usb_gadget_driver *driver; 479 struct fsl_usb2_platform_data *pdata; 480 struct completion *done; /* to make sure release() is done */ 481 struct fsl_ep *eps; 482 unsigned int max_ep; 483 unsigned int irq; 484 485 struct usb_ctrlrequest local_setup_buff; 486 spinlock_t lock; 487 struct usb_phy *transceiver; 488 unsigned softconnect:1; 489 unsigned vbus_active:1; 490 unsigned stopped:1; 491 unsigned remote_wakeup:1; 492 unsigned already_stopped:1; 493 unsigned big_endian_desc:1; 494 495 struct ep_queue_head *ep_qh; /* Endpoints Queue-Head */ 496 struct fsl_req *status_req; /* ep0 status request */ 497 struct dma_pool *td_pool; /* dma pool for DTD */ 498 enum fsl_usb2_phy_modes phy_mode; 499 500 size_t ep_qh_size; /* size after alignment adjustment*/ 501 dma_addr_t ep_qh_dma; /* dma address of QH */ 502 503 u32 max_pipes; /* Device max pipes */ 504 u32 bus_reset; /* Device is bus resetting */ 505 u32 resume_state; /* USB state to resume */ 506 u32 usb_state; /* USB current state */ 507 u32 ep0_state; /* Endpoint zero state */ 508 u32 ep0_dir; /* Endpoint zero direction: can be 509 USB_DIR_IN or USB_DIR_OUT */ 510 u8 device_address; /* Device USB address */ 511}; 512 513/*-------------------------------------------------------------------------*/ 514 515#ifdef DEBUG 516#define DBG(fmt, args...) printk(KERN_DEBUG "[%s] " fmt "\n", \ 517 __func__, ## args) 518#else 519#define DBG(fmt, args...) do{}while(0) 520#endif 521 522#if 0 523static void dump_msg(const char *label, const u8 * buf, unsigned int length) 524{ 525 unsigned int start, num, i; 526 char line[52], *p; 527 528 if (length >= 512) 529 return; 530 DBG("%s, length %u:\n", label, length); 531 start = 0; 532 while (length > 0) { 533 num = min(length, 16u); 534 p = line; 535 for (i = 0; i < num; ++i) { 536 if (i == 8) 537 *p++ = ' '; 538 sprintf(p, " %02x", buf[i]); 539 p += 3; 540 } 541 *p = 0; 542 printk(KERN_DEBUG "%6x: %s\n", start, line); 543 buf += num; 544 start += num; 545 length -= num; 546 } 547} 548#endif 549 550#ifdef VERBOSE 551#define VDBG DBG 552#else 553#define VDBG(stuff...) do{}while(0) 554#endif 555 556#define ERR(stuff...) pr_err("udc: " stuff) 557#define WARNING(stuff...) pr_warning("udc: " stuff) 558#define INFO(stuff...) pr_info("udc: " stuff) 559 560/*-------------------------------------------------------------------------*/ 561 562/* ### Add board specific defines here 563 */ 564 565/* 566 * ### pipe direction macro from device view 567 */ 568#define USB_RECV 0 /* OUT EP */ 569#define USB_SEND 1 /* IN EP */ 570 571/* 572 * ### internal used help routines. 573 */ 574#define ep_index(EP) ((EP)->ep.desc->bEndpointAddress&0xF) 575#define ep_maxpacket(EP) ((EP)->ep.maxpacket) 576#define ep_is_in(EP) ( (ep_index(EP) == 0) ? (EP->udc->ep0_dir == \ 577 USB_DIR_IN) : ((EP)->ep.desc->bEndpointAddress \ 578 & USB_DIR_IN)==USB_DIR_IN) 579#define get_ep_by_pipe(udc, pipe) ((pipe == 1)? &udc->eps[0]: \ 580 &udc->eps[pipe]) 581#define get_pipe_by_windex(windex) ((windex & USB_ENDPOINT_NUMBER_MASK) \ 582 * 2 + ((windex & USB_DIR_IN) ? 1 : 0)) 583#define get_pipe_by_ep(EP) (ep_index(EP) * 2 + ep_is_in(EP)) 584 585static inline struct ep_queue_head *get_qh_by_ep(struct fsl_ep *ep) 586{ 587 /* we only have one ep0 structure but two queue heads */ 588 if (ep_index(ep) != 0) 589 return ep->qh; 590 else 591 return &ep->udc->ep_qh[(ep->udc->ep0_dir == 592 USB_DIR_IN) ? 1 : 0]; 593} 594 595struct platform_device; 596#ifdef CONFIG_ARCH_MXC 597int fsl_udc_clk_init(struct platform_device *pdev); 598int fsl_udc_clk_finalize(struct platform_device *pdev); 599void fsl_udc_clk_release(void); 600#else 601static inline int fsl_udc_clk_init(struct platform_device *pdev) 602{ 603 return 0; 604} 605static inline int fsl_udc_clk_finalize(struct platform_device *pdev) 606{ 607 return 0; 608} 609static inline void fsl_udc_clk_release(void) 610{ 611} 612#endif 613 614#endif 615