1/* 2 * Copyright (c) 2001-2002 by David Brownell 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software Foundation, 16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19#ifndef __LINUX_EHCI_HCD_H 20#define __LINUX_EHCI_HCD_H 21 22/* definitions used for the EHCI driver */ 23 24/* 25 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to 26 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on 27 * the host controller implementation. 28 * 29 * To facilitate the strongest possible byte-order checking from "sparse" 30 * and so on, we use __leXX unless that's not practical. 31 */ 32#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 33typedef __u32 __bitwise __hc32; 34typedef __u16 __bitwise __hc16; 35#else 36#define __hc32 __le32 37#define __hc16 __le16 38#endif 39 40/* statistics can be kept for tuning/monitoring */ 41#ifdef CONFIG_DYNAMIC_DEBUG 42#define EHCI_STATS 43#endif 44 45struct ehci_stats { 46 /* irq usage */ 47 unsigned long normal; 48 unsigned long error; 49 unsigned long iaa; 50 unsigned long lost_iaa; 51 52 /* termination of urbs from core */ 53 unsigned long complete; 54 unsigned long unlink; 55}; 56 57/* 58 * Scheduling and budgeting information for periodic transfers, for both 59 * high-speed devices and full/low-speed devices lying behind a TT. 60 */ 61struct ehci_per_sched { 62 struct usb_device *udev; /* access to the TT */ 63 struct usb_host_endpoint *ep; 64 struct list_head ps_list; /* node on ehci_tt's ps_list */ 65 u16 tt_usecs; /* time on the FS/LS bus */ 66 u16 cs_mask; /* C-mask and S-mask bytes */ 67 u16 period; /* actual period in frames */ 68 u16 phase; /* actual phase, frame part */ 69 u8 bw_phase; /* same, for bandwidth 70 reservation */ 71 u8 phase_uf; /* uframe part of the phase */ 72 u8 usecs, c_usecs; /* times on the HS bus */ 73 u8 bw_uperiod; /* period in microframes, for 74 bandwidth reservation */ 75 u8 bw_period; /* same, in frames */ 76}; 77#define NO_FRAME 29999 /* frame not assigned yet */ 78 79/* ehci_hcd->lock guards shared data against other CPUs: 80 * ehci_hcd: async, unlink, periodic (and shadow), ... 81 * usb_host_endpoint: hcpriv 82 * ehci_qh: qh_next, qtd_list 83 * ehci_qtd: qtd_list 84 * 85 * Also, hold this lock when talking to HC registers or 86 * when updating hw_* fields in shared qh/qtd/... structures. 87 */ 88 89#define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ 90 91/* 92 * ehci_rh_state values of EHCI_RH_RUNNING or above mean that the 93 * controller may be doing DMA. Lower values mean there's no DMA. 94 */ 95enum ehci_rh_state { 96 EHCI_RH_HALTED, 97 EHCI_RH_SUSPENDED, 98 EHCI_RH_RUNNING, 99 EHCI_RH_STOPPING 100}; 101 102/* 103 * Timer events, ordered by increasing delay length. 104 * Always update event_delays_ns[] and event_handlers[] (defined in 105 * ehci-timer.c) in parallel with this list. 106 */ 107enum ehci_hrtimer_event { 108 EHCI_HRTIMER_POLL_ASS, /* Poll for async schedule off */ 109 EHCI_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */ 110 EHCI_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */ 111 EHCI_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */ 112 EHCI_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */ 113 EHCI_HRTIMER_START_UNLINK_INTR, /* Unlink empty interrupt QHs */ 114 EHCI_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */ 115 EHCI_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */ 116 EHCI_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */ 117 EHCI_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */ 118 EHCI_HRTIMER_IO_WATCHDOG, /* Check for missing IRQs */ 119 EHCI_HRTIMER_NUM_EVENTS /* Must come last */ 120}; 121#define EHCI_HRTIMER_NO_EVENT 99 122 123struct ehci_hcd { /* one per controller */ 124 /* timing support */ 125 enum ehci_hrtimer_event next_hrtimer_event; 126 unsigned enabled_hrtimer_events; 127 ktime_t hr_timeouts[EHCI_HRTIMER_NUM_EVENTS]; 128 struct hrtimer hrtimer; 129 130 int PSS_poll_count; 131 int ASS_poll_count; 132 int died_poll_count; 133 134 /* glue to PCI and HCD framework */ 135 struct ehci_caps __iomem *caps; 136 struct ehci_regs __iomem *regs; 137 struct ehci_dbg_port __iomem *debug; 138 139 __u32 hcs_params; /* cached register copy */ 140 spinlock_t lock; 141 enum ehci_rh_state rh_state; 142 143 /* general schedule support */ 144 bool scanning:1; 145 bool need_rescan:1; 146 bool intr_unlinking:1; 147 bool iaa_in_progress:1; 148 bool async_unlinking:1; 149 bool shutdown:1; 150 struct ehci_qh *qh_scan_next; 151 152 /* async schedule support */ 153 struct ehci_qh *async; 154 struct ehci_qh *dummy; /* For AMD quirk use */ 155 struct list_head async_unlink; 156 struct list_head async_idle; 157 unsigned async_unlink_cycle; 158 unsigned async_count; /* async activity count */ 159 160 /* periodic schedule support */ 161#define DEFAULT_I_TDPS 1024 /* some HCs can do less */ 162 unsigned periodic_size; 163 __hc32 *periodic; /* hw periodic table */ 164 dma_addr_t periodic_dma; 165 struct list_head intr_qh_list; 166 unsigned i_thresh; /* uframes HC might cache */ 167 168 union ehci_shadow *pshadow; /* mirror hw periodic table */ 169 struct list_head intr_unlink_wait; 170 struct list_head intr_unlink; 171 unsigned intr_unlink_wait_cycle; 172 unsigned intr_unlink_cycle; 173 unsigned now_frame; /* frame from HC hardware */ 174 unsigned last_iso_frame; /* last frame scanned for iso */ 175 unsigned intr_count; /* intr activity count */ 176 unsigned isoc_count; /* isoc activity count */ 177 unsigned periodic_count; /* periodic activity count */ 178 unsigned uframe_periodic_max; /* max periodic time per uframe */ 179 180 181 /* list of itds & sitds completed while now_frame was still active */ 182 struct list_head cached_itd_list; 183 struct ehci_itd *last_itd_to_free; 184 struct list_head cached_sitd_list; 185 struct ehci_sitd *last_sitd_to_free; 186 187 /* per root hub port */ 188 unsigned long reset_done [EHCI_MAX_ROOT_PORTS]; 189 190 /* bit vectors (one bit per port) */ 191 unsigned long bus_suspended; /* which ports were 192 already suspended at the start of a bus suspend */ 193 unsigned long companion_ports; /* which ports are 194 dedicated to the companion controller */ 195 unsigned long owned_ports; /* which ports are 196 owned by the companion during a bus suspend */ 197 unsigned long port_c_suspend; /* which ports have 198 the change-suspend feature turned on */ 199 unsigned long suspended_ports; /* which ports are 200 suspended */ 201 unsigned long resuming_ports; /* which ports have 202 started to resume */ 203 204 /* per-HC memory pools (could be per-bus, but ...) */ 205 struct dma_pool *qh_pool; /* qh per active urb */ 206 struct dma_pool *qtd_pool; /* one or more per qh */ 207 struct dma_pool *itd_pool; /* itd per iso urb */ 208 struct dma_pool *sitd_pool; /* sitd per split iso urb */ 209 210 unsigned random_frame; 211 unsigned long next_statechange; 212 ktime_t last_periodic_enable; 213 u32 command; 214 215 /* SILICON QUIRKS */ 216 unsigned no_selective_suspend:1; 217 unsigned has_fsl_port_bug:1; /* FreeScale */ 218 unsigned big_endian_mmio:1; 219 unsigned big_endian_desc:1; 220 unsigned big_endian_capbase:1; 221 unsigned has_amcc_usb23:1; 222 unsigned need_io_watchdog:1; 223 unsigned amd_pll_fix:1; 224 unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/ 225 unsigned has_synopsys_hc_bug:1; /* Synopsys HC */ 226 unsigned frame_index_bug:1; /* MosChip (AKA NetMos) */ 227 unsigned need_oc_pp_cycle:1; /* MPC834X port power */ 228 unsigned imx28_write_fix:1; /* For Freescale i.MX28 */ 229 230 /* required for usb32 quirk */ 231 #define OHCI_CTRL_HCFS (3 << 6) 232 #define OHCI_USB_OPER (2 << 6) 233 #define OHCI_USB_SUSPEND (3 << 6) 234 235 #define OHCI_HCCTRL_OFFSET 0x4 236 #define OHCI_HCCTRL_LEN 0x4 237 __hc32 *ohci_hcctrl_reg; 238 unsigned has_hostpc:1; 239 unsigned has_tdi_phy_lpm:1; 240 unsigned has_ppcd:1; /* support per-port change bits */ 241 u8 sbrn; /* packed release number */ 242 243 /* irq statistics */ 244#ifdef EHCI_STATS 245 struct ehci_stats stats; 246# define COUNT(x) do { (x)++; } while (0) 247#else 248# define COUNT(x) do {} while (0) 249#endif 250 251 /* debug files */ 252#ifdef CONFIG_DYNAMIC_DEBUG 253 struct dentry *debug_dir; 254#endif 255 256 /* bandwidth usage */ 257#define EHCI_BANDWIDTH_SIZE 64 258#define EHCI_BANDWIDTH_FRAMES (EHCI_BANDWIDTH_SIZE >> 3) 259 u8 bandwidth[EHCI_BANDWIDTH_SIZE]; 260 /* us allocated per uframe */ 261 u8 tt_budget[EHCI_BANDWIDTH_SIZE]; 262 /* us budgeted per uframe */ 263 struct list_head tt_list; 264 265 /* platform-specific data -- must come last */ 266 unsigned long priv[0] __aligned(sizeof(s64)); 267}; 268 269/* convert between an HCD pointer and the corresponding EHCI_HCD */ 270static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd) 271{ 272 return (struct ehci_hcd *) (hcd->hcd_priv); 273} 274static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci) 275{ 276 return container_of ((void *) ehci, struct usb_hcd, hcd_priv); 277} 278 279/*-------------------------------------------------------------------------*/ 280 281#include <linux/usb/ehci_def.h> 282 283/*-------------------------------------------------------------------------*/ 284 285#define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma) 286 287/* 288 * EHCI Specification 0.95 Section 3.5 289 * QTD: describe data transfer components (buffer, direction, ...) 290 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". 291 * 292 * These are associated only with "QH" (Queue Head) structures, 293 * used with control, bulk, and interrupt transfers. 294 */ 295struct ehci_qtd { 296 /* first part defined by EHCI spec */ 297 __hc32 hw_next; /* see EHCI 3.5.1 */ 298 __hc32 hw_alt_next; /* see EHCI 3.5.2 */ 299 __hc32 hw_token; /* see EHCI 3.5.3 */ 300#define QTD_TOGGLE (1 << 31) /* data toggle */ 301#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) 302#define QTD_IOC (1 << 15) /* interrupt on complete */ 303#define QTD_CERR(tok) (((tok)>>10) & 0x3) 304#define QTD_PID(tok) (((tok)>>8) & 0x3) 305#define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ 306#define QTD_STS_HALT (1 << 6) /* halted on error */ 307#define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 308#define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ 309#define QTD_STS_XACT (1 << 3) /* device gave illegal response */ 310#define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ 311#define QTD_STS_STS (1 << 1) /* split transaction state */ 312#define QTD_STS_PING (1 << 0) /* issue PING? */ 313 314#define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE) 315#define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT) 316#define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS) 317 318 __hc32 hw_buf [5]; /* see EHCI 3.5.4 */ 319 __hc32 hw_buf_hi [5]; /* Appendix B */ 320 321 /* the rest is HCD-private */ 322 dma_addr_t qtd_dma; /* qtd address */ 323 struct list_head qtd_list; /* sw qtd list */ 324 struct urb *urb; /* qtd's urb */ 325 size_t length; /* length of buffer */ 326} __attribute__ ((aligned (32))); 327 328/* mask NakCnt+T in qh->hw_alt_next */ 329#define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f) 330 331#define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1) 332 333/*-------------------------------------------------------------------------*/ 334 335/* type tag from {qh,itd,sitd,fstn}->hw_next */ 336#define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1)) 337 338/* 339 * Now the following defines are not converted using the 340 * cpu_to_le32() macro anymore, since we have to support 341 * "dynamic" switching between be and le support, so that the driver 342 * can be used on one system with SoC EHCI controller using big-endian 343 * descriptors as well as a normal little-endian PCI EHCI controller. 344 */ 345/* values for that type tag */ 346#define Q_TYPE_ITD (0 << 1) 347#define Q_TYPE_QH (1 << 1) 348#define Q_TYPE_SITD (2 << 1) 349#define Q_TYPE_FSTN (3 << 1) 350 351/* next async queue entry, or pointer to interrupt/periodic QH */ 352#define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH)) 353 354/* for periodic/async schedules and qtd lists, mark end of list */ 355#define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */ 356 357/* 358 * Entries in periodic shadow table are pointers to one of four kinds 359 * of data structure. That's dictated by the hardware; a type tag is 360 * encoded in the low bits of the hardware's periodic schedule. Use 361 * Q_NEXT_TYPE to get the tag. 362 * 363 * For entries in the async schedule, the type tag always says "qh". 364 */ 365union ehci_shadow { 366 struct ehci_qh *qh; /* Q_TYPE_QH */ 367 struct ehci_itd *itd; /* Q_TYPE_ITD */ 368 struct ehci_sitd *sitd; /* Q_TYPE_SITD */ 369 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */ 370 __hc32 *hw_next; /* (all types) */ 371 void *ptr; 372}; 373 374/*-------------------------------------------------------------------------*/ 375 376/* 377 * EHCI Specification 0.95 Section 3.6 378 * QH: describes control/bulk/interrupt endpoints 379 * See Fig 3-7 "Queue Head Structure Layout". 380 * 381 * These appear in both the async and (for interrupt) periodic schedules. 382 */ 383 384/* first part defined by EHCI spec */ 385struct ehci_qh_hw { 386 __hc32 hw_next; /* see EHCI 3.6.1 */ 387 __hc32 hw_info1; /* see EHCI 3.6.2 */ 388#define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */ 389#define QH_HEAD (1 << 15) /* Head of async reclamation list */ 390#define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */ 391#define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */ 392#define QH_LOW_SPEED (1 << 12) 393#define QH_FULL_SPEED (0 << 12) 394#define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */ 395 __hc32 hw_info2; /* see EHCI 3.6.2 */ 396#define QH_SMASK 0x000000ff 397#define QH_CMASK 0x0000ff00 398#define QH_HUBADDR 0x007f0000 399#define QH_HUBPORT 0x3f800000 400#define QH_MULT 0xc0000000 401 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */ 402 403 /* qtd overlay (hardware parts of a struct ehci_qtd) */ 404 __hc32 hw_qtd_next; 405 __hc32 hw_alt_next; 406 __hc32 hw_token; 407 __hc32 hw_buf [5]; 408 __hc32 hw_buf_hi [5]; 409} __attribute__ ((aligned(32))); 410 411struct ehci_qh { 412 struct ehci_qh_hw *hw; /* Must come first */ 413 /* the rest is HCD-private */ 414 dma_addr_t qh_dma; /* address of qh */ 415 union ehci_shadow qh_next; /* ptr to qh; or periodic */ 416 struct list_head qtd_list; /* sw qtd list */ 417 struct list_head intr_node; /* list of intr QHs */ 418 struct ehci_qtd *dummy; 419 struct list_head unlink_node; 420 struct ehci_per_sched ps; /* scheduling info */ 421 422 unsigned unlink_cycle; 423 424 u8 qh_state; 425#define QH_STATE_LINKED 1 /* HC sees this */ 426#define QH_STATE_UNLINK 2 /* HC may still see this */ 427#define QH_STATE_IDLE 3 /* HC doesn't see this */ 428#define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */ 429#define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ 430 431 u8 xacterrs; /* XactErr retry counter */ 432#define QH_XACTERR_MAX 32 /* XactErr retry limit */ 433 434 u8 gap_uf; /* uframes split/csplit gap */ 435 436 unsigned is_out:1; /* bulk or intr OUT */ 437 unsigned clearing_tt:1; /* Clear-TT-Buf in progress */ 438 unsigned dequeue_during_giveback:1; 439 unsigned exception:1; /* got a fault, or an unlink 440 was requested */ 441}; 442 443/*-------------------------------------------------------------------------*/ 444 445/* description of one iso transaction (up to 3 KB data if highspeed) */ 446struct ehci_iso_packet { 447 /* These will be copied to iTD when scheduling */ 448 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ 449 __hc32 transaction; /* itd->hw_transaction[i] |= */ 450 u8 cross; /* buf crosses pages */ 451 /* for full speed OUT splits */ 452 u32 buf1; 453}; 454 455/* temporary schedule data for packets from iso urbs (both speeds) 456 * each packet is one logical usb transaction to the device (not TT), 457 * beginning at stream->next_uframe 458 */ 459struct ehci_iso_sched { 460 struct list_head td_list; 461 unsigned span; 462 unsigned first_packet; 463 struct ehci_iso_packet packet [0]; 464}; 465 466/* 467 * ehci_iso_stream - groups all (s)itds for this endpoint. 468 * acts like a qh would, if EHCI had them for ISO. 469 */ 470struct ehci_iso_stream { 471 /* first field matches ehci_hq, but is NULL */ 472 struct ehci_qh_hw *hw; 473 474 u8 bEndpointAddress; 475 u8 highspeed; 476 struct list_head td_list; /* queued itds/sitds */ 477 struct list_head free_list; /* list of unused itds/sitds */ 478 479 /* output of (re)scheduling */ 480 struct ehci_per_sched ps; /* scheduling info */ 481 unsigned next_uframe; 482 __hc32 splits; 483 484 /* the rest is derived from the endpoint descriptor, 485 * including the extra info for hw_bufp[0..2] 486 */ 487 u16 uperiod; /* period in uframes */ 488 u16 maxp; 489 unsigned bandwidth; 490 491 /* This is used to initialize iTD's hw_bufp fields */ 492 __hc32 buf0; 493 __hc32 buf1; 494 __hc32 buf2; 495 496 /* this is used to initialize sITD's tt info */ 497 __hc32 address; 498}; 499 500/*-------------------------------------------------------------------------*/ 501 502/* 503 * EHCI Specification 0.95 Section 3.3 504 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)" 505 * 506 * Schedule records for high speed iso xfers 507 */ 508struct ehci_itd { 509 /* first part defined by EHCI spec */ 510 __hc32 hw_next; /* see EHCI 3.3.1 */ 511 __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */ 512#define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ 513#define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */ 514#define EHCI_ISOC_BABBLE (1<<29) /* babble detected */ 515#define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ 516#define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) 517#define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */ 518 519#define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE) 520 521 __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */ 522 __hc32 hw_bufp_hi [7]; /* Appendix B */ 523 524 /* the rest is HCD-private */ 525 dma_addr_t itd_dma; /* for this itd */ 526 union ehci_shadow itd_next; /* ptr to periodic q entry */ 527 528 struct urb *urb; 529 struct ehci_iso_stream *stream; /* endpoint's queue */ 530 struct list_head itd_list; /* list of stream's itds */ 531 532 /* any/all hw_transactions here may be used by that urb */ 533 unsigned frame; /* where scheduled */ 534 unsigned pg; 535 unsigned index[8]; /* in urb->iso_frame_desc */ 536} __attribute__ ((aligned (32))); 537 538/*-------------------------------------------------------------------------*/ 539 540/* 541 * EHCI Specification 0.95 Section 3.4 542 * siTD, aka split-transaction isochronous Transfer Descriptor 543 * ... describe full speed iso xfers through TT in hubs 544 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD) 545 */ 546struct ehci_sitd { 547 /* first part defined by EHCI spec */ 548 __hc32 hw_next; 549/* uses bit field macros above - see EHCI 0.95 Table 3-8 */ 550 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */ 551 __hc32 hw_uframe; /* EHCI table 3-10 */ 552 __hc32 hw_results; /* EHCI table 3-11 */ 553#define SITD_IOC (1 << 31) /* interrupt on completion */ 554#define SITD_PAGE (1 << 30) /* buffer 0/1 */ 555#define SITD_LENGTH(x) (0x3ff & ((x)>>16)) 556#define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */ 557#define SITD_STS_ERR (1 << 6) /* error from TT */ 558#define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 559#define SITD_STS_BABBLE (1 << 4) /* device was babbling */ 560#define SITD_STS_XACT (1 << 3) /* illegal IN response */ 561#define SITD_STS_MMF (1 << 2) /* incomplete split transaction */ 562#define SITD_STS_STS (1 << 1) /* split transaction state */ 563 564#define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE) 565 566 __hc32 hw_buf [2]; /* EHCI table 3-12 */ 567 __hc32 hw_backpointer; /* EHCI table 3-13 */ 568 __hc32 hw_buf_hi [2]; /* Appendix B */ 569 570 /* the rest is HCD-private */ 571 dma_addr_t sitd_dma; 572 union ehci_shadow sitd_next; /* ptr to periodic q entry */ 573 574 struct urb *urb; 575 struct ehci_iso_stream *stream; /* endpoint's queue */ 576 struct list_head sitd_list; /* list of stream's sitds */ 577 unsigned frame; 578 unsigned index; 579} __attribute__ ((aligned (32))); 580 581/*-------------------------------------------------------------------------*/ 582 583/* 584 * EHCI Specification 0.96 Section 3.7 585 * Periodic Frame Span Traversal Node (FSTN) 586 * 587 * Manages split interrupt transactions (using TT) that span frame boundaries 588 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN 589 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until 590 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. 591 */ 592struct ehci_fstn { 593 __hc32 hw_next; /* any periodic q entry */ 594 __hc32 hw_prev; /* qh or EHCI_LIST_END */ 595 596 /* the rest is HCD-private */ 597 dma_addr_t fstn_dma; 598 union ehci_shadow fstn_next; /* ptr to periodic q entry */ 599} __attribute__ ((aligned (32))); 600 601/*-------------------------------------------------------------------------*/ 602 603/* 604 * USB-2.0 Specification Sections 11.14 and 11.18 605 * Scheduling and budgeting split transactions using TTs 606 * 607 * A hub can have a single TT for all its ports, or multiple TTs (one for each 608 * port). The bandwidth and budgeting information for the full/low-speed bus 609 * below each TT is self-contained and independent of the other TTs or the 610 * high-speed bus. 611 * 612 * "Bandwidth" refers to the number of microseconds on the FS/LS bus allocated 613 * to an interrupt or isochronous endpoint for each frame. "Budget" refers to 614 * the best-case estimate of the number of full-speed bytes allocated to an 615 * endpoint for each microframe within an allocated frame. 616 * 617 * Removal of an endpoint invalidates a TT's budget. Instead of trying to 618 * keep an up-to-date record, we recompute the budget when it is needed. 619 */ 620 621struct ehci_tt { 622 u16 bandwidth[EHCI_BANDWIDTH_FRAMES]; 623 624 struct list_head tt_list; /* List of all ehci_tt's */ 625 struct list_head ps_list; /* Items using this TT */ 626 struct usb_tt *usb_tt; 627 int tt_port; /* TT port number */ 628}; 629 630/*-------------------------------------------------------------------------*/ 631 632/* Prepare the PORTSC wakeup flags during controller suspend/resume */ 633 634#define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \ 635 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup); 636 637#define ehci_prepare_ports_for_controller_resume(ehci) \ 638 ehci_adjust_port_wakeup_flags(ehci, false, false); 639 640/*-------------------------------------------------------------------------*/ 641 642#ifdef CONFIG_USB_EHCI_ROOT_HUB_TT 643 644/* 645 * Some EHCI controllers have a Transaction Translator built into the 646 * root hub. This is a non-standard feature. Each controller will need 647 * to add code to the following inline functions, and call them as 648 * needed (mostly in root hub code). 649 */ 650 651#define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt) 652 653/* Returns the speed of a device attached to a port on the root hub. */ 654static inline unsigned int 655ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) 656{ 657 if (ehci_is_TDI(ehci)) { 658 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) { 659 case 0: 660 return 0; 661 case 1: 662 return USB_PORT_STAT_LOW_SPEED; 663 case 2: 664 default: 665 return USB_PORT_STAT_HIGH_SPEED; 666 } 667 } 668 return USB_PORT_STAT_HIGH_SPEED; 669} 670 671#else 672 673#define ehci_is_TDI(e) (0) 674 675#define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED 676#endif 677 678/*-------------------------------------------------------------------------*/ 679 680#ifdef CONFIG_PPC_83xx 681/* Some Freescale processors have an erratum in which the TT 682 * port number in the queue head was 0..N-1 instead of 1..N. 683 */ 684#define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug) 685#else 686#define ehci_has_fsl_portno_bug(e) (0) 687#endif 688 689/* 690 * While most USB host controllers implement their registers in 691 * little-endian format, a minority (celleb companion chip) implement 692 * them in big endian format. 693 * 694 * This attempts to support either format at compile time without a 695 * runtime penalty, or both formats with the additional overhead 696 * of checking a flag bit. 697 * 698 * ehci_big_endian_capbase is a special quirk for controllers that 699 * implement the HC capability registers as separate registers and not 700 * as fields of a 32-bit register. 701 */ 702 703#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 704#define ehci_big_endian_mmio(e) ((e)->big_endian_mmio) 705#define ehci_big_endian_capbase(e) ((e)->big_endian_capbase) 706#else 707#define ehci_big_endian_mmio(e) 0 708#define ehci_big_endian_capbase(e) 0 709#endif 710 711/* 712 * Big-endian read/write functions are arch-specific. 713 * Other arches can be added if/when they're needed. 714 */ 715#if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX) 716#define readl_be(addr) __raw_readl((__force unsigned *)addr) 717#define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) 718#endif 719 720static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, 721 __u32 __iomem * regs) 722{ 723#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 724 return ehci_big_endian_mmio(ehci) ? 725 readl_be(regs) : 726 readl(regs); 727#else 728 return readl(regs); 729#endif 730} 731 732#ifdef CONFIG_SOC_IMX28 733static inline void imx28_ehci_writel(const unsigned int val, 734 volatile __u32 __iomem *addr) 735{ 736 __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr)); 737} 738#else 739static inline void imx28_ehci_writel(const unsigned int val, 740 volatile __u32 __iomem *addr) 741{ 742} 743#endif 744static inline void ehci_writel(const struct ehci_hcd *ehci, 745 const unsigned int val, __u32 __iomem *regs) 746{ 747#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 748 ehci_big_endian_mmio(ehci) ? 749 writel_be(val, regs) : 750 writel(val, regs); 751#else 752 if (ehci->imx28_write_fix) 753 imx28_ehci_writel(val, regs); 754 else 755 writel(val, regs); 756#endif 757} 758 759/* 760 * On certain ppc-44x SoC there is a HW issue, that could only worked around with 761 * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch. 762 * Other common bits are dependent on has_amcc_usb23 quirk flag. 763 */ 764#ifdef CONFIG_44x 765static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) 766{ 767 u32 hc_control; 768 769 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS); 770 if (operational) 771 hc_control |= OHCI_USB_OPER; 772 else 773 hc_control |= OHCI_USB_SUSPEND; 774 775 writel_be(hc_control, ehci->ohci_hcctrl_reg); 776 (void) readl_be(ehci->ohci_hcctrl_reg); 777} 778#else 779static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) 780{ } 781#endif 782 783/*-------------------------------------------------------------------------*/ 784 785/* 786 * The AMCC 440EPx not only implements its EHCI registers in big-endian 787 * format, but also its DMA data structures (descriptors). 788 * 789 * EHCI controllers accessed through PCI work normally (little-endian 790 * everywhere), so we won't bother supporting a BE-only mode for now. 791 */ 792#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 793#define ehci_big_endian_desc(e) ((e)->big_endian_desc) 794 795/* cpu to ehci */ 796static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) 797{ 798 return ehci_big_endian_desc(ehci) 799 ? (__force __hc32)cpu_to_be32(x) 800 : (__force __hc32)cpu_to_le32(x); 801} 802 803/* ehci to cpu */ 804static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) 805{ 806 return ehci_big_endian_desc(ehci) 807 ? be32_to_cpu((__force __be32)x) 808 : le32_to_cpu((__force __le32)x); 809} 810 811static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) 812{ 813 return ehci_big_endian_desc(ehci) 814 ? be32_to_cpup((__force __be32 *)x) 815 : le32_to_cpup((__force __le32 *)x); 816} 817 818#else 819 820/* cpu to ehci */ 821static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) 822{ 823 return cpu_to_le32(x); 824} 825 826/* ehci to cpu */ 827static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) 828{ 829 return le32_to_cpu(x); 830} 831 832static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) 833{ 834 return le32_to_cpup(x); 835} 836 837#endif 838 839/*-------------------------------------------------------------------------*/ 840 841#define ehci_dbg(ehci, fmt, args...) \ 842 dev_dbg(ehci_to_hcd(ehci)->self.controller , fmt , ## args) 843#define ehci_err(ehci, fmt, args...) \ 844 dev_err(ehci_to_hcd(ehci)->self.controller , fmt , ## args) 845#define ehci_info(ehci, fmt, args...) \ 846 dev_info(ehci_to_hcd(ehci)->self.controller , fmt , ## args) 847#define ehci_warn(ehci, fmt, args...) \ 848 dev_warn(ehci_to_hcd(ehci)->self.controller , fmt , ## args) 849 850 851#ifndef CONFIG_DYNAMIC_DEBUG 852#define STUB_DEBUG_FILES 853#endif 854 855/*-------------------------------------------------------------------------*/ 856 857/* Declarations of things exported for use by ehci platform drivers */ 858 859struct ehci_driver_overrides { 860 size_t extra_priv_size; 861 int (*reset)(struct usb_hcd *hcd); 862 int (*port_power)(struct usb_hcd *hcd, 863 int portnum, bool enable); 864}; 865 866extern void ehci_init_driver(struct hc_driver *drv, 867 const struct ehci_driver_overrides *over); 868extern int ehci_setup(struct usb_hcd *hcd); 869extern int ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr, 870 u32 mask, u32 done, int usec); 871 872#ifdef CONFIG_PM 873extern int ehci_suspend(struct usb_hcd *hcd, bool do_wakeup); 874extern int ehci_resume(struct usb_hcd *hcd, bool force_reset); 875#endif /* CONFIG_PM */ 876 877extern int ehci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 878 u16 wIndex, char *buf, u16 wLength); 879 880#endif /* __LINUX_EHCI_HCD_H */ 881