1/*
2 * xHCI host controller driver PCI Bus Glue.
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/pci.h>
24#include <linux/slab.h>
25#include <linux/module.h>
26#include <linux/acpi.h>
27
28#include "xhci.h"
29#include "xhci-trace.h"
30
31#define SSIC_PORT_NUM		2
32#define SSIC_PORT_CFG2		0x880c
33#define SSIC_PORT_CFG2_OFFSET	0x30
34#define PROG_DONE		(1 << 30)
35#define SSIC_PORT_UNUSED	(1 << 31)
36
37/* Device for a quirk */
38#define PCI_VENDOR_ID_FRESCO_LOGIC	0x1b73
39#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK	0x1000
40#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400	0x1400
41
42#define PCI_VENDOR_ID_ETRON		0x1b6f
43#define PCI_DEVICE_ID_EJ168		0x7023
44
45#define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI	0x8c31
46#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI	0x9c31
47#define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI		0x22b5
48#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI		0xa12f
49#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI	0x9d2f
50#define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI		0x0aa8
51#define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI		0x1aa8
52
53static const char hcd_name[] = "xhci_hcd";
54
55static struct hc_driver __read_mostly xhci_pci_hc_driver;
56
57/* called after powerup, by probe or system-pm "wakeup" */
58static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
59{
60	/*
61	 * TODO: Implement finding debug ports later.
62	 * TODO: see if there are any quirks that need to be added to handle
63	 * new extended capabilities.
64	 */
65
66	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
67	if (!pci_set_mwi(pdev))
68		xhci_dbg(xhci, "MWI active\n");
69
70	xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
71	return 0;
72}
73
74static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
75{
76	struct pci_dev		*pdev = to_pci_dev(dev);
77
78	/* Look for vendor-specific quirks */
79	if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
80			(pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
81			 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
82		if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
83				pdev->revision == 0x0) {
84			xhci->quirks |= XHCI_RESET_EP_QUIRK;
85			xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
86				"QUIRK: Fresco Logic xHC needs configure"
87				" endpoint cmd after reset endpoint");
88		}
89		if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
90				pdev->revision == 0x4) {
91			xhci->quirks |= XHCI_SLOW_SUSPEND;
92			xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
93				"QUIRK: Fresco Logic xHC revision %u"
94				"must be suspended extra slowly",
95				pdev->revision);
96		}
97		if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
98			xhci->quirks |= XHCI_BROKEN_STREAMS;
99		/* Fresco Logic confirms: all revisions of this chip do not
100		 * support MSI, even though some of them claim to in their PCI
101		 * capabilities.
102		 */
103		xhci->quirks |= XHCI_BROKEN_MSI;
104		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
105				"QUIRK: Fresco Logic revision %u "
106				"has broken MSI implementation",
107				pdev->revision);
108		xhci->quirks |= XHCI_TRUST_TX_LENGTH;
109	}
110
111	if (pdev->vendor == PCI_VENDOR_ID_NEC)
112		xhci->quirks |= XHCI_NEC_HOST;
113
114	if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
115		xhci->quirks |= XHCI_AMD_0x96_HOST;
116
117	/* AMD PLL quirk */
118	if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
119		xhci->quirks |= XHCI_AMD_PLL_FIX;
120
121	if (pdev->vendor == PCI_VENDOR_ID_AMD)
122		xhci->quirks |= XHCI_TRUST_TX_LENGTH;
123
124	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
125		xhci->quirks |= XHCI_LPM_SUPPORT;
126		xhci->quirks |= XHCI_INTEL_HOST;
127		xhci->quirks |= XHCI_AVOID_BEI;
128	}
129	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
130			pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
131		xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
132		xhci->limit_active_eps = 64;
133		xhci->quirks |= XHCI_SW_BW_CHECKING;
134		/*
135		 * PPT desktop boards DH77EB and DH77DF will power back on after
136		 * a few seconds of being shutdown.  The fix for this is to
137		 * switch the ports from xHCI to EHCI on shutdown.  We can't use
138		 * DMI information to find those particular boards (since each
139		 * vendor will change the board name), so we have to key off all
140		 * PPT chipsets.
141		 */
142		xhci->quirks |= XHCI_SPURIOUS_REBOOT;
143	}
144	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
145		pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI) {
146		xhci->quirks |= XHCI_SPURIOUS_REBOOT;
147		xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
148	}
149	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
150		(pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
151		 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
152		 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
153		 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
154		 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI)) {
155		xhci->quirks |= XHCI_PME_STUCK_QUIRK;
156	}
157	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
158		 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
159		xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
160	}
161	if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
162			pdev->device == PCI_DEVICE_ID_EJ168) {
163		xhci->quirks |= XHCI_RESET_ON_RESUME;
164		xhci->quirks |= XHCI_TRUST_TX_LENGTH;
165		xhci->quirks |= XHCI_BROKEN_STREAMS;
166	}
167	if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
168			pdev->device == 0x0015)
169		xhci->quirks |= XHCI_RESET_ON_RESUME;
170	if (pdev->vendor == PCI_VENDOR_ID_VIA)
171		xhci->quirks |= XHCI_RESET_ON_RESUME;
172
173	/* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
174	if (pdev->vendor == PCI_VENDOR_ID_VIA &&
175			pdev->device == 0x3432)
176		xhci->quirks |= XHCI_BROKEN_STREAMS;
177
178	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
179			pdev->device == 0x1042)
180		xhci->quirks |= XHCI_BROKEN_STREAMS;
181
182	if (xhci->quirks & XHCI_RESET_ON_RESUME)
183		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
184				"QUIRK: Resetting on resume");
185}
186
187#ifdef CONFIG_ACPI
188static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
189{
190	static const u8 intel_dsm_uuid[] = {
191		0xb7, 0x0c, 0x34, 0xac,	0x01, 0xe9, 0xbf, 0x45,
192		0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23,
193	};
194	acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), intel_dsm_uuid, 3, 1, NULL);
195}
196#else
197	static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
198#endif /* CONFIG_ACPI */
199
200/* called during probe() after chip reset completes */
201static int xhci_pci_setup(struct usb_hcd *hcd)
202{
203	struct xhci_hcd		*xhci;
204	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
205	int			retval;
206
207	retval = xhci_gen_setup(hcd, xhci_pci_quirks);
208	if (retval)
209		return retval;
210
211	xhci = hcd_to_xhci(hcd);
212	if (!usb_hcd_is_primary_hcd(hcd))
213		return 0;
214
215	pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
216	xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
217
218	/* Find any debug ports */
219	retval = xhci_pci_reinit(xhci, pdev);
220	if (!retval)
221		return retval;
222
223	kfree(xhci);
224	return retval;
225}
226
227/*
228 * We need to register our own PCI probe function (instead of the USB core's
229 * function) in order to create a second roothub under xHCI.
230 */
231static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
232{
233	int retval;
234	struct xhci_hcd *xhci;
235	struct hc_driver *driver;
236	struct usb_hcd *hcd;
237
238	driver = (struct hc_driver *)id->driver_data;
239
240	/* Prevent runtime suspending between USB-2 and USB-3 initialization */
241	pm_runtime_get_noresume(&dev->dev);
242
243	/* Register the USB 2.0 roothub.
244	 * FIXME: USB core must know to register the USB 2.0 roothub first.
245	 * This is sort of silly, because we could just set the HCD driver flags
246	 * to say USB 2.0, but I'm not sure what the implications would be in
247	 * the other parts of the HCD code.
248	 */
249	retval = usb_hcd_pci_probe(dev, id);
250
251	if (retval)
252		goto put_runtime_pm;
253
254	/* USB 2.0 roothub is stored in the PCI device now. */
255	hcd = dev_get_drvdata(&dev->dev);
256	xhci = hcd_to_xhci(hcd);
257	xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
258				pci_name(dev), hcd);
259	if (!xhci->shared_hcd) {
260		retval = -ENOMEM;
261		goto dealloc_usb2_hcd;
262	}
263
264	/* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset)
265	 * is called by usb_add_hcd().
266	 */
267	*((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
268
269	retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
270			IRQF_SHARED);
271	if (retval)
272		goto put_usb3_hcd;
273	/* Roothub already marked as USB 3.0 speed */
274
275	if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
276			HCC_MAX_PSA(xhci->hcc_params) >= 4)
277		xhci->shared_hcd->can_do_streams = 1;
278
279	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
280		xhci_pme_acpi_rtd3_enable(dev);
281
282	/* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
283	pm_runtime_put_noidle(&dev->dev);
284
285	return 0;
286
287put_usb3_hcd:
288	usb_put_hcd(xhci->shared_hcd);
289dealloc_usb2_hcd:
290	usb_hcd_pci_remove(dev);
291put_runtime_pm:
292	pm_runtime_put_noidle(&dev->dev);
293	return retval;
294}
295
296static void xhci_pci_remove(struct pci_dev *dev)
297{
298	struct xhci_hcd *xhci;
299
300	xhci = hcd_to_xhci(pci_get_drvdata(dev));
301	xhci->xhc_state |= XHCI_STATE_REMOVING;
302	if (xhci->shared_hcd) {
303		usb_remove_hcd(xhci->shared_hcd);
304		usb_put_hcd(xhci->shared_hcd);
305	}
306	usb_hcd_pci_remove(dev);
307
308	/* Workaround for spurious wakeups at shutdown with HSW */
309	if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
310		pci_set_power_state(dev, PCI_D3hot);
311
312	kfree(xhci);
313}
314
315#ifdef CONFIG_PM
316/*
317 * In some Intel xHCI controllers, in order to get D3 working,
318 * through a vendor specific SSIC CONFIG register at offset 0x883c,
319 * SSIC PORT need to be marked as "unused" before putting xHCI
320 * into D3. After D3 exit, the SSIC port need to be marked as "used".
321 * Without this change, xHCI might not enter D3 state.
322 */
323static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
324{
325	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
326	u32 val;
327	void __iomem *reg;
328	int i;
329
330	for (i = 0; i < SSIC_PORT_NUM; i++) {
331		reg = (void __iomem *) xhci->cap_regs +
332				SSIC_PORT_CFG2 +
333				i * SSIC_PORT_CFG2_OFFSET;
334
335		/* Notify SSIC that SSIC profile programming is not done. */
336		val = readl(reg) & ~PROG_DONE;
337		writel(val, reg);
338
339		/* Mark SSIC port as unused(suspend) or used(resume) */
340		val = readl(reg);
341		if (suspend)
342			val |= SSIC_PORT_UNUSED;
343		else
344			val &= ~SSIC_PORT_UNUSED;
345		writel(val, reg);
346
347		/* Notify SSIC that SSIC profile programming is done */
348		val = readl(reg) | PROG_DONE;
349		writel(val, reg);
350		readl(reg);
351	}
352}
353
354/*
355 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
356 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
357 */
358static void xhci_pme_quirk(struct usb_hcd *hcd)
359{
360	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
361	void __iomem *reg;
362	u32 val;
363
364	reg = (void __iomem *) xhci->cap_regs + 0x80a4;
365	val = readl(reg);
366	writel(val | BIT(28), reg);
367	readl(reg);
368}
369
370static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
371{
372	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
373	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
374	int			ret;
375
376	/*
377	 * Systems with the TI redriver that loses port status change events
378	 * need to have the registers polled during D3, so avoid D3cold.
379	 */
380	if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
381		pdev->no_d3cold = true;
382
383	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
384		xhci_pme_quirk(hcd);
385
386	if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
387		xhci_ssic_port_unused_quirk(hcd, true);
388
389	ret = xhci_suspend(xhci, do_wakeup);
390	if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
391		xhci_ssic_port_unused_quirk(hcd, false);
392
393	return ret;
394}
395
396static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
397{
398	struct xhci_hcd		*xhci = hcd_to_xhci(hcd);
399	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
400	int			retval = 0;
401
402	/* The BIOS on systems with the Intel Panther Point chipset may or may
403	 * not support xHCI natively.  That means that during system resume, it
404	 * may switch the ports back to EHCI so that users can use their
405	 * keyboard to select a kernel from GRUB after resume from hibernate.
406	 *
407	 * The BIOS is supposed to remember whether the OS had xHCI ports
408	 * enabled before resume, and switch the ports back to xHCI when the
409	 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
410	 * writers.
411	 *
412	 * Unconditionally switch the ports back to xHCI after a system resume.
413	 * It should not matter whether the EHCI or xHCI controller is
414	 * resumed first. It's enough to do the switchover in xHCI because
415	 * USB core won't notice anything as the hub driver doesn't start
416	 * running again until after all the devices (including both EHCI and
417	 * xHCI host controllers) have been resumed.
418	 */
419
420	if (pdev->vendor == PCI_VENDOR_ID_INTEL)
421		usb_enable_intel_xhci_ports(pdev);
422
423	if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
424		xhci_ssic_port_unused_quirk(hcd, false);
425
426	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
427		xhci_pme_quirk(hcd);
428
429	retval = xhci_resume(xhci, hibernated);
430	return retval;
431}
432#endif /* CONFIG_PM */
433
434/*-------------------------------------------------------------------------*/
435
436/* PCI driver selection metadata; PCI hotplugging uses this */
437static const struct pci_device_id pci_ids[] = { {
438	/* handle any USB 3.0 xHCI controller */
439	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
440	.driver_data =	(unsigned long) &xhci_pci_hc_driver,
441	},
442	{ /* end: all zeroes */ }
443};
444MODULE_DEVICE_TABLE(pci, pci_ids);
445
446/* pci driver glue; this is a "new style" PCI driver module */
447static struct pci_driver xhci_pci_driver = {
448	.name =		(char *) hcd_name,
449	.id_table =	pci_ids,
450
451	.probe =	xhci_pci_probe,
452	.remove =	xhci_pci_remove,
453	/* suspend and resume implemented later */
454
455	.shutdown = 	usb_hcd_pci_shutdown,
456#ifdef CONFIG_PM
457	.driver = {
458		.pm = &usb_hcd_pci_pm_ops
459	},
460#endif
461};
462
463static int __init xhci_pci_init(void)
464{
465	xhci_init_driver(&xhci_pci_hc_driver, xhci_pci_setup);
466#ifdef CONFIG_PM
467	xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
468	xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
469#endif
470	return pci_register_driver(&xhci_pci_driver);
471}
472module_init(xhci_pci_init);
473
474static void __exit xhci_pci_exit(void)
475{
476	pci_unregister_driver(&xhci_pci_driver);
477}
478module_exit(xhci_pci_exit);
479
480MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
481MODULE_LICENSE("GPL");
482