1/*
2 *  linux/drivers/video/arkfb.c -- Frame buffer device driver for ARK 2000PV
3 *  with ICS 5342 dac (it is easy to add support for different dacs).
4 *
5 *  Copyright (c) 2007 Ondrej Zajicek <santiago@crfreenet.org>
6 *
7 *  This file is subject to the terms and conditions of the GNU General Public
8 *  License.  See the file COPYING in the main directory of this archive for
9 *  more details.
10 *
11 *  Code is based on s3fb
12 */
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/errno.h>
17#include <linux/string.h>
18#include <linux/mm.h>
19#include <linux/tty.h>
20#include <linux/slab.h>
21#include <linux/delay.h>
22#include <linux/fb.h>
23#include <linux/svga.h>
24#include <linux/init.h>
25#include <linux/pci.h>
26#include <linux/console.h> /* Why should fb driver call console functions? because console_lock() */
27#include <video/vga.h>
28
29#ifdef CONFIG_MTRR
30#include <asm/mtrr.h>
31#endif
32
33struct arkfb_info {
34	int mclk_freq;
35	int mtrr_reg;
36
37	struct dac_info *dac;
38	struct vgastate state;
39	struct mutex open_lock;
40	unsigned int ref_count;
41	u32 pseudo_palette[16];
42};
43
44
45/* ------------------------------------------------------------------------- */
46
47
48static const struct svga_fb_format arkfb_formats[] = {
49	{ 0,  {0, 6, 0},  {0, 6, 0},  {0, 6, 0}, {0, 0, 0}, 0,
50		FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4,	FB_VISUAL_PSEUDOCOLOR, 8, 8},
51	{ 4,  {0, 6, 0},  {0, 6, 0},  {0, 6, 0}, {0, 0, 0}, 0,
52		FB_TYPE_PACKED_PIXELS, 0,		FB_VISUAL_PSEUDOCOLOR, 8, 16},
53	{ 4,  {0, 6, 0},  {0, 6, 0},  {0, 6, 0}, {0, 0, 0}, 1,
54		FB_TYPE_INTERLEAVED_PLANES, 1,		FB_VISUAL_PSEUDOCOLOR, 8, 16},
55	{ 8,  {0, 6, 0},  {0, 6, 0},  {0, 6, 0}, {0, 0, 0}, 0,
56		FB_TYPE_PACKED_PIXELS, 0,		FB_VISUAL_PSEUDOCOLOR, 8, 8},
57	{16,  {10, 5, 0}, {5, 5, 0},  {0, 5, 0}, {0, 0, 0}, 0,
58		FB_TYPE_PACKED_PIXELS, 0,		FB_VISUAL_TRUECOLOR, 4, 4},
59	{16,  {11, 5, 0}, {5, 6, 0},  {0, 5, 0}, {0, 0, 0}, 0,
60		FB_TYPE_PACKED_PIXELS, 0,		FB_VISUAL_TRUECOLOR, 4, 4},
61	{24,  {16, 8, 0}, {8, 8, 0},  {0, 8, 0}, {0, 0, 0}, 0,
62		FB_TYPE_PACKED_PIXELS, 0,		FB_VISUAL_TRUECOLOR, 8, 8},
63	{32,  {16, 8, 0}, {8, 8, 0},  {0, 8, 0}, {0, 0, 0}, 0,
64		FB_TYPE_PACKED_PIXELS, 0,		FB_VISUAL_TRUECOLOR, 2, 2},
65	SVGA_FORMAT_END
66};
67
68
69/* CRT timing register sets */
70
71static const struct vga_regset ark_h_total_regs[]        = {{0x00, 0, 7}, {0x41, 7, 7}, VGA_REGSET_END};
72static const struct vga_regset ark_h_display_regs[]      = {{0x01, 0, 7}, {0x41, 6, 6}, VGA_REGSET_END};
73static const struct vga_regset ark_h_blank_start_regs[]  = {{0x02, 0, 7}, {0x41, 5, 5}, VGA_REGSET_END};
74static const struct vga_regset ark_h_blank_end_regs[]    = {{0x03, 0, 4}, {0x05, 7, 7	}, VGA_REGSET_END};
75static const struct vga_regset ark_h_sync_start_regs[]   = {{0x04, 0, 7}, {0x41, 4, 4}, VGA_REGSET_END};
76static const struct vga_regset ark_h_sync_end_regs[]     = {{0x05, 0, 4}, VGA_REGSET_END};
77
78static const struct vga_regset ark_v_total_regs[]        = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x40, 7, 7}, VGA_REGSET_END};
79static const struct vga_regset ark_v_display_regs[]      = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x40, 6, 6}, VGA_REGSET_END};
80static const struct vga_regset ark_v_blank_start_regs[]  = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x40, 5, 5}, VGA_REGSET_END};
81// const struct vga_regset ark_v_blank_end_regs[]    = {{0x16, 0, 6}, VGA_REGSET_END};
82static const struct vga_regset ark_v_blank_end_regs[]    = {{0x16, 0, 7}, VGA_REGSET_END};
83static const struct vga_regset ark_v_sync_start_regs[]   = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x40, 4, 4}, VGA_REGSET_END};
84static const struct vga_regset ark_v_sync_end_regs[]     = {{0x11, 0, 3}, VGA_REGSET_END};
85
86static const struct vga_regset ark_line_compare_regs[]   = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, VGA_REGSET_END};
87static const struct vga_regset ark_start_address_regs[]  = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x40, 0, 2}, VGA_REGSET_END};
88static const struct vga_regset ark_offset_regs[]         = {{0x13, 0, 7}, {0x41, 3, 3}, VGA_REGSET_END};
89
90static const struct svga_timing_regs ark_timing_regs     = {
91	ark_h_total_regs, ark_h_display_regs, ark_h_blank_start_regs,
92	ark_h_blank_end_regs, ark_h_sync_start_regs, ark_h_sync_end_regs,
93	ark_v_total_regs, ark_v_display_regs, ark_v_blank_start_regs,
94	ark_v_blank_end_regs, ark_v_sync_start_regs, ark_v_sync_end_regs,
95};
96
97
98/* ------------------------------------------------------------------------- */
99
100
101/* Module parameters */
102
103static char *mode_option = "640x480-8@60";
104
105#ifdef CONFIG_MTRR
106static int mtrr = 1;
107#endif
108
109MODULE_AUTHOR("(c) 2007 Ondrej Zajicek <santiago@crfreenet.org>");
110MODULE_LICENSE("GPL");
111MODULE_DESCRIPTION("fbdev driver for ARK 2000PV");
112
113module_param(mode_option, charp, 0444);
114MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)");
115module_param_named(mode, mode_option, charp, 0444);
116MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc) (deprecated)");
117
118#ifdef CONFIG_MTRR
119module_param(mtrr, int, 0444);
120MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");
121#endif
122
123static int threshold = 4;
124
125module_param(threshold, int, 0644);
126MODULE_PARM_DESC(threshold, "FIFO threshold");
127
128
129/* ------------------------------------------------------------------------- */
130
131
132static void arkfb_settile(struct fb_info *info, struct fb_tilemap *map)
133{
134	const u8 *font = map->data;
135	u8 __iomem *fb = (u8 __iomem *)info->screen_base;
136	int i, c;
137
138	if ((map->width != 8) || (map->height != 16) ||
139	    (map->depth != 1) || (map->length != 256)) {
140		fb_err(info, "unsupported font parameters: width %d, height %d, depth %d, length %d\n",
141		       map->width, map->height, map->depth, map->length);
142		return;
143	}
144
145	fb += 2;
146	for (c = 0; c < map->length; c++) {
147		for (i = 0; i < map->height; i++) {
148			fb_writeb(font[i], &fb[i * 4]);
149			fb_writeb(font[i], &fb[i * 4 + (128 * 8)]);
150		}
151		fb += 128;
152
153		if ((c % 8) == 7)
154			fb += 128*8;
155
156		font += map->height;
157	}
158}
159
160static void arkfb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor)
161{
162	struct arkfb_info *par = info->par;
163
164	svga_tilecursor(par->state.vgabase, info, cursor);
165}
166
167static struct fb_tile_ops arkfb_tile_ops = {
168	.fb_settile	= arkfb_settile,
169	.fb_tilecopy	= svga_tilecopy,
170	.fb_tilefill    = svga_tilefill,
171	.fb_tileblit    = svga_tileblit,
172	.fb_tilecursor  = arkfb_tilecursor,
173	.fb_get_tilemax = svga_get_tilemax,
174};
175
176
177/* ------------------------------------------------------------------------- */
178
179
180/* image data is MSB-first, fb structure is MSB-first too */
181static inline u32 expand_color(u32 c)
182{
183	return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF;
184}
185
186/* arkfb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */
187static void arkfb_iplan_imageblit(struct fb_info *info, const struct fb_image *image)
188{
189	u32 fg = expand_color(image->fg_color);
190	u32 bg = expand_color(image->bg_color);
191	const u8 *src1, *src;
192	u8 __iomem *dst1;
193	u32 __iomem *dst;
194	u32 val;
195	int x, y;
196
197	src1 = image->data;
198	dst1 = info->screen_base + (image->dy * info->fix.line_length)
199		 + ((image->dx / 8) * 4);
200
201	for (y = 0; y < image->height; y++) {
202		src = src1;
203		dst = (u32 __iomem *) dst1;
204		for (x = 0; x < image->width; x += 8) {
205			val = *(src++) * 0x01010101;
206			val = (val & fg) | (~val & bg);
207			fb_writel(val, dst++);
208		}
209		src1 += image->width / 8;
210		dst1 += info->fix.line_length;
211	}
212
213}
214
215/* arkfb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */
216static void arkfb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
217{
218	u32 fg = expand_color(rect->color);
219	u8 __iomem *dst1;
220	u32 __iomem *dst;
221	int x, y;
222
223	dst1 = info->screen_base + (rect->dy * info->fix.line_length)
224		 + ((rect->dx / 8) * 4);
225
226	for (y = 0; y < rect->height; y++) {
227		dst = (u32 __iomem *) dst1;
228		for (x = 0; x < rect->width; x += 8) {
229			fb_writel(fg, dst++);
230		}
231		dst1 += info->fix.line_length;
232	}
233
234}
235
236
237/* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */
238static inline u32 expand_pixel(u32 c)
239{
240	return (((c &  1) << 24) | ((c &  2) << 27) | ((c &  4) << 14) | ((c &   8) << 17) |
241		((c & 16) <<  4) | ((c & 32) <<  7) | ((c & 64) >>  6) | ((c & 128) >>  3)) * 0xF;
242}
243
244/* arkfb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */
245static void arkfb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image)
246{
247	u32 fg = image->fg_color * 0x11111111;
248	u32 bg = image->bg_color * 0x11111111;
249	const u8 *src1, *src;
250	u8 __iomem *dst1;
251	u32 __iomem *dst;
252	u32 val;
253	int x, y;
254
255	src1 = image->data;
256	dst1 = info->screen_base + (image->dy * info->fix.line_length)
257		 + ((image->dx / 8) * 4);
258
259	for (y = 0; y < image->height; y++) {
260		src = src1;
261		dst = (u32 __iomem *) dst1;
262		for (x = 0; x < image->width; x += 8) {
263			val = expand_pixel(*(src++));
264			val = (val & fg) | (~val & bg);
265			fb_writel(val, dst++);
266		}
267		src1 += image->width / 8;
268		dst1 += info->fix.line_length;
269	}
270
271}
272
273static void arkfb_imageblit(struct fb_info *info, const struct fb_image *image)
274{
275	if ((info->var.bits_per_pixel == 4) && (image->depth == 1)
276	    && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) {
277		if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)
278			arkfb_iplan_imageblit(info, image);
279		else
280			arkfb_cfb4_imageblit(info, image);
281	} else
282		cfb_imageblit(info, image);
283}
284
285static void arkfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
286{
287	if ((info->var.bits_per_pixel == 4)
288	    && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0)
289	    && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES))
290		arkfb_iplan_fillrect(info, rect);
291	 else
292		cfb_fillrect(info, rect);
293}
294
295
296/* ------------------------------------------------------------------------- */
297
298
299enum
300{
301	DAC_PSEUDO8_8,
302	DAC_RGB1555_8,
303	DAC_RGB0565_8,
304	DAC_RGB0888_8,
305	DAC_RGB8888_8,
306	DAC_PSEUDO8_16,
307	DAC_RGB1555_16,
308	DAC_RGB0565_16,
309	DAC_RGB0888_16,
310	DAC_RGB8888_16,
311	DAC_MAX
312};
313
314struct dac_ops {
315	int (*dac_get_mode)(struct dac_info *info);
316	int (*dac_set_mode)(struct dac_info *info, int mode);
317	int (*dac_get_freq)(struct dac_info *info, int channel);
318	int (*dac_set_freq)(struct dac_info *info, int channel, u32 freq);
319	void (*dac_release)(struct dac_info *info);
320};
321
322typedef void (*dac_read_regs_t)(void *data, u8 *code, int count);
323typedef void (*dac_write_regs_t)(void *data, u8 *code, int count);
324
325struct dac_info
326{
327	struct dac_ops *dacops;
328	dac_read_regs_t dac_read_regs;
329	dac_write_regs_t dac_write_regs;
330	void *data;
331};
332
333
334static inline u8 dac_read_reg(struct dac_info *info, u8 reg)
335{
336	u8 code[2] = {reg, 0};
337	info->dac_read_regs(info->data, code, 1);
338	return code[1];
339}
340
341static inline void dac_read_regs(struct dac_info *info, u8 *code, int count)
342{
343	info->dac_read_regs(info->data, code, count);
344}
345
346static inline void dac_write_reg(struct dac_info *info, u8 reg, u8 val)
347{
348	u8 code[2] = {reg, val};
349	info->dac_write_regs(info->data, code, 1);
350}
351
352static inline void dac_write_regs(struct dac_info *info, u8 *code, int count)
353{
354	info->dac_write_regs(info->data, code, count);
355}
356
357static inline int dac_set_mode(struct dac_info *info, int mode)
358{
359	return info->dacops->dac_set_mode(info, mode);
360}
361
362static inline int dac_set_freq(struct dac_info *info, int channel, u32 freq)
363{
364	return info->dacops->dac_set_freq(info, channel, freq);
365}
366
367static inline void dac_release(struct dac_info *info)
368{
369	info->dacops->dac_release(info);
370}
371
372
373/* ------------------------------------------------------------------------- */
374
375
376/* ICS5342 DAC */
377
378struct ics5342_info
379{
380	struct dac_info dac;
381	u8 mode;
382};
383
384#define DAC_PAR(info) ((struct ics5342_info *) info)
385
386/* LSB is set to distinguish unused slots */
387static const u8 ics5342_mode_table[DAC_MAX] = {
388	[DAC_PSEUDO8_8]  = 0x01, [DAC_RGB1555_8]  = 0x21, [DAC_RGB0565_8]  = 0x61,
389	[DAC_RGB0888_8]  = 0x41, [DAC_PSEUDO8_16] = 0x11, [DAC_RGB1555_16] = 0x31,
390	[DAC_RGB0565_16] = 0x51, [DAC_RGB0888_16] = 0x91, [DAC_RGB8888_16] = 0x71
391};
392
393static int ics5342_set_mode(struct dac_info *info, int mode)
394{
395	u8 code;
396
397	if (mode >= DAC_MAX)
398		return -EINVAL;
399
400	code = ics5342_mode_table[mode];
401
402	if (! code)
403		return -EINVAL;
404
405	dac_write_reg(info, 6, code & 0xF0);
406	DAC_PAR(info)->mode = mode;
407
408	return 0;
409}
410
411static const struct svga_pll ics5342_pll = {3, 129, 3, 33, 0, 3,
412	60000, 250000, 14318};
413
414/* pd4 - allow only posdivider 4 (r=2) */
415static const struct svga_pll ics5342_pll_pd4 = {3, 129, 3, 33, 2, 2,
416	60000, 335000, 14318};
417
418/* 270 MHz should be upper bound for VCO clock according to specs,
419   but that is too restrictive in pd4 case */
420
421static int ics5342_set_freq(struct dac_info *info, int channel, u32 freq)
422{
423	u16 m, n, r;
424
425	/* only postdivider 4 (r=2) is valid in mode DAC_PSEUDO8_16 */
426	int rv = svga_compute_pll((DAC_PAR(info)->mode == DAC_PSEUDO8_16)
427				  ? &ics5342_pll_pd4 : &ics5342_pll,
428				  freq, &m, &n, &r, 0);
429
430	if (rv < 0) {
431		return -EINVAL;
432	} else {
433		u8 code[6] = {4, 3, 5, m-2, 5, (n-2) | (r << 5)};
434		dac_write_regs(info, code, 3);
435		return 0;
436	}
437}
438
439static void ics5342_release(struct dac_info *info)
440{
441	ics5342_set_mode(info, DAC_PSEUDO8_8);
442	kfree(info);
443}
444
445static struct dac_ops ics5342_ops = {
446	.dac_set_mode	= ics5342_set_mode,
447	.dac_set_freq	= ics5342_set_freq,
448	.dac_release	= ics5342_release
449};
450
451
452static struct dac_info * ics5342_init(dac_read_regs_t drr, dac_write_regs_t dwr, void *data)
453{
454	struct dac_info *info = kzalloc(sizeof(struct ics5342_info), GFP_KERNEL);
455
456	if (! info)
457		return NULL;
458
459	info->dacops = &ics5342_ops;
460	info->dac_read_regs = drr;
461	info->dac_write_regs = dwr;
462	info->data = data;
463	DAC_PAR(info)->mode = DAC_PSEUDO8_8; /* estimation */
464	return info;
465}
466
467
468/* ------------------------------------------------------------------------- */
469
470
471static unsigned short dac_regs[4] = {0x3c8, 0x3c9, 0x3c6, 0x3c7};
472
473static void ark_dac_read_regs(void *data, u8 *code, int count)
474{
475	struct fb_info *info = data;
476	struct arkfb_info *par;
477	u8 regval;
478
479	par = info->par;
480	regval = vga_rseq(par->state.vgabase, 0x1C);
481	while (count != 0)
482	{
483		vga_wseq(par->state.vgabase, 0x1C, regval | (code[0] & 4 ? 0x80 : 0));
484		code[1] = vga_r(par->state.vgabase, dac_regs[code[0] & 3]);
485		count--;
486		code += 2;
487	}
488
489	vga_wseq(par->state.vgabase, 0x1C, regval);
490}
491
492static void ark_dac_write_regs(void *data, u8 *code, int count)
493{
494	struct fb_info *info = data;
495	struct arkfb_info *par;
496	u8 regval;
497
498	par = info->par;
499	regval = vga_rseq(par->state.vgabase, 0x1C);
500	while (count != 0)
501	{
502		vga_wseq(par->state.vgabase, 0x1C, regval | (code[0] & 4 ? 0x80 : 0));
503		vga_w(par->state.vgabase, dac_regs[code[0] & 3], code[1]);
504		count--;
505		code += 2;
506	}
507
508	vga_wseq(par->state.vgabase, 0x1C, regval);
509}
510
511
512static void ark_set_pixclock(struct fb_info *info, u32 pixclock)
513{
514	struct arkfb_info *par = info->par;
515	u8 regval;
516
517	int rv = dac_set_freq(par->dac, 0, 1000000000 / pixclock);
518	if (rv < 0) {
519		fb_err(info, "cannot set requested pixclock, keeping old value\n");
520		return;
521	}
522
523	/* Set VGA misc register  */
524	regval = vga_r(par->state.vgabase, VGA_MIS_R);
525	vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
526}
527
528
529/* Open framebuffer */
530
531static int arkfb_open(struct fb_info *info, int user)
532{
533	struct arkfb_info *par = info->par;
534
535	mutex_lock(&(par->open_lock));
536	if (par->ref_count == 0) {
537		void __iomem *vgabase = par->state.vgabase;
538
539		memset(&(par->state), 0, sizeof(struct vgastate));
540		par->state.vgabase = vgabase;
541		par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;
542		par->state.num_crtc = 0x60;
543		par->state.num_seq = 0x30;
544		save_vga(&(par->state));
545	}
546
547	par->ref_count++;
548	mutex_unlock(&(par->open_lock));
549
550	return 0;
551}
552
553/* Close framebuffer */
554
555static int arkfb_release(struct fb_info *info, int user)
556{
557	struct arkfb_info *par = info->par;
558
559	mutex_lock(&(par->open_lock));
560	if (par->ref_count == 0) {
561		mutex_unlock(&(par->open_lock));
562		return -EINVAL;
563	}
564
565	if (par->ref_count == 1) {
566		restore_vga(&(par->state));
567		dac_set_mode(par->dac, DAC_PSEUDO8_8);
568	}
569
570	par->ref_count--;
571	mutex_unlock(&(par->open_lock));
572
573	return 0;
574}
575
576/* Validate passed in var */
577
578static int arkfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
579{
580	int rv, mem, step;
581
582	/* Find appropriate format */
583	rv = svga_match_format (arkfb_formats, var, NULL);
584	if (rv < 0)
585	{
586		fb_err(info, "unsupported mode requested\n");
587		return rv;
588	}
589
590	/* Do not allow to have real resoulution larger than virtual */
591	if (var->xres > var->xres_virtual)
592		var->xres_virtual = var->xres;
593
594	if (var->yres > var->yres_virtual)
595		var->yres_virtual = var->yres;
596
597	/* Round up xres_virtual to have proper alignment of lines */
598	step = arkfb_formats[rv].xresstep - 1;
599	var->xres_virtual = (var->xres_virtual+step) & ~step;
600
601
602	/* Check whether have enough memory */
603	mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual;
604	if (mem > info->screen_size)
605	{
606		fb_err(info, "not enough framebuffer memory (%d kB requested, %d kB available)\n",
607		       mem >> 10, (unsigned int) (info->screen_size >> 10));
608		return -EINVAL;
609	}
610
611	rv = svga_check_timings (&ark_timing_regs, var, info->node);
612	if (rv < 0)
613	{
614		fb_err(info, "invalid timings requested\n");
615		return rv;
616	}
617
618	/* Interlaced mode is broken */
619	if (var->vmode & FB_VMODE_INTERLACED)
620		return -EINVAL;
621
622	return 0;
623}
624
625/* Set video mode from par */
626
627static int arkfb_set_par(struct fb_info *info)
628{
629	struct arkfb_info *par = info->par;
630	u32 value, mode, hmul, hdiv, offset_value, screen_size;
631	u32 bpp = info->var.bits_per_pixel;
632	u8 regval;
633
634	if (bpp != 0) {
635		info->fix.ypanstep = 1;
636		info->fix.line_length = (info->var.xres_virtual * bpp) / 8;
637
638		info->flags &= ~FBINFO_MISC_TILEBLITTING;
639		info->tileops = NULL;
640
641		/* in 4bpp supports 8p wide tiles only, any tiles otherwise */
642		info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0);
643		info->pixmap.blit_y = ~(u32)0;
644
645		offset_value = (info->var.xres_virtual * bpp) / 64;
646		screen_size = info->var.yres_virtual * info->fix.line_length;
647	} else {
648		info->fix.ypanstep = 16;
649		info->fix.line_length = 0;
650
651		info->flags |= FBINFO_MISC_TILEBLITTING;
652		info->tileops = &arkfb_tile_ops;
653
654		/* supports 8x16 tiles only */
655		info->pixmap.blit_x = 1 << (8 - 1);
656		info->pixmap.blit_y = 1 << (16 - 1);
657
658		offset_value = info->var.xres_virtual / 16;
659		screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64;
660	}
661
662	info->var.xoffset = 0;
663	info->var.yoffset = 0;
664	info->var.activate = FB_ACTIVATE_NOW;
665
666	/* Unlock registers */
667	svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80);
668
669	/* Blank screen and turn off sync */
670	svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
671	svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
672
673	/* Set default values */
674	svga_set_default_gfx_regs(par->state.vgabase);
675	svga_set_default_atc_regs(par->state.vgabase);
676	svga_set_default_seq_regs(par->state.vgabase);
677	svga_set_default_crt_regs(par->state.vgabase);
678	svga_wcrt_multi(par->state.vgabase, ark_line_compare_regs, 0xFFFFFFFF);
679	svga_wcrt_multi(par->state.vgabase, ark_start_address_regs, 0);
680
681	/* ARK specific initialization */
682	svga_wseq_mask(par->state.vgabase, 0x10, 0x1F, 0x1F); /* enable linear framebuffer and full memory access */
683	svga_wseq_mask(par->state.vgabase, 0x12, 0x03, 0x03); /* 4 MB linear framebuffer size */
684
685	vga_wseq(par->state.vgabase, 0x13, info->fix.smem_start >> 16);
686	vga_wseq(par->state.vgabase, 0x14, info->fix.smem_start >> 24);
687	vga_wseq(par->state.vgabase, 0x15, 0);
688	vga_wseq(par->state.vgabase, 0x16, 0);
689
690	/* Set the FIFO threshold register */
691	/* It is fascinating way to store 5-bit value in 8-bit register */
692	regval = 0x10 | ((threshold & 0x0E) >> 1) | (threshold & 0x01) << 7 | (threshold & 0x10) << 1;
693	vga_wseq(par->state.vgabase, 0x18, regval);
694
695	/* Set the offset register */
696	fb_dbg(info, "offset register       : %d\n", offset_value);
697	svga_wcrt_multi(par->state.vgabase, ark_offset_regs, offset_value);
698
699	/* fix for hi-res textmode */
700	svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08);
701
702	if (info->var.vmode & FB_VMODE_DOUBLE)
703		svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80);
704	else
705		svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80);
706
707	if (info->var.vmode & FB_VMODE_INTERLACED)
708		svga_wcrt_mask(par->state.vgabase, 0x44, 0x04, 0x04);
709	else
710		svga_wcrt_mask(par->state.vgabase, 0x44, 0x00, 0x04);
711
712	hmul = 1;
713	hdiv = 1;
714	mode = svga_match_format(arkfb_formats, &(info->var), &(info->fix));
715
716	/* Set mode-specific register values */
717	switch (mode) {
718	case 0:
719		fb_dbg(info, "text mode\n");
720		svga_set_textmode_vga_regs(par->state.vgabase);
721
722		vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */
723		svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
724		dac_set_mode(par->dac, DAC_PSEUDO8_8);
725
726		break;
727	case 1:
728		fb_dbg(info, "4 bit pseudocolor\n");
729		vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40);
730
731		vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */
732		svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
733		dac_set_mode(par->dac, DAC_PSEUDO8_8);
734		break;
735	case 2:
736		fb_dbg(info, "4 bit pseudocolor, planar\n");
737
738		vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */
739		svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
740		dac_set_mode(par->dac, DAC_PSEUDO8_8);
741		break;
742	case 3:
743		fb_dbg(info, "8 bit pseudocolor\n");
744
745		vga_wseq(par->state.vgabase, 0x11, 0x16); /* 8bpp accel mode */
746
747		if (info->var.pixclock > 20000) {
748			fb_dbg(info, "not using multiplex\n");
749			svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
750			dac_set_mode(par->dac, DAC_PSEUDO8_8);
751		} else {
752			fb_dbg(info, "using multiplex\n");
753			svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
754			dac_set_mode(par->dac, DAC_PSEUDO8_16);
755			hdiv = 2;
756		}
757		break;
758	case 4:
759		fb_dbg(info, "5/5/5 truecolor\n");
760
761		vga_wseq(par->state.vgabase, 0x11, 0x1A); /* 16bpp accel mode */
762		svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
763		dac_set_mode(par->dac, DAC_RGB1555_16);
764		break;
765	case 5:
766		fb_dbg(info, "5/6/5 truecolor\n");
767
768		vga_wseq(par->state.vgabase, 0x11, 0x1A); /* 16bpp accel mode */
769		svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
770		dac_set_mode(par->dac, DAC_RGB0565_16);
771		break;
772	case 6:
773		fb_dbg(info, "8/8/8 truecolor\n");
774
775		vga_wseq(par->state.vgabase, 0x11, 0x16); /* 8bpp accel mode ??? */
776		svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
777		dac_set_mode(par->dac, DAC_RGB0888_16);
778		hmul = 3;
779		hdiv = 2;
780		break;
781	case 7:
782		fb_dbg(info, "8/8/8/8 truecolor\n");
783
784		vga_wseq(par->state.vgabase, 0x11, 0x1E); /* 32bpp accel mode */
785		svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
786		dac_set_mode(par->dac, DAC_RGB8888_16);
787		hmul = 2;
788		break;
789	default:
790		fb_err(info, "unsupported mode - bug\n");
791		return -EINVAL;
792	}
793
794	ark_set_pixclock(info, (hdiv * info->var.pixclock) / hmul);
795	svga_set_timings(par->state.vgabase, &ark_timing_regs, &(info->var), hmul, hdiv,
796			 (info->var.vmode & FB_VMODE_DOUBLE)     ? 2 : 1,
797			 (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1,
798			  hmul, info->node);
799
800	/* Set interlaced mode start/end register */
801	value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len;
802	value = ((value * hmul / hdiv) / 8) - 5;
803	vga_wcrt(par->state.vgabase, 0x42, (value + 1) / 2);
804
805	memset_io(info->screen_base, 0x00, screen_size);
806	/* Device and screen back on */
807	svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
808	svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
809
810	return 0;
811}
812
813/* Set a colour register */
814
815static int arkfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
816				u_int transp, struct fb_info *fb)
817{
818	switch (fb->var.bits_per_pixel) {
819	case 0:
820	case 4:
821		if (regno >= 16)
822			return -EINVAL;
823
824		if ((fb->var.bits_per_pixel == 4) &&
825		    (fb->var.nonstd == 0)) {
826			outb(0xF0, VGA_PEL_MSK);
827			outb(regno*16, VGA_PEL_IW);
828		} else {
829			outb(0x0F, VGA_PEL_MSK);
830			outb(regno, VGA_PEL_IW);
831		}
832		outb(red >> 10, VGA_PEL_D);
833		outb(green >> 10, VGA_PEL_D);
834		outb(blue >> 10, VGA_PEL_D);
835		break;
836	case 8:
837		if (regno >= 256)
838			return -EINVAL;
839
840		outb(0xFF, VGA_PEL_MSK);
841		outb(regno, VGA_PEL_IW);
842		outb(red >> 10, VGA_PEL_D);
843		outb(green >> 10, VGA_PEL_D);
844		outb(blue >> 10, VGA_PEL_D);
845		break;
846	case 16:
847		if (regno >= 16)
848			return 0;
849
850		if (fb->var.green.length == 5)
851			((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) |
852				((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11);
853		else if (fb->var.green.length == 6)
854			((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) |
855				((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
856		else
857			return -EINVAL;
858		break;
859	case 24:
860	case 32:
861		if (regno >= 16)
862			return 0;
863
864		((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) |
865			(green & 0xFF00) | ((blue & 0xFF00) >> 8);
866		break;
867	default:
868		return -EINVAL;
869	}
870
871	return 0;
872}
873
874/* Set the display blanking state */
875
876static int arkfb_blank(int blank_mode, struct fb_info *info)
877{
878	struct arkfb_info *par = info->par;
879
880	switch (blank_mode) {
881	case FB_BLANK_UNBLANK:
882		fb_dbg(info, "unblank\n");
883		svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
884		svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
885		break;
886	case FB_BLANK_NORMAL:
887		fb_dbg(info, "blank\n");
888		svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
889		svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
890		break;
891	case FB_BLANK_POWERDOWN:
892	case FB_BLANK_HSYNC_SUSPEND:
893	case FB_BLANK_VSYNC_SUSPEND:
894		fb_dbg(info, "sync down\n");
895		svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
896		svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
897		break;
898	}
899	return 0;
900}
901
902
903/* Pan the display */
904
905static int arkfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
906{
907	struct arkfb_info *par = info->par;
908	unsigned int offset;
909
910	/* Calculate the offset */
911	if (info->var.bits_per_pixel == 0) {
912		offset = (var->yoffset / 16) * (info->var.xres_virtual / 2)
913		       + (var->xoffset / 2);
914		offset = offset >> 2;
915	} else {
916		offset = (var->yoffset * info->fix.line_length) +
917			 (var->xoffset * info->var.bits_per_pixel / 8);
918		offset = offset >> ((info->var.bits_per_pixel == 4) ? 2 : 3);
919	}
920
921	/* Set the offset */
922	svga_wcrt_multi(par->state.vgabase, ark_start_address_regs, offset);
923
924	return 0;
925}
926
927
928/* ------------------------------------------------------------------------- */
929
930
931/* Frame buffer operations */
932
933static struct fb_ops arkfb_ops = {
934	.owner		= THIS_MODULE,
935	.fb_open	= arkfb_open,
936	.fb_release	= arkfb_release,
937	.fb_check_var	= arkfb_check_var,
938	.fb_set_par	= arkfb_set_par,
939	.fb_setcolreg	= arkfb_setcolreg,
940	.fb_blank	= arkfb_blank,
941	.fb_pan_display	= arkfb_pan_display,
942	.fb_fillrect	= arkfb_fillrect,
943	.fb_copyarea	= cfb_copyarea,
944	.fb_imageblit	= arkfb_imageblit,
945	.fb_get_caps    = svga_get_caps,
946};
947
948
949/* ------------------------------------------------------------------------- */
950
951
952/* PCI probe */
953static int ark_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
954{
955	struct pci_bus_region bus_reg;
956	struct resource vga_res;
957	struct fb_info *info;
958	struct arkfb_info *par;
959	int rc;
960	u8 regval;
961
962	/* Ignore secondary VGA device because there is no VGA arbitration */
963	if (! svga_primary_device(dev)) {
964		dev_info(&(dev->dev), "ignoring secondary device\n");
965		return -ENODEV;
966	}
967
968	/* Allocate and fill driver data structure */
969	info = framebuffer_alloc(sizeof(struct arkfb_info), &(dev->dev));
970	if (! info) {
971		dev_err(&(dev->dev), "cannot allocate memory\n");
972		return -ENOMEM;
973	}
974
975	par = info->par;
976	mutex_init(&par->open_lock);
977
978	info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN;
979	info->fbops = &arkfb_ops;
980
981	/* Prepare PCI device */
982	rc = pci_enable_device(dev);
983	if (rc < 0) {
984		dev_err(info->device, "cannot enable PCI device\n");
985		goto err_enable_device;
986	}
987
988	rc = pci_request_regions(dev, "arkfb");
989	if (rc < 0) {
990		dev_err(info->device, "cannot reserve framebuffer region\n");
991		goto err_request_regions;
992	}
993
994	par->dac = ics5342_init(ark_dac_read_regs, ark_dac_write_regs, info);
995	if (! par->dac) {
996		rc = -ENOMEM;
997		dev_err(info->device, "RAMDAC initialization failed\n");
998		goto err_dac;
999	}
1000
1001	info->fix.smem_start = pci_resource_start(dev, 0);
1002	info->fix.smem_len = pci_resource_len(dev, 0);
1003
1004	/* Map physical IO memory address into kernel space */
1005	info->screen_base = pci_iomap(dev, 0, 0);
1006	if (! info->screen_base) {
1007		rc = -ENOMEM;
1008		dev_err(info->device, "iomap for framebuffer failed\n");
1009		goto err_iomap;
1010	}
1011
1012	bus_reg.start = 0;
1013	bus_reg.end = 64 * 1024;
1014
1015	vga_res.flags = IORESOURCE_IO;
1016
1017	pcibios_bus_to_resource(dev->bus, &vga_res, &bus_reg);
1018
1019	par->state.vgabase = (void __iomem *) (unsigned long) vga_res.start;
1020
1021	/* FIXME get memsize */
1022	regval = vga_rseq(par->state.vgabase, 0x10);
1023	info->screen_size = (1 << (regval >> 6)) << 20;
1024	info->fix.smem_len = info->screen_size;
1025
1026	strcpy(info->fix.id, "ARK 2000PV");
1027	info->fix.mmio_start = 0;
1028	info->fix.mmio_len = 0;
1029	info->fix.type = FB_TYPE_PACKED_PIXELS;
1030	info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1031	info->fix.ypanstep = 0;
1032	info->fix.accel = FB_ACCEL_NONE;
1033	info->pseudo_palette = (void*) (par->pseudo_palette);
1034
1035	/* Prepare startup mode */
1036	rc = fb_find_mode(&(info->var), info, mode_option, NULL, 0, NULL, 8);
1037	if (! ((rc == 1) || (rc == 2))) {
1038		rc = -EINVAL;
1039		dev_err(info->device, "mode %s not found\n", mode_option);
1040		goto err_find_mode;
1041	}
1042
1043	rc = fb_alloc_cmap(&info->cmap, 256, 0);
1044	if (rc < 0) {
1045		dev_err(info->device, "cannot allocate colormap\n");
1046		goto err_alloc_cmap;
1047	}
1048
1049	rc = register_framebuffer(info);
1050	if (rc < 0) {
1051		dev_err(info->device, "cannot register framebuffer\n");
1052		goto err_reg_fb;
1053	}
1054
1055	fb_info(info, "%s on %s, %d MB RAM\n",
1056		info->fix.id, pci_name(dev), info->fix.smem_len >> 20);
1057
1058	/* Record a reference to the driver data */
1059	pci_set_drvdata(dev, info);
1060
1061#ifdef CONFIG_MTRR
1062	if (mtrr) {
1063		par->mtrr_reg = -1;
1064		par->mtrr_reg = mtrr_add(info->fix.smem_start, info->fix.smem_len, MTRR_TYPE_WRCOMB, 1);
1065	}
1066#endif
1067
1068	return 0;
1069
1070	/* Error handling */
1071err_reg_fb:
1072	fb_dealloc_cmap(&info->cmap);
1073err_alloc_cmap:
1074err_find_mode:
1075	pci_iounmap(dev, info->screen_base);
1076err_iomap:
1077	dac_release(par->dac);
1078err_dac:
1079	pci_release_regions(dev);
1080err_request_regions:
1081/*	pci_disable_device(dev); */
1082err_enable_device:
1083	framebuffer_release(info);
1084	return rc;
1085}
1086
1087/* PCI remove */
1088
1089static void ark_pci_remove(struct pci_dev *dev)
1090{
1091	struct fb_info *info = pci_get_drvdata(dev);
1092
1093	if (info) {
1094		struct arkfb_info *par = info->par;
1095
1096#ifdef CONFIG_MTRR
1097		if (par->mtrr_reg >= 0) {
1098			mtrr_del(par->mtrr_reg, 0, 0);
1099			par->mtrr_reg = -1;
1100		}
1101#endif
1102
1103		dac_release(par->dac);
1104		unregister_framebuffer(info);
1105		fb_dealloc_cmap(&info->cmap);
1106
1107		pci_iounmap(dev, info->screen_base);
1108		pci_release_regions(dev);
1109/*		pci_disable_device(dev); */
1110
1111		framebuffer_release(info);
1112	}
1113}
1114
1115
1116#ifdef CONFIG_PM
1117/* PCI suspend */
1118
1119static int ark_pci_suspend (struct pci_dev* dev, pm_message_t state)
1120{
1121	struct fb_info *info = pci_get_drvdata(dev);
1122	struct arkfb_info *par = info->par;
1123
1124	dev_info(info->device, "suspend\n");
1125
1126	console_lock();
1127	mutex_lock(&(par->open_lock));
1128
1129	if ((state.event == PM_EVENT_FREEZE) || (par->ref_count == 0)) {
1130		mutex_unlock(&(par->open_lock));
1131		console_unlock();
1132		return 0;
1133	}
1134
1135	fb_set_suspend(info, 1);
1136
1137	pci_save_state(dev);
1138	pci_disable_device(dev);
1139	pci_set_power_state(dev, pci_choose_state(dev, state));
1140
1141	mutex_unlock(&(par->open_lock));
1142	console_unlock();
1143
1144	return 0;
1145}
1146
1147
1148/* PCI resume */
1149
1150static int ark_pci_resume (struct pci_dev* dev)
1151{
1152	struct fb_info *info = pci_get_drvdata(dev);
1153	struct arkfb_info *par = info->par;
1154
1155	dev_info(info->device, "resume\n");
1156
1157	console_lock();
1158	mutex_lock(&(par->open_lock));
1159
1160	if (par->ref_count == 0)
1161		goto fail;
1162
1163	pci_set_power_state(dev, PCI_D0);
1164	pci_restore_state(dev);
1165
1166	if (pci_enable_device(dev))
1167		goto fail;
1168
1169	pci_set_master(dev);
1170
1171	arkfb_set_par(info);
1172	fb_set_suspend(info, 0);
1173
1174fail:
1175	mutex_unlock(&(par->open_lock));
1176	console_unlock();
1177	return 0;
1178}
1179#else
1180#define ark_pci_suspend NULL
1181#define ark_pci_resume NULL
1182#endif /* CONFIG_PM */
1183
1184/* List of boards that we are trying to support */
1185
1186static struct pci_device_id ark_devices[] = {
1187	{PCI_DEVICE(0xEDD8, 0xA099)},
1188	{0, 0, 0, 0, 0, 0, 0}
1189};
1190
1191
1192MODULE_DEVICE_TABLE(pci, ark_devices);
1193
1194static struct pci_driver arkfb_pci_driver = {
1195	.name		= "arkfb",
1196	.id_table	= ark_devices,
1197	.probe		= ark_pci_probe,
1198	.remove		= ark_pci_remove,
1199	.suspend	= ark_pci_suspend,
1200	.resume		= ark_pci_resume,
1201};
1202
1203/* Cleanup */
1204
1205static void __exit arkfb_cleanup(void)
1206{
1207	pr_debug("arkfb: cleaning up\n");
1208	pci_unregister_driver(&arkfb_pci_driver);
1209}
1210
1211/* Driver Initialisation */
1212
1213static int __init arkfb_init(void)
1214{
1215
1216#ifndef MODULE
1217	char *option = NULL;
1218
1219	if (fb_get_options("arkfb", &option))
1220		return -ENODEV;
1221
1222	if (option && *option)
1223		mode_option = option;
1224#endif
1225
1226	pr_debug("arkfb: initializing\n");
1227	return pci_register_driver(&arkfb_pci_driver);
1228}
1229
1230module_init(arkfb_init);
1231module_exit(arkfb_cleanup);
1232