1/* 2 * linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver 3 * 4 * Maintained by Ani Joshi <ajoshi@shell.unixbox.com> 5 * 6 * Copyright 1999-2000 Jeff Garzik 7 * 8 * Contributors: 9 * 10 * Ani Joshi: Lots of debugging and cleanup work, really helped 11 * get the driver going 12 * 13 * Ferenc Bakonyi: Bug fixes, cleanup, modularization 14 * 15 * Jindrich Makovicka: Accel code help, hw cursor, mtrr 16 * 17 * Paul Richards: Bug fixes, updates 18 * 19 * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven 20 * Includes riva_hw.c from nVidia, see copyright below. 21 * KGI code provided the basis for state storage, init, and mode switching. 22 * 23 * This file is subject to the terms and conditions of the GNU General Public 24 * License. See the file COPYING in the main directory of this archive 25 * for more details. 26 * 27 * Known bugs and issues: 28 * restoring text mode fails 29 * doublescan modes are broken 30 */ 31 32#include <linux/module.h> 33#include <linux/kernel.h> 34#include <linux/errno.h> 35#include <linux/string.h> 36#include <linux/mm.h> 37#include <linux/slab.h> 38#include <linux/delay.h> 39#include <linux/fb.h> 40#include <linux/init.h> 41#include <linux/pci.h> 42#include <linux/backlight.h> 43#include <linux/bitrev.h> 44#ifdef CONFIG_MTRR 45#include <asm/mtrr.h> 46#endif 47#ifdef CONFIG_PMAC_BACKLIGHT 48#include <asm/machdep.h> 49#include <asm/backlight.h> 50#endif 51 52#include "rivafb.h" 53#include "nvreg.h" 54 55/* version number of this driver */ 56#define RIVAFB_VERSION "0.9.5b" 57 58/* ------------------------------------------------------------------------- * 59 * 60 * various helpful macros and constants 61 * 62 * ------------------------------------------------------------------------- */ 63#ifdef CONFIG_FB_RIVA_DEBUG 64#define NVTRACE printk 65#else 66#define NVTRACE if(0) printk 67#endif 68 69#define NVTRACE_ENTER(...) NVTRACE("%s START\n", __func__) 70#define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __func__) 71 72#ifdef CONFIG_FB_RIVA_DEBUG 73#define assert(expr) \ 74 if(!(expr)) { \ 75 printk( "Assertion failed! %s,%s,%s,line=%d\n",\ 76 #expr,__FILE__,__func__,__LINE__); \ 77 BUG(); \ 78 } 79#else 80#define assert(expr) 81#endif 82 83#define PFX "rivafb: " 84 85/* macro that allows you to set overflow bits */ 86#define SetBitField(value,from,to) SetBF(to,GetBF(value,from)) 87#define SetBit(n) (1<<(n)) 88#define Set8Bits(value) ((value)&0xff) 89 90/* HW cursor parameters */ 91#define MAX_CURS 32 92 93/* ------------------------------------------------------------------------- * 94 * 95 * prototypes 96 * 97 * ------------------------------------------------------------------------- */ 98 99static int rivafb_blank(int blank, struct fb_info *info); 100 101/* ------------------------------------------------------------------------- * 102 * 103 * card identification 104 * 105 * ------------------------------------------------------------------------- */ 106 107static struct pci_device_id rivafb_pci_tbl[] = { 108 { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128, 109 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 110 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT, 111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 112 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2, 113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 114 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2, 115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 116 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2, 117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 118 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2, 119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 120 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2, 121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 122 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR, 123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 124 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR, 125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 126 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO, 127 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 128 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX, 129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 130 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2, 131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 132 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO, 133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 134 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR, 135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 136 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS, 137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 138 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2, 139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 140 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA, 141 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 142 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO, 143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 144 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460, 145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 146 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440, 147 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 148 // NF2/IGP version, GeForce 4 MX, NV18 149 { PCI_VENDOR_ID_NVIDIA, 0x01f0, 150 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 151 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420, 152 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 153 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO, 154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 155 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO, 156 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 157 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32, 158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 159 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL, 160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 161 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64, 162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 163 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200, 164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 165 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL, 166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 167 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL, 168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 169 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2, 170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 171 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3, 172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 173 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1, 174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 175 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2, 176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 177 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC, 178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 179 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600, 180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 181 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400, 182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 183 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200, 184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 185 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL, 186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 187 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL, 188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 189 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL, 190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 191 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200, 192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 193 { 0, } /* terminate list */ 194}; 195MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl); 196 197/* ------------------------------------------------------------------------- * 198 * 199 * global variables 200 * 201 * ------------------------------------------------------------------------- */ 202 203/* command line data, set in rivafb_setup() */ 204static int flatpanel = -1; /* Autodetect later */ 205static int forceCRTC = -1; 206static bool noaccel = 0; 207#ifdef CONFIG_MTRR 208static bool nomtrr = 0; 209#endif 210#ifdef CONFIG_PMAC_BACKLIGHT 211static int backlight = 1; 212#else 213static int backlight = 0; 214#endif 215 216static char *mode_option = NULL; 217static bool strictmode = 0; 218 219static struct fb_fix_screeninfo rivafb_fix = { 220 .type = FB_TYPE_PACKED_PIXELS, 221 .xpanstep = 1, 222 .ypanstep = 1, 223}; 224 225static struct fb_var_screeninfo rivafb_default_var = { 226 .xres = 640, 227 .yres = 480, 228 .xres_virtual = 640, 229 .yres_virtual = 480, 230 .bits_per_pixel = 8, 231 .red = {0, 8, 0}, 232 .green = {0, 8, 0}, 233 .blue = {0, 8, 0}, 234 .transp = {0, 0, 0}, 235 .activate = FB_ACTIVATE_NOW, 236 .height = -1, 237 .width = -1, 238 .pixclock = 39721, 239 .left_margin = 40, 240 .right_margin = 24, 241 .upper_margin = 32, 242 .lower_margin = 11, 243 .hsync_len = 96, 244 .vsync_len = 2, 245 .vmode = FB_VMODE_NONINTERLACED 246}; 247 248/* from GGI */ 249static const struct riva_regs reg_template = { 250 {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */ 251 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 252 0x41, 0x01, 0x0F, 0x00, 0x00}, 253 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */ 254 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 255 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */ 256 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 257 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */ 258 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 259 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */ 260 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 261 0x00, /* 0x40 */ 262 }, 263 {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */ 264 0xFF}, 265 {0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */ 266 0xEB /* MISC */ 267}; 268 269/* 270 * Backlight control 271 */ 272#ifdef CONFIG_FB_RIVA_BACKLIGHT 273/* We do not have any information about which values are allowed, thus 274 * we used safe values. 275 */ 276#define MIN_LEVEL 0x158 277#define MAX_LEVEL 0x534 278#define LEVEL_STEP ((MAX_LEVEL - MIN_LEVEL) / FB_BACKLIGHT_MAX) 279 280static int riva_bl_get_level_brightness(struct riva_par *par, 281 int level) 282{ 283 struct fb_info *info = pci_get_drvdata(par->pdev); 284 int nlevel; 285 286 /* Get and convert the value */ 287 /* No locking on bl_curve since accessing a single value */ 288 nlevel = MIN_LEVEL + info->bl_curve[level] * LEVEL_STEP; 289 290 if (nlevel < 0) 291 nlevel = 0; 292 else if (nlevel < MIN_LEVEL) 293 nlevel = MIN_LEVEL; 294 else if (nlevel > MAX_LEVEL) 295 nlevel = MAX_LEVEL; 296 297 return nlevel; 298} 299 300static int riva_bl_update_status(struct backlight_device *bd) 301{ 302 struct riva_par *par = bl_get_data(bd); 303 U032 tmp_pcrt, tmp_pmc; 304 int level; 305 306 if (bd->props.power != FB_BLANK_UNBLANK || 307 bd->props.fb_blank != FB_BLANK_UNBLANK) 308 level = 0; 309 else 310 level = bd->props.brightness; 311 312 tmp_pmc = NV_RD32(par->riva.PMC, 0x10F0) & 0x0000FFFF; 313 tmp_pcrt = NV_RD32(par->riva.PCRTC0, 0x081C) & 0xFFFFFFFC; 314 if(level > 0) { 315 tmp_pcrt |= 0x1; 316 tmp_pmc |= (1 << 31); /* backlight bit */ 317 tmp_pmc |= riva_bl_get_level_brightness(par, level) << 16; /* level */ 318 } 319 NV_WR32(par->riva.PCRTC0, 0x081C, tmp_pcrt); 320 NV_WR32(par->riva.PMC, 0x10F0, tmp_pmc); 321 322 return 0; 323} 324 325static const struct backlight_ops riva_bl_ops = { 326 .update_status = riva_bl_update_status, 327}; 328 329static void riva_bl_init(struct riva_par *par) 330{ 331 struct backlight_properties props; 332 struct fb_info *info = pci_get_drvdata(par->pdev); 333 struct backlight_device *bd; 334 char name[12]; 335 336 if (!par->FlatPanel) 337 return; 338 339#ifdef CONFIG_PMAC_BACKLIGHT 340 if (!machine_is(powermac) || 341 !pmac_has_backlight_type("mnca")) 342 return; 343#endif 344 345 snprintf(name, sizeof(name), "rivabl%d", info->node); 346 347 memset(&props, 0, sizeof(struct backlight_properties)); 348 props.type = BACKLIGHT_RAW; 349 props.max_brightness = FB_BACKLIGHT_LEVELS - 1; 350 bd = backlight_device_register(name, info->dev, par, &riva_bl_ops, 351 &props); 352 if (IS_ERR(bd)) { 353 info->bl_dev = NULL; 354 printk(KERN_WARNING "riva: Backlight registration failed\n"); 355 goto error; 356 } 357 358 info->bl_dev = bd; 359 fb_bl_default_curve(info, 0, 360 MIN_LEVEL * FB_BACKLIGHT_MAX / MAX_LEVEL, 361 FB_BACKLIGHT_MAX); 362 363 bd->props.brightness = bd->props.max_brightness; 364 bd->props.power = FB_BLANK_UNBLANK; 365 backlight_update_status(bd); 366 367 printk("riva: Backlight initialized (%s)\n", name); 368 369 return; 370 371error: 372 return; 373} 374 375static void riva_bl_exit(struct fb_info *info) 376{ 377 struct backlight_device *bd = info->bl_dev; 378 379 backlight_device_unregister(bd); 380 printk("riva: Backlight unloaded\n"); 381} 382#else 383static inline void riva_bl_init(struct riva_par *par) {} 384static inline void riva_bl_exit(struct fb_info *info) {} 385#endif /* CONFIG_FB_RIVA_BACKLIGHT */ 386 387/* ------------------------------------------------------------------------- * 388 * 389 * MMIO access macros 390 * 391 * ------------------------------------------------------------------------- */ 392 393static inline void CRTCout(struct riva_par *par, unsigned char index, 394 unsigned char val) 395{ 396 VGA_WR08(par->riva.PCIO, 0x3d4, index); 397 VGA_WR08(par->riva.PCIO, 0x3d5, val); 398} 399 400static inline unsigned char CRTCin(struct riva_par *par, 401 unsigned char index) 402{ 403 VGA_WR08(par->riva.PCIO, 0x3d4, index); 404 return (VGA_RD08(par->riva.PCIO, 0x3d5)); 405} 406 407static inline void GRAout(struct riva_par *par, unsigned char index, 408 unsigned char val) 409{ 410 VGA_WR08(par->riva.PVIO, 0x3ce, index); 411 VGA_WR08(par->riva.PVIO, 0x3cf, val); 412} 413 414static inline unsigned char GRAin(struct riva_par *par, 415 unsigned char index) 416{ 417 VGA_WR08(par->riva.PVIO, 0x3ce, index); 418 return (VGA_RD08(par->riva.PVIO, 0x3cf)); 419} 420 421static inline void SEQout(struct riva_par *par, unsigned char index, 422 unsigned char val) 423{ 424 VGA_WR08(par->riva.PVIO, 0x3c4, index); 425 VGA_WR08(par->riva.PVIO, 0x3c5, val); 426} 427 428static inline unsigned char SEQin(struct riva_par *par, 429 unsigned char index) 430{ 431 VGA_WR08(par->riva.PVIO, 0x3c4, index); 432 return (VGA_RD08(par->riva.PVIO, 0x3c5)); 433} 434 435static inline void ATTRout(struct riva_par *par, unsigned char index, 436 unsigned char val) 437{ 438 VGA_WR08(par->riva.PCIO, 0x3c0, index); 439 VGA_WR08(par->riva.PCIO, 0x3c0, val); 440} 441 442static inline unsigned char ATTRin(struct riva_par *par, 443 unsigned char index) 444{ 445 VGA_WR08(par->riva.PCIO, 0x3c0, index); 446 return (VGA_RD08(par->riva.PCIO, 0x3c1)); 447} 448 449static inline void MISCout(struct riva_par *par, unsigned char val) 450{ 451 VGA_WR08(par->riva.PVIO, 0x3c2, val); 452} 453 454static inline unsigned char MISCin(struct riva_par *par) 455{ 456 return (VGA_RD08(par->riva.PVIO, 0x3cc)); 457} 458 459static inline void reverse_order(u32 *l) 460{ 461 u8 *a = (u8 *)l; 462 a[0] = bitrev8(a[0]); 463 a[1] = bitrev8(a[1]); 464 a[2] = bitrev8(a[2]); 465 a[3] = bitrev8(a[3]); 466} 467 468/* ------------------------------------------------------------------------- * 469 * 470 * cursor stuff 471 * 472 * ------------------------------------------------------------------------- */ 473 474/** 475 * rivafb_load_cursor_image - load cursor image to hardware 476 * @data: address to monochrome bitmap (1 = foreground color, 0 = background) 477 * @par: pointer to private data 478 * @w: width of cursor image in pixels 479 * @h: height of cursor image in scanlines 480 * @bg: background color (ARGB1555) - alpha bit determines opacity 481 * @fg: foreground color (ARGB1555) 482 * 483 * DESCRIPTiON: 484 * Loads cursor image based on a monochrome source and mask bitmap. The 485 * image bits determines the color of the pixel, 0 for background, 1 for 486 * foreground. Only the affected region (as determined by @w and @h 487 * parameters) will be updated. 488 * 489 * CALLED FROM: 490 * rivafb_cursor() 491 */ 492static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8, 493 u16 bg, u16 fg, u32 w, u32 h) 494{ 495 int i, j, k = 0; 496 u32 b, tmp; 497 u32 *data = (u32 *)data8; 498 bg = le16_to_cpu(bg); 499 fg = le16_to_cpu(fg); 500 501 w = (w + 1) & ~1; 502 503 for (i = 0; i < h; i++) { 504 b = *data++; 505 reverse_order(&b); 506 507 for (j = 0; j < w/2; j++) { 508 tmp = 0; 509#if defined (__BIG_ENDIAN) 510 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16; 511 b <<= 1; 512 tmp |= (b & (1 << 31)) ? fg : bg; 513 b <<= 1; 514#else 515 tmp = (b & 1) ? fg : bg; 516 b >>= 1; 517 tmp |= (b & 1) ? fg << 16 : bg << 16; 518 b >>= 1; 519#endif 520 writel(tmp, &par->riva.CURSOR[k++]); 521 } 522 k += (MAX_CURS - w)/2; 523 } 524} 525 526/* ------------------------------------------------------------------------- * 527 * 528 * general utility functions 529 * 530 * ------------------------------------------------------------------------- */ 531 532/** 533 * riva_wclut - set CLUT entry 534 * @chip: pointer to RIVA_HW_INST object 535 * @regnum: register number 536 * @red: red component 537 * @green: green component 538 * @blue: blue component 539 * 540 * DESCRIPTION: 541 * Sets color register @regnum. 542 * 543 * CALLED FROM: 544 * rivafb_setcolreg() 545 */ 546static void riva_wclut(RIVA_HW_INST *chip, 547 unsigned char regnum, unsigned char red, 548 unsigned char green, unsigned char blue) 549{ 550 VGA_WR08(chip->PDIO, 0x3c8, regnum); 551 VGA_WR08(chip->PDIO, 0x3c9, red); 552 VGA_WR08(chip->PDIO, 0x3c9, green); 553 VGA_WR08(chip->PDIO, 0x3c9, blue); 554} 555 556/** 557 * riva_rclut - read fromCLUT register 558 * @chip: pointer to RIVA_HW_INST object 559 * @regnum: register number 560 * @red: red component 561 * @green: green component 562 * @blue: blue component 563 * 564 * DESCRIPTION: 565 * Reads red, green, and blue from color register @regnum. 566 * 567 * CALLED FROM: 568 * rivafb_setcolreg() 569 */ 570static void riva_rclut(RIVA_HW_INST *chip, 571 unsigned char regnum, unsigned char *red, 572 unsigned char *green, unsigned char *blue) 573{ 574 575 VGA_WR08(chip->PDIO, 0x3c7, regnum); 576 *red = VGA_RD08(chip->PDIO, 0x3c9); 577 *green = VGA_RD08(chip->PDIO, 0x3c9); 578 *blue = VGA_RD08(chip->PDIO, 0x3c9); 579} 580 581/** 582 * riva_save_state - saves current chip state 583 * @par: pointer to riva_par object containing info for current riva board 584 * @regs: pointer to riva_regs object 585 * 586 * DESCRIPTION: 587 * Saves current chip state to @regs. 588 * 589 * CALLED FROM: 590 * rivafb_probe() 591 */ 592/* from GGI */ 593static void riva_save_state(struct riva_par *par, struct riva_regs *regs) 594{ 595 int i; 596 597 NVTRACE_ENTER(); 598 par->riva.LockUnlock(&par->riva, 0); 599 600 par->riva.UnloadStateExt(&par->riva, ®s->ext); 601 602 regs->misc_output = MISCin(par); 603 604 for (i = 0; i < NUM_CRT_REGS; i++) 605 regs->crtc[i] = CRTCin(par, i); 606 607 for (i = 0; i < NUM_ATC_REGS; i++) 608 regs->attr[i] = ATTRin(par, i); 609 610 for (i = 0; i < NUM_GRC_REGS; i++) 611 regs->gra[i] = GRAin(par, i); 612 613 for (i = 0; i < NUM_SEQ_REGS; i++) 614 regs->seq[i] = SEQin(par, i); 615 NVTRACE_LEAVE(); 616} 617 618/** 619 * riva_load_state - loads current chip state 620 * @par: pointer to riva_par object containing info for current riva board 621 * @regs: pointer to riva_regs object 622 * 623 * DESCRIPTION: 624 * Loads chip state from @regs. 625 * 626 * CALLED FROM: 627 * riva_load_video_mode() 628 * rivafb_probe() 629 * rivafb_remove() 630 */ 631/* from GGI */ 632static void riva_load_state(struct riva_par *par, struct riva_regs *regs) 633{ 634 RIVA_HW_STATE *state = ®s->ext; 635 int i; 636 637 NVTRACE_ENTER(); 638 CRTCout(par, 0x11, 0x00); 639 640 par->riva.LockUnlock(&par->riva, 0); 641 642 par->riva.LoadStateExt(&par->riva, state); 643 644 MISCout(par, regs->misc_output); 645 646 for (i = 0; i < NUM_CRT_REGS; i++) { 647 switch (i) { 648 case 0x19: 649 case 0x20 ... 0x40: 650 break; 651 default: 652 CRTCout(par, i, regs->crtc[i]); 653 } 654 } 655 656 for (i = 0; i < NUM_ATC_REGS; i++) 657 ATTRout(par, i, regs->attr[i]); 658 659 for (i = 0; i < NUM_GRC_REGS; i++) 660 GRAout(par, i, regs->gra[i]); 661 662 for (i = 0; i < NUM_SEQ_REGS; i++) 663 SEQout(par, i, regs->seq[i]); 664 NVTRACE_LEAVE(); 665} 666 667/** 668 * riva_load_video_mode - calculate timings 669 * @info: pointer to fb_info object containing info for current riva board 670 * 671 * DESCRIPTION: 672 * Calculate some timings and then send em off to riva_load_state(). 673 * 674 * CALLED FROM: 675 * rivafb_set_par() 676 */ 677static int riva_load_video_mode(struct fb_info *info) 678{ 679 int bpp, width, hDisplaySize, hDisplay, hStart, 680 hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock; 681 int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd; 682 int rc; 683 struct riva_par *par = info->par; 684 struct riva_regs newmode; 685 686 NVTRACE_ENTER(); 687 /* time to calculate */ 688 rivafb_blank(FB_BLANK_NORMAL, info); 689 690 bpp = info->var.bits_per_pixel; 691 if (bpp == 16 && info->var.green.length == 5) 692 bpp = 15; 693 width = info->var.xres_virtual; 694 hDisplaySize = info->var.xres; 695 hDisplay = (hDisplaySize / 8) - 1; 696 hStart = (hDisplaySize + info->var.right_margin) / 8 - 1; 697 hEnd = (hDisplaySize + info->var.right_margin + 698 info->var.hsync_len) / 8 - 1; 699 hTotal = (hDisplaySize + info->var.right_margin + 700 info->var.hsync_len + info->var.left_margin) / 8 - 5; 701 hBlankStart = hDisplay; 702 hBlankEnd = hTotal + 4; 703 704 height = info->var.yres_virtual; 705 vDisplay = info->var.yres - 1; 706 vStart = info->var.yres + info->var.lower_margin - 1; 707 vEnd = info->var.yres + info->var.lower_margin + 708 info->var.vsync_len - 1; 709 vTotal = info->var.yres + info->var.lower_margin + 710 info->var.vsync_len + info->var.upper_margin + 2; 711 vBlankStart = vDisplay; 712 vBlankEnd = vTotal + 1; 713 dotClock = 1000000000 / info->var.pixclock; 714 715 memcpy(&newmode, ®_template, sizeof(struct riva_regs)); 716 717 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) 718 vTotal |= 1; 719 720 if (par->FlatPanel) { 721 vStart = vTotal - 3; 722 vEnd = vTotal - 2; 723 vBlankStart = vStart; 724 hStart = hTotal - 3; 725 hEnd = hTotal - 2; 726 hBlankEnd = hTotal + 4; 727 } 728 729 newmode.crtc[0x0] = Set8Bits (hTotal); 730 newmode.crtc[0x1] = Set8Bits (hDisplay); 731 newmode.crtc[0x2] = Set8Bits (hBlankStart); 732 newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7); 733 newmode.crtc[0x4] = Set8Bits (hStart); 734 newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7) 735 | SetBitField (hEnd, 4: 0, 4:0); 736 newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0); 737 newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0) 738 | SetBitField (vDisplay, 8: 8, 1:1) 739 | SetBitField (vStart, 8: 8, 2:2) 740 | SetBitField (vBlankStart, 8: 8, 3:3) 741 | SetBit (4) 742 | SetBitField (vTotal, 9: 9, 5:5) 743 | SetBitField (vDisplay, 9: 9, 6:6) 744 | SetBitField (vStart, 9: 9, 7:7); 745 newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5) 746 | SetBit (6); 747 newmode.crtc[0x10] = Set8Bits (vStart); 748 newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0) 749 | SetBit (5); 750 newmode.crtc[0x12] = Set8Bits (vDisplay); 751 newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8); 752 newmode.crtc[0x15] = Set8Bits (vBlankStart); 753 newmode.crtc[0x16] = Set8Bits (vBlankEnd); 754 755 newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4) 756 | SetBitField(vBlankStart,10:10,3:3) 757 | SetBitField(vStart,10:10,2:2) 758 | SetBitField(vDisplay,10:10,1:1) 759 | SetBitField(vTotal,10:10,0:0); 760 newmode.ext.horiz = SetBitField(hTotal,8:8,0:0) 761 | SetBitField(hDisplay,8:8,1:1) 762 | SetBitField(hBlankStart,8:8,2:2) 763 | SetBitField(hStart,8:8,3:3); 764 newmode.ext.extra = SetBitField(vTotal,11:11,0:0) 765 | SetBitField(vDisplay,11:11,2:2) 766 | SetBitField(vStart,11:11,4:4) 767 | SetBitField(vBlankStart,11:11,6:6); 768 769 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) { 770 int tmp = (hTotal >> 1) & ~1; 771 newmode.ext.interlace = Set8Bits(tmp); 772 newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4); 773 } else 774 newmode.ext.interlace = 0xff; /* interlace off */ 775 776 if (par->riva.Architecture >= NV_ARCH_10) 777 par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart); 778 779 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) 780 newmode.misc_output &= ~0x40; 781 else 782 newmode.misc_output |= 0x40; 783 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) 784 newmode.misc_output &= ~0x80; 785 else 786 newmode.misc_output |= 0x80; 787 788 rc = CalcStateExt(&par->riva, &newmode.ext, bpp, width, 789 hDisplaySize, height, dotClock); 790 if (rc) 791 goto out; 792 793 newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) & 794 0xfff000ff; 795 if (par->FlatPanel == 1) { 796 newmode.ext.pixel |= (1 << 7); 797 newmode.ext.scale |= (1 << 8); 798 } 799 if (par->SecondCRTC) { 800 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) & 801 ~0x00001000; 802 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) | 803 0x00001000; 804 newmode.ext.crtcOwner = 3; 805 newmode.ext.pllsel |= 0x20000800; 806 newmode.ext.vpll2 = newmode.ext.vpll; 807 } else if (par->riva.twoHeads) { 808 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) | 809 0x00001000; 810 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) & 811 ~0x00001000; 812 newmode.ext.crtcOwner = 0; 813 newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520); 814 } 815 if (par->FlatPanel == 1) { 816 newmode.ext.pixel |= (1 << 7); 817 newmode.ext.scale |= (1 << 8); 818 } 819 newmode.ext.cursorConfig = 0x02000100; 820 par->current_state = newmode; 821 riva_load_state(par, &par->current_state); 822 par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */ 823 824out: 825 rivafb_blank(FB_BLANK_UNBLANK, info); 826 NVTRACE_LEAVE(); 827 828 return rc; 829} 830 831static void riva_update_var(struct fb_var_screeninfo *var, 832 const struct fb_videomode *modedb) 833{ 834 NVTRACE_ENTER(); 835 var->xres = var->xres_virtual = modedb->xres; 836 var->yres = modedb->yres; 837 if (var->yres_virtual < var->yres) 838 var->yres_virtual = var->yres; 839 var->xoffset = var->yoffset = 0; 840 var->pixclock = modedb->pixclock; 841 var->left_margin = modedb->left_margin; 842 var->right_margin = modedb->right_margin; 843 var->upper_margin = modedb->upper_margin; 844 var->lower_margin = modedb->lower_margin; 845 var->hsync_len = modedb->hsync_len; 846 var->vsync_len = modedb->vsync_len; 847 var->sync = modedb->sync; 848 var->vmode = modedb->vmode; 849 NVTRACE_LEAVE(); 850} 851 852/** 853 * rivafb_do_maximize - 854 * @info: pointer to fb_info object containing info for current riva board 855 * @var: 856 * @nom: 857 * @den: 858 * 859 * DESCRIPTION: 860 * . 861 * 862 * RETURNS: 863 * -EINVAL on failure, 0 on success 864 * 865 * 866 * CALLED FROM: 867 * rivafb_check_var() 868 */ 869static int rivafb_do_maximize(struct fb_info *info, 870 struct fb_var_screeninfo *var, 871 int nom, int den) 872{ 873 static struct { 874 int xres, yres; 875 } modes[] = { 876 {1600, 1280}, 877 {1280, 1024}, 878 {1024, 768}, 879 {800, 600}, 880 {640, 480}, 881 {-1, -1} 882 }; 883 int i; 884 885 NVTRACE_ENTER(); 886 /* use highest possible virtual resolution */ 887 if (var->xres_virtual == -1 && var->yres_virtual == -1) { 888 printk(KERN_WARNING PFX 889 "using maximum available virtual resolution\n"); 890 for (i = 0; modes[i].xres != -1; i++) { 891 if (modes[i].xres * nom / den * modes[i].yres < 892 info->fix.smem_len) 893 break; 894 } 895 if (modes[i].xres == -1) { 896 printk(KERN_ERR PFX 897 "could not find a virtual resolution that fits into video memory!!\n"); 898 NVTRACE("EXIT - EINVAL error\n"); 899 return -EINVAL; 900 } 901 var->xres_virtual = modes[i].xres; 902 var->yres_virtual = modes[i].yres; 903 904 printk(KERN_INFO PFX 905 "virtual resolution set to maximum of %dx%d\n", 906 var->xres_virtual, var->yres_virtual); 907 } else if (var->xres_virtual == -1) { 908 var->xres_virtual = (info->fix.smem_len * den / 909 (nom * var->yres_virtual)) & ~15; 910 printk(KERN_WARNING PFX 911 "setting virtual X resolution to %d\n", var->xres_virtual); 912 } else if (var->yres_virtual == -1) { 913 var->xres_virtual = (var->xres_virtual + 15) & ~15; 914 var->yres_virtual = info->fix.smem_len * den / 915 (nom * var->xres_virtual); 916 printk(KERN_WARNING PFX 917 "setting virtual Y resolution to %d\n", var->yres_virtual); 918 } else { 919 var->xres_virtual = (var->xres_virtual + 15) & ~15; 920 if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) { 921 printk(KERN_ERR PFX 922 "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n", 923 var->xres, var->yres, var->bits_per_pixel); 924 NVTRACE("EXIT - EINVAL error\n"); 925 return -EINVAL; 926 } 927 } 928 929 if (var->xres_virtual * nom / den >= 8192) { 930 printk(KERN_WARNING PFX 931 "virtual X resolution (%d) is too high, lowering to %d\n", 932 var->xres_virtual, 8192 * den / nom - 16); 933 var->xres_virtual = 8192 * den / nom - 16; 934 } 935 936 if (var->xres_virtual < var->xres) { 937 printk(KERN_ERR PFX 938 "virtual X resolution (%d) is smaller than real\n", var->xres_virtual); 939 return -EINVAL; 940 } 941 942 if (var->yres_virtual < var->yres) { 943 printk(KERN_ERR PFX 944 "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual); 945 return -EINVAL; 946 } 947 if (var->yres_virtual > 0x7fff/nom) 948 var->yres_virtual = 0x7fff/nom; 949 if (var->xres_virtual > 0x7fff/nom) 950 var->xres_virtual = 0x7fff/nom; 951 NVTRACE_LEAVE(); 952 return 0; 953} 954 955static void 956riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1) 957{ 958 RIVA_FIFO_FREE(par->riva, Patt, 4); 959 NV_WR32(&par->riva.Patt->Color0, 0, clr0); 960 NV_WR32(&par->riva.Patt->Color1, 0, clr1); 961 NV_WR32(par->riva.Patt->Monochrome, 0, pat0); 962 NV_WR32(par->riva.Patt->Monochrome, 4, pat1); 963} 964 965/* acceleration routines */ 966static inline void wait_for_idle(struct riva_par *par) 967{ 968 while (par->riva.Busy(&par->riva)); 969} 970 971/* 972 * Set ROP. Translate X rop into ROP3. Internal routine. 973 */ 974static void 975riva_set_rop_solid(struct riva_par *par, int rop) 976{ 977 riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); 978 RIVA_FIFO_FREE(par->riva, Rop, 1); 979 NV_WR32(&par->riva.Rop->Rop3, 0, rop); 980 981} 982 983static void riva_setup_accel(struct fb_info *info) 984{ 985 struct riva_par *par = info->par; 986 987 RIVA_FIFO_FREE(par->riva, Clip, 2); 988 NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0); 989 NV_WR32(&par->riva.Clip->WidthHeight, 0, 990 (info->var.xres_virtual & 0xffff) | 991 (info->var.yres_virtual << 16)); 992 riva_set_rop_solid(par, 0xcc); 993 wait_for_idle(par); 994} 995 996/** 997 * riva_get_cmap_len - query current color map length 998 * @var: standard kernel fb changeable data 999 * 1000 * DESCRIPTION: 1001 * Get current color map length. 1002 * 1003 * RETURNS: 1004 * Length of color map 1005 * 1006 * CALLED FROM: 1007 * rivafb_setcolreg() 1008 */ 1009static int riva_get_cmap_len(const struct fb_var_screeninfo *var) 1010{ 1011 int rc = 256; /* reasonable default */ 1012 1013 switch (var->green.length) { 1014 case 8: 1015 rc = 256; /* 256 entries (2^8), 8 bpp and RGB8888 */ 1016 break; 1017 case 5: 1018 rc = 32; /* 32 entries (2^5), 16 bpp, RGB555 */ 1019 break; 1020 case 6: 1021 rc = 64; /* 64 entries (2^6), 16 bpp, RGB565 */ 1022 break; 1023 default: 1024 /* should not occur */ 1025 break; 1026 } 1027 return rc; 1028} 1029 1030/* ------------------------------------------------------------------------- * 1031 * 1032 * framebuffer operations 1033 * 1034 * ------------------------------------------------------------------------- */ 1035 1036static int rivafb_open(struct fb_info *info, int user) 1037{ 1038 struct riva_par *par = info->par; 1039 1040 NVTRACE_ENTER(); 1041 mutex_lock(&par->open_lock); 1042 if (!par->ref_count) { 1043#ifdef CONFIG_X86 1044 memset(&par->state, 0, sizeof(struct vgastate)); 1045 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS; 1046 /* save the DAC for Riva128 */ 1047 if (par->riva.Architecture == NV_ARCH_03) 1048 par->state.flags |= VGA_SAVE_CMAP; 1049 save_vga(&par->state); 1050#endif 1051 /* vgaHWunlock() + riva unlock (0x7F) */ 1052 CRTCout(par, 0x11, 0xFF); 1053 par->riva.LockUnlock(&par->riva, 0); 1054 1055 riva_save_state(par, &par->initial_state); 1056 } 1057 par->ref_count++; 1058 mutex_unlock(&par->open_lock); 1059 NVTRACE_LEAVE(); 1060 return 0; 1061} 1062 1063static int rivafb_release(struct fb_info *info, int user) 1064{ 1065 struct riva_par *par = info->par; 1066 1067 NVTRACE_ENTER(); 1068 mutex_lock(&par->open_lock); 1069 if (!par->ref_count) { 1070 mutex_unlock(&par->open_lock); 1071 return -EINVAL; 1072 } 1073 if (par->ref_count == 1) { 1074 par->riva.LockUnlock(&par->riva, 0); 1075 par->riva.LoadStateExt(&par->riva, &par->initial_state.ext); 1076 riva_load_state(par, &par->initial_state); 1077#ifdef CONFIG_X86 1078 restore_vga(&par->state); 1079#endif 1080 par->riva.LockUnlock(&par->riva, 1); 1081 } 1082 par->ref_count--; 1083 mutex_unlock(&par->open_lock); 1084 NVTRACE_LEAVE(); 1085 return 0; 1086} 1087 1088static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 1089{ 1090 const struct fb_videomode *mode; 1091 struct riva_par *par = info->par; 1092 int nom, den; /* translating from pixels->bytes */ 1093 int mode_valid = 0; 1094 1095 NVTRACE_ENTER(); 1096 switch (var->bits_per_pixel) { 1097 case 1 ... 8: 1098 var->red.offset = var->green.offset = var->blue.offset = 0; 1099 var->red.length = var->green.length = var->blue.length = 8; 1100 var->bits_per_pixel = 8; 1101 nom = den = 1; 1102 break; 1103 case 9 ... 15: 1104 var->green.length = 5; 1105 /* fall through */ 1106 case 16: 1107 var->bits_per_pixel = 16; 1108 /* The Riva128 supports RGB555 only */ 1109 if (par->riva.Architecture == NV_ARCH_03) 1110 var->green.length = 5; 1111 if (var->green.length == 5) { 1112 /* 0rrrrrgg gggbbbbb */ 1113 var->red.offset = 10; 1114 var->green.offset = 5; 1115 var->blue.offset = 0; 1116 var->red.length = 5; 1117 var->green.length = 5; 1118 var->blue.length = 5; 1119 } else { 1120 /* rrrrrggg gggbbbbb */ 1121 var->red.offset = 11; 1122 var->green.offset = 5; 1123 var->blue.offset = 0; 1124 var->red.length = 5; 1125 var->green.length = 6; 1126 var->blue.length = 5; 1127 } 1128 nom = 2; 1129 den = 1; 1130 break; 1131 case 17 ... 32: 1132 var->red.length = var->green.length = var->blue.length = 8; 1133 var->bits_per_pixel = 32; 1134 var->red.offset = 16; 1135 var->green.offset = 8; 1136 var->blue.offset = 0; 1137 nom = 4; 1138 den = 1; 1139 break; 1140 default: 1141 printk(KERN_ERR PFX 1142 "mode %dx%dx%d rejected...color depth not supported.\n", 1143 var->xres, var->yres, var->bits_per_pixel); 1144 NVTRACE("EXIT, returning -EINVAL\n"); 1145 return -EINVAL; 1146 } 1147 1148 if (!strictmode) { 1149 if (!info->monspecs.vfmax || !info->monspecs.hfmax || 1150 !info->monspecs.dclkmax || !fb_validate_mode(var, info)) 1151 mode_valid = 1; 1152 } 1153 1154 /* calculate modeline if supported by monitor */ 1155 if (!mode_valid && info->monspecs.gtf) { 1156 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info)) 1157 mode_valid = 1; 1158 } 1159 1160 if (!mode_valid) { 1161 mode = fb_find_best_mode(var, &info->modelist); 1162 if (mode) { 1163 riva_update_var(var, mode); 1164 mode_valid = 1; 1165 } 1166 } 1167 1168 if (!mode_valid && info->monspecs.modedb_len) 1169 return -EINVAL; 1170 1171 if (var->xres_virtual < var->xres) 1172 var->xres_virtual = var->xres; 1173 if (var->yres_virtual <= var->yres) 1174 var->yres_virtual = -1; 1175 if (rivafb_do_maximize(info, var, nom, den) < 0) 1176 return -EINVAL; 1177 1178 /* truncate xoffset and yoffset to maximum if too high */ 1179 if (var->xoffset > var->xres_virtual - var->xres) 1180 var->xoffset = var->xres_virtual - var->xres - 1; 1181 1182 if (var->yoffset > var->yres_virtual - var->yres) 1183 var->yoffset = var->yres_virtual - var->yres - 1; 1184 1185 var->red.msb_right = 1186 var->green.msb_right = 1187 var->blue.msb_right = 1188 var->transp.offset = var->transp.length = var->transp.msb_right = 0; 1189 NVTRACE_LEAVE(); 1190 return 0; 1191} 1192 1193static int rivafb_set_par(struct fb_info *info) 1194{ 1195 struct riva_par *par = info->par; 1196 int rc = 0; 1197 1198 NVTRACE_ENTER(); 1199 /* vgaHWunlock() + riva unlock (0x7F) */ 1200 CRTCout(par, 0x11, 0xFF); 1201 par->riva.LockUnlock(&par->riva, 0); 1202 rc = riva_load_video_mode(info); 1203 if (rc) 1204 goto out; 1205 if(!(info->flags & FBINFO_HWACCEL_DISABLED)) 1206 riva_setup_accel(info); 1207 1208 par->cursor_reset = 1; 1209 info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3)); 1210 info->fix.visual = (info->var.bits_per_pixel == 8) ? 1211 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; 1212 1213 if (info->flags & FBINFO_HWACCEL_DISABLED) 1214 info->pixmap.scan_align = 1; 1215 else 1216 info->pixmap.scan_align = 4; 1217 1218out: 1219 NVTRACE_LEAVE(); 1220 return rc; 1221} 1222 1223/** 1224 * rivafb_pan_display 1225 * @var: standard kernel fb changeable data 1226 * @con: TODO 1227 * @info: pointer to fb_info object containing info for current riva board 1228 * 1229 * DESCRIPTION: 1230 * Pan (or wrap, depending on the `vmode' field) the display using the 1231 * `xoffset' and `yoffset' fields of the `var' structure. 1232 * If the values don't fit, return -EINVAL. 1233 * 1234 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag 1235 */ 1236static int rivafb_pan_display(struct fb_var_screeninfo *var, 1237 struct fb_info *info) 1238{ 1239 struct riva_par *par = info->par; 1240 unsigned int base; 1241 1242 NVTRACE_ENTER(); 1243 base = var->yoffset * info->fix.line_length + var->xoffset; 1244 par->riva.SetStartAddress(&par->riva, base); 1245 NVTRACE_LEAVE(); 1246 return 0; 1247} 1248 1249static int rivafb_blank(int blank, struct fb_info *info) 1250{ 1251 struct riva_par *par= info->par; 1252 unsigned char tmp, vesa; 1253 1254 tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */ 1255 vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */ 1256 1257 NVTRACE_ENTER(); 1258 1259 if (blank) 1260 tmp |= 0x20; 1261 1262 switch (blank) { 1263 case FB_BLANK_UNBLANK: 1264 case FB_BLANK_NORMAL: 1265 break; 1266 case FB_BLANK_VSYNC_SUSPEND: 1267 vesa |= 0x80; 1268 break; 1269 case FB_BLANK_HSYNC_SUSPEND: 1270 vesa |= 0x40; 1271 break; 1272 case FB_BLANK_POWERDOWN: 1273 vesa |= 0xc0; 1274 break; 1275 } 1276 1277 SEQout(par, 0x01, tmp); 1278 CRTCout(par, 0x1a, vesa); 1279 1280 NVTRACE_LEAVE(); 1281 1282 return 0; 1283} 1284 1285/** 1286 * rivafb_setcolreg 1287 * @regno: register index 1288 * @red: red component 1289 * @green: green component 1290 * @blue: blue component 1291 * @transp: transparency 1292 * @info: pointer to fb_info object containing info for current riva board 1293 * 1294 * DESCRIPTION: 1295 * Set a single color register. The values supplied have a 16 bit 1296 * magnitude. 1297 * 1298 * RETURNS: 1299 * Return != 0 for invalid regno. 1300 * 1301 * CALLED FROM: 1302 * fbcmap.c:fb_set_cmap() 1303 */ 1304static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green, 1305 unsigned blue, unsigned transp, 1306 struct fb_info *info) 1307{ 1308 struct riva_par *par = info->par; 1309 RIVA_HW_INST *chip = &par->riva; 1310 int i; 1311 1312 if (regno >= riva_get_cmap_len(&info->var)) 1313 return -EINVAL; 1314 1315 if (info->var.grayscale) { 1316 /* gray = 0.30*R + 0.59*G + 0.11*B */ 1317 red = green = blue = 1318 (red * 77 + green * 151 + blue * 28) >> 8; 1319 } 1320 1321 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) { 1322 ((u32 *) info->pseudo_palette)[regno] = 1323 (regno << info->var.red.offset) | 1324 (regno << info->var.green.offset) | 1325 (regno << info->var.blue.offset); 1326 /* 1327 * The Riva128 2D engine requires color information in 1328 * TrueColor format even if framebuffer is in DirectColor 1329 */ 1330 if (par->riva.Architecture == NV_ARCH_03) { 1331 switch (info->var.bits_per_pixel) { 1332 case 16: 1333 par->palette[regno] = ((red & 0xf800) >> 1) | 1334 ((green & 0xf800) >> 6) | 1335 ((blue & 0xf800) >> 11); 1336 break; 1337 case 32: 1338 par->palette[regno] = ((red & 0xff00) << 8) | 1339 ((green & 0xff00)) | 1340 ((blue & 0xff00) >> 8); 1341 break; 1342 } 1343 } 1344 } 1345 1346 switch (info->var.bits_per_pixel) { 1347 case 8: 1348 /* "transparent" stuff is completely ignored. */ 1349 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8); 1350 break; 1351 case 16: 1352 if (info->var.green.length == 5) { 1353 for (i = 0; i < 8; i++) { 1354 riva_wclut(chip, regno*8+i, red >> 8, 1355 green >> 8, blue >> 8); 1356 } 1357 } else { 1358 u8 r, g, b; 1359 1360 if (regno < 32) { 1361 for (i = 0; i < 8; i++) { 1362 riva_wclut(chip, regno*8+i, 1363 red >> 8, green >> 8, 1364 blue >> 8); 1365 } 1366 } 1367 riva_rclut(chip, regno*4, &r, &g, &b); 1368 for (i = 0; i < 4; i++) 1369 riva_wclut(chip, regno*4+i, r, 1370 green >> 8, b); 1371 } 1372 break; 1373 case 32: 1374 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8); 1375 break; 1376 default: 1377 /* do nothing */ 1378 break; 1379 } 1380 return 0; 1381} 1382 1383/** 1384 * rivafb_fillrect - hardware accelerated color fill function 1385 * @info: pointer to fb_info structure 1386 * @rect: pointer to fb_fillrect structure 1387 * 1388 * DESCRIPTION: 1389 * This function fills up a region of framebuffer memory with a solid 1390 * color with a choice of two different ROP's, copy or invert. 1391 * 1392 * CALLED FROM: 1393 * framebuffer hook 1394 */ 1395static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 1396{ 1397 struct riva_par *par = info->par; 1398 u_int color, rop = 0; 1399 1400 if ((info->flags & FBINFO_HWACCEL_DISABLED)) { 1401 cfb_fillrect(info, rect); 1402 return; 1403 } 1404 1405 if (info->var.bits_per_pixel == 8) 1406 color = rect->color; 1407 else { 1408 if (par->riva.Architecture != NV_ARCH_03) 1409 color = ((u32 *)info->pseudo_palette)[rect->color]; 1410 else 1411 color = par->palette[rect->color]; 1412 } 1413 1414 switch (rect->rop) { 1415 case ROP_XOR: 1416 rop = 0x66; 1417 break; 1418 case ROP_COPY: 1419 default: 1420 rop = 0xCC; 1421 break; 1422 } 1423 1424 riva_set_rop_solid(par, rop); 1425 1426 RIVA_FIFO_FREE(par->riva, Bitmap, 1); 1427 NV_WR32(&par->riva.Bitmap->Color1A, 0, color); 1428 1429 RIVA_FIFO_FREE(par->riva, Bitmap, 2); 1430 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0, 1431 (rect->dx << 16) | rect->dy); 1432 mb(); 1433 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0, 1434 (rect->width << 16) | rect->height); 1435 mb(); 1436 riva_set_rop_solid(par, 0xcc); 1437 1438} 1439 1440/** 1441 * rivafb_copyarea - hardware accelerated blit function 1442 * @info: pointer to fb_info structure 1443 * @region: pointer to fb_copyarea structure 1444 * 1445 * DESCRIPTION: 1446 * This copies an area of pixels from one location to another 1447 * 1448 * CALLED FROM: 1449 * framebuffer hook 1450 */ 1451static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region) 1452{ 1453 struct riva_par *par = info->par; 1454 1455 if ((info->flags & FBINFO_HWACCEL_DISABLED)) { 1456 cfb_copyarea(info, region); 1457 return; 1458 } 1459 1460 RIVA_FIFO_FREE(par->riva, Blt, 3); 1461 NV_WR32(&par->riva.Blt->TopLeftSrc, 0, 1462 (region->sy << 16) | region->sx); 1463 NV_WR32(&par->riva.Blt->TopLeftDst, 0, 1464 (region->dy << 16) | region->dx); 1465 mb(); 1466 NV_WR32(&par->riva.Blt->WidthHeight, 0, 1467 (region->height << 16) | region->width); 1468 mb(); 1469} 1470 1471static inline void convert_bgcolor_16(u32 *col) 1472{ 1473 *col = ((*col & 0x0000F800) << 8) 1474 | ((*col & 0x00007E0) << 5) 1475 | ((*col & 0x0000001F) << 3) 1476 | 0xFF000000; 1477 mb(); 1478} 1479 1480/** 1481 * rivafb_imageblit: hardware accelerated color expand function 1482 * @info: pointer to fb_info structure 1483 * @image: pointer to fb_image structure 1484 * 1485 * DESCRIPTION: 1486 * If the source is a monochrome bitmap, the function fills up a a region 1487 * of framebuffer memory with pixels whose color is determined by the bit 1488 * setting of the bitmap, 1 - foreground, 0 - background. 1489 * 1490 * If the source is not a monochrome bitmap, color expansion is not done. 1491 * In this case, it is channeled to a software function. 1492 * 1493 * CALLED FROM: 1494 * framebuffer hook 1495 */ 1496static void rivafb_imageblit(struct fb_info *info, 1497 const struct fb_image *image) 1498{ 1499 struct riva_par *par = info->par; 1500 u32 fgx = 0, bgx = 0, width, tmp; 1501 u8 *cdat = (u8 *) image->data; 1502 volatile u32 __iomem *d; 1503 int i, size; 1504 1505 if ((info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1) { 1506 cfb_imageblit(info, image); 1507 return; 1508 } 1509 1510 switch (info->var.bits_per_pixel) { 1511 case 8: 1512 fgx = image->fg_color; 1513 bgx = image->bg_color; 1514 break; 1515 case 16: 1516 case 32: 1517 if (par->riva.Architecture != NV_ARCH_03) { 1518 fgx = ((u32 *)info->pseudo_palette)[image->fg_color]; 1519 bgx = ((u32 *)info->pseudo_palette)[image->bg_color]; 1520 } else { 1521 fgx = par->palette[image->fg_color]; 1522 bgx = par->palette[image->bg_color]; 1523 } 1524 if (info->var.green.length == 6) 1525 convert_bgcolor_16(&bgx); 1526 break; 1527 } 1528 1529 RIVA_FIFO_FREE(par->riva, Bitmap, 7); 1530 NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0, 1531 (image->dy << 16) | (image->dx & 0xFFFF)); 1532 NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0, 1533 (((image->dy + image->height) << 16) | 1534 ((image->dx + image->width) & 0xffff))); 1535 NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx); 1536 NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx); 1537 NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0, 1538 (image->height << 16) | ((image->width + 31) & ~31)); 1539 NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0, 1540 (image->height << 16) | ((image->width + 31) & ~31)); 1541 NV_WR32(&par->riva.Bitmap->PointE, 0, 1542 (image->dy << 16) | (image->dx & 0xFFFF)); 1543 1544 d = &par->riva.Bitmap->MonochromeData01E; 1545 1546 width = (image->width + 31)/32; 1547 size = width * image->height; 1548 while (size >= 16) { 1549 RIVA_FIFO_FREE(par->riva, Bitmap, 16); 1550 for (i = 0; i < 16; i++) { 1551 tmp = *((u32 *)cdat); 1552 cdat = (u8 *)((u32 *)cdat + 1); 1553 reverse_order(&tmp); 1554 NV_WR32(d, i*4, tmp); 1555 } 1556 size -= 16; 1557 } 1558 if (size) { 1559 RIVA_FIFO_FREE(par->riva, Bitmap, size); 1560 for (i = 0; i < size; i++) { 1561 tmp = *((u32 *) cdat); 1562 cdat = (u8 *)((u32 *)cdat + 1); 1563 reverse_order(&tmp); 1564 NV_WR32(d, i*4, tmp); 1565 } 1566 } 1567} 1568 1569/** 1570 * rivafb_cursor - hardware cursor function 1571 * @info: pointer to info structure 1572 * @cursor: pointer to fbcursor structure 1573 * 1574 * DESCRIPTION: 1575 * A cursor function that supports displaying a cursor image via hardware. 1576 * Within the kernel, copy and invert rops are supported. If exported 1577 * to user space, only the copy rop will be supported. 1578 * 1579 * CALLED FROM 1580 * framebuffer hook 1581 */ 1582static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor) 1583{ 1584 struct riva_par *par = info->par; 1585 u8 data[MAX_CURS * MAX_CURS/8]; 1586 int i, set = cursor->set; 1587 u16 fg, bg; 1588 1589 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS) 1590 return -ENXIO; 1591 1592 par->riva.ShowHideCursor(&par->riva, 0); 1593 1594 if (par->cursor_reset) { 1595 set = FB_CUR_SETALL; 1596 par->cursor_reset = 0; 1597 } 1598 1599 if (set & FB_CUR_SETSIZE) 1600 memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2); 1601 1602 if (set & FB_CUR_SETPOS) { 1603 u32 xx, yy, temp; 1604 1605 yy = cursor->image.dy - info->var.yoffset; 1606 xx = cursor->image.dx - info->var.xoffset; 1607 temp = xx & 0xFFFF; 1608 temp |= yy << 16; 1609 1610 NV_WR32(par->riva.PRAMDAC, 0x0000300, temp); 1611 } 1612 1613 1614 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) { 1615 u32 bg_idx = cursor->image.bg_color; 1616 u32 fg_idx = cursor->image.fg_color; 1617 u32 s_pitch = (cursor->image.width+7) >> 3; 1618 u32 d_pitch = MAX_CURS/8; 1619 u8 *dat = (u8 *) cursor->image.data; 1620 u8 *msk = (u8 *) cursor->mask; 1621 u8 *src; 1622 1623 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC); 1624 1625 if (src) { 1626 switch (cursor->rop) { 1627 case ROP_XOR: 1628 for (i = 0; i < s_pitch * cursor->image.height; i++) 1629 src[i] = dat[i] ^ msk[i]; 1630 break; 1631 case ROP_COPY: 1632 default: 1633 for (i = 0; i < s_pitch * cursor->image.height; i++) 1634 src[i] = dat[i] & msk[i]; 1635 break; 1636 } 1637 1638 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch, 1639 cursor->image.height); 1640 1641 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) | 1642 ((info->cmap.green[bg_idx] & 0xf8) << 2) | 1643 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1644 1 << 15; 1645 1646 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) | 1647 ((info->cmap.green[fg_idx] & 0xf8) << 2) | 1648 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1649 1 << 15; 1650 1651 par->riva.LockUnlock(&par->riva, 0); 1652 1653 rivafb_load_cursor_image(par, data, bg, fg, 1654 cursor->image.width, 1655 cursor->image.height); 1656 kfree(src); 1657 } 1658 } 1659 1660 if (cursor->enable) 1661 par->riva.ShowHideCursor(&par->riva, 1); 1662 1663 return 0; 1664} 1665 1666static int rivafb_sync(struct fb_info *info) 1667{ 1668 struct riva_par *par = info->par; 1669 1670 wait_for_idle(par); 1671 return 0; 1672} 1673 1674/* ------------------------------------------------------------------------- * 1675 * 1676 * initialization helper functions 1677 * 1678 * ------------------------------------------------------------------------- */ 1679 1680/* kernel interface */ 1681static struct fb_ops riva_fb_ops = { 1682 .owner = THIS_MODULE, 1683 .fb_open = rivafb_open, 1684 .fb_release = rivafb_release, 1685 .fb_check_var = rivafb_check_var, 1686 .fb_set_par = rivafb_set_par, 1687 .fb_setcolreg = rivafb_setcolreg, 1688 .fb_pan_display = rivafb_pan_display, 1689 .fb_blank = rivafb_blank, 1690 .fb_fillrect = rivafb_fillrect, 1691 .fb_copyarea = rivafb_copyarea, 1692 .fb_imageblit = rivafb_imageblit, 1693 .fb_cursor = rivafb_cursor, 1694 .fb_sync = rivafb_sync, 1695}; 1696 1697static int riva_set_fbinfo(struct fb_info *info) 1698{ 1699 unsigned int cmap_len; 1700 struct riva_par *par = info->par; 1701 1702 NVTRACE_ENTER(); 1703 info->flags = FBINFO_DEFAULT 1704 | FBINFO_HWACCEL_XPAN 1705 | FBINFO_HWACCEL_YPAN 1706 | FBINFO_HWACCEL_COPYAREA 1707 | FBINFO_HWACCEL_FILLRECT 1708 | FBINFO_HWACCEL_IMAGEBLIT; 1709 1710 /* Accel seems to not work properly on NV30 yet...*/ 1711 if ((par->riva.Architecture == NV_ARCH_30) || noaccel) { 1712 printk(KERN_DEBUG PFX "disabling acceleration\n"); 1713 info->flags |= FBINFO_HWACCEL_DISABLED; 1714 } 1715 1716 info->var = rivafb_default_var; 1717 info->fix.visual = (info->var.bits_per_pixel == 8) ? 1718 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; 1719 1720 info->pseudo_palette = par->pseudo_palette; 1721 1722 cmap_len = riva_get_cmap_len(&info->var); 1723 fb_alloc_cmap(&info->cmap, cmap_len, 0); 1724 1725 info->pixmap.size = 8 * 1024; 1726 info->pixmap.buf_align = 4; 1727 info->pixmap.access_align = 32; 1728 info->pixmap.flags = FB_PIXMAP_SYSTEM; 1729 info->var.yres_virtual = -1; 1730 NVTRACE_LEAVE(); 1731 return (rivafb_check_var(&info->var, info)); 1732} 1733 1734static int riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd) 1735{ 1736 struct riva_par *par = info->par; 1737 struct device_node *dp; 1738 const unsigned char *pedid = NULL; 1739 const unsigned char *disptype = NULL; 1740 static char *propnames[] = { 1741 "DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL }; 1742 int i; 1743 1744 NVTRACE_ENTER(); 1745 dp = pci_device_to_OF_node(pd); 1746 for (; dp != NULL; dp = dp->child) { 1747 disptype = of_get_property(dp, "display-type", NULL); 1748 if (disptype == NULL) 1749 continue; 1750 if (strncmp(disptype, "LCD", 3) != 0) 1751 continue; 1752 for (i = 0; propnames[i] != NULL; ++i) { 1753 pedid = of_get_property(dp, propnames[i], NULL); 1754 if (pedid != NULL) { 1755 par->EDID = (unsigned char *)pedid; 1756 NVTRACE("LCD found.\n"); 1757 return 1; 1758 } 1759 } 1760 } 1761 NVTRACE_LEAVE(); 1762 return 0; 1763} 1764 1765#if defined(CONFIG_FB_RIVA_I2C) 1766static int riva_get_EDID_i2c(struct fb_info *info) 1767{ 1768 struct riva_par *par = info->par; 1769 struct fb_var_screeninfo var; 1770 int i; 1771 1772 NVTRACE_ENTER(); 1773 riva_create_i2c_busses(par); 1774 for (i = 0; i < 3; i++) { 1775 if (!par->chan[i].par) 1776 continue; 1777 riva_probe_i2c_connector(par, i, &par->EDID); 1778 if (par->EDID && !fb_parse_edid(par->EDID, &var)) { 1779 printk(PFX "Found EDID Block from BUS %i\n", i); 1780 break; 1781 } 1782 } 1783 1784 NVTRACE_LEAVE(); 1785 return (par->EDID) ? 1 : 0; 1786} 1787#endif /* CONFIG_FB_RIVA_I2C */ 1788 1789static void riva_update_default_var(struct fb_var_screeninfo *var, 1790 struct fb_info *info) 1791{ 1792 struct fb_monspecs *specs = &info->monspecs; 1793 struct fb_videomode modedb; 1794 1795 NVTRACE_ENTER(); 1796 /* respect mode options */ 1797 if (mode_option) { 1798 fb_find_mode(var, info, mode_option, 1799 specs->modedb, specs->modedb_len, 1800 NULL, 8); 1801 } else if (specs->modedb != NULL) { 1802 /* get first mode in database as fallback */ 1803 modedb = specs->modedb[0]; 1804 /* get preferred timing */ 1805 if (info->monspecs.misc & FB_MISC_1ST_DETAIL) { 1806 int i; 1807 1808 for (i = 0; i < specs->modedb_len; i++) { 1809 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) { 1810 modedb = specs->modedb[i]; 1811 break; 1812 } 1813 } 1814 } 1815 var->bits_per_pixel = 8; 1816 riva_update_var(var, &modedb); 1817 } 1818 NVTRACE_LEAVE(); 1819} 1820 1821 1822static void riva_get_EDID(struct fb_info *info, struct pci_dev *pdev) 1823{ 1824 NVTRACE_ENTER(); 1825 if (riva_get_EDID_OF(info, pdev)) { 1826 NVTRACE_LEAVE(); 1827 return; 1828 } 1829 if (IS_ENABLED(CONFIG_OF)) 1830 printk(PFX "could not retrieve EDID from OF\n"); 1831#if defined(CONFIG_FB_RIVA_I2C) 1832 if (!riva_get_EDID_i2c(info)) 1833 printk(PFX "could not retrieve EDID from DDC/I2C\n"); 1834#endif 1835 NVTRACE_LEAVE(); 1836} 1837 1838 1839static void riva_get_edidinfo(struct fb_info *info) 1840{ 1841 struct fb_var_screeninfo *var = &rivafb_default_var; 1842 struct riva_par *par = info->par; 1843 1844 fb_edid_to_monspecs(par->EDID, &info->monspecs); 1845 fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len, 1846 &info->modelist); 1847 riva_update_default_var(var, info); 1848 1849 /* if user specified flatpanel, we respect that */ 1850 if (info->monspecs.input & FB_DISP_DDI) 1851 par->FlatPanel = 1; 1852} 1853 1854/* ------------------------------------------------------------------------- * 1855 * 1856 * PCI bus 1857 * 1858 * ------------------------------------------------------------------------- */ 1859 1860static u32 riva_get_arch(struct pci_dev *pd) 1861{ 1862 u32 arch = 0; 1863 1864 switch (pd->device & 0x0ff0) { 1865 case 0x0100: /* GeForce 256 */ 1866 case 0x0110: /* GeForce2 MX */ 1867 case 0x0150: /* GeForce2 */ 1868 case 0x0170: /* GeForce4 MX */ 1869 case 0x0180: /* GeForce4 MX (8x AGP) */ 1870 case 0x01A0: /* nForce */ 1871 case 0x01F0: /* nForce2 */ 1872 arch = NV_ARCH_10; 1873 break; 1874 case 0x0200: /* GeForce3 */ 1875 case 0x0250: /* GeForce4 Ti */ 1876 case 0x0280: /* GeForce4 Ti (8x AGP) */ 1877 arch = NV_ARCH_20; 1878 break; 1879 case 0x0300: /* GeForceFX 5800 */ 1880 case 0x0310: /* GeForceFX 5600 */ 1881 case 0x0320: /* GeForceFX 5200 */ 1882 case 0x0330: /* GeForceFX 5900 */ 1883 case 0x0340: /* GeForceFX 5700 */ 1884 arch = NV_ARCH_30; 1885 break; 1886 case 0x0020: /* TNT, TNT2 */ 1887 arch = NV_ARCH_04; 1888 break; 1889 case 0x0010: /* Riva128 */ 1890 arch = NV_ARCH_03; 1891 break; 1892 default: /* unknown architecture */ 1893 break; 1894 } 1895 return arch; 1896} 1897 1898static int rivafb_probe(struct pci_dev *pd, const struct pci_device_id *ent) 1899{ 1900 struct riva_par *default_par; 1901 struct fb_info *info; 1902 int ret; 1903 1904 NVTRACE_ENTER(); 1905 assert(pd != NULL); 1906 1907 info = framebuffer_alloc(sizeof(struct riva_par), &pd->dev); 1908 if (!info) { 1909 printk (KERN_ERR PFX "could not allocate memory\n"); 1910 ret = -ENOMEM; 1911 goto err_ret; 1912 } 1913 default_par = info->par; 1914 default_par->pdev = pd; 1915 1916 info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL); 1917 if (info->pixmap.addr == NULL) { 1918 ret = -ENOMEM; 1919 goto err_framebuffer_release; 1920 } 1921 1922 ret = pci_enable_device(pd); 1923 if (ret < 0) { 1924 printk(KERN_ERR PFX "cannot enable PCI device\n"); 1925 goto err_free_pixmap; 1926 } 1927 1928 ret = pci_request_regions(pd, "rivafb"); 1929 if (ret < 0) { 1930 printk(KERN_ERR PFX "cannot request PCI regions\n"); 1931 goto err_disable_device; 1932 } 1933 1934 mutex_init(&default_par->open_lock); 1935 default_par->riva.Architecture = riva_get_arch(pd); 1936 1937 default_par->Chipset = (pd->vendor << 16) | pd->device; 1938 printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset); 1939 1940 if(default_par->riva.Architecture == 0) { 1941 printk(KERN_ERR PFX "unknown NV_ARCH\n"); 1942 ret=-ENODEV; 1943 goto err_release_region; 1944 } 1945 if(default_par->riva.Architecture == NV_ARCH_10 || 1946 default_par->riva.Architecture == NV_ARCH_20 || 1947 default_par->riva.Architecture == NV_ARCH_30) { 1948 sprintf(rivafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4); 1949 } else { 1950 sprintf(rivafb_fix.id, "NV%x", default_par->riva.Architecture); 1951 } 1952 1953 default_par->FlatPanel = flatpanel; 1954 if (flatpanel == 1) 1955 printk(KERN_INFO PFX "flatpanel support enabled\n"); 1956 default_par->forceCRTC = forceCRTC; 1957 1958 rivafb_fix.mmio_len = pci_resource_len(pd, 0); 1959 rivafb_fix.smem_len = pci_resource_len(pd, 1); 1960 1961 { 1962 /* enable IO and mem if not already done */ 1963 unsigned short cmd; 1964 1965 pci_read_config_word(pd, PCI_COMMAND, &cmd); 1966 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY); 1967 pci_write_config_word(pd, PCI_COMMAND, cmd); 1968 } 1969 1970 rivafb_fix.mmio_start = pci_resource_start(pd, 0); 1971 rivafb_fix.smem_start = pci_resource_start(pd, 1); 1972 1973 default_par->ctrl_base = ioremap(rivafb_fix.mmio_start, 1974 rivafb_fix.mmio_len); 1975 if (!default_par->ctrl_base) { 1976 printk(KERN_ERR PFX "cannot ioremap MMIO base\n"); 1977 ret = -EIO; 1978 goto err_release_region; 1979 } 1980 1981 switch (default_par->riva.Architecture) { 1982 case NV_ARCH_03: 1983 /* Riva128's PRAMIN is in the "framebuffer" space 1984 * Since these cards were never made with more than 8 megabytes 1985 * we can safely allocate this separately. 1986 */ 1987 default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000); 1988 if (!default_par->riva.PRAMIN) { 1989 printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n"); 1990 ret = -EIO; 1991 goto err_iounmap_ctrl_base; 1992 } 1993 break; 1994 case NV_ARCH_04: 1995 case NV_ARCH_10: 1996 case NV_ARCH_20: 1997 case NV_ARCH_30: 1998 default_par->riva.PCRTC0 = 1999 (u32 __iomem *)(default_par->ctrl_base + 0x00600000); 2000 default_par->riva.PRAMIN = 2001 (u32 __iomem *)(default_par->ctrl_base + 0x00710000); 2002 break; 2003 } 2004 riva_common_setup(default_par); 2005 2006 if (default_par->riva.Architecture == NV_ARCH_03) { 2007 default_par->riva.PCRTC = default_par->riva.PCRTC0 2008 = default_par->riva.PGRAPH; 2009 } 2010 2011 rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024; 2012 default_par->dclk_max = riva_get_maxdclk(default_par) * 1000; 2013 info->screen_base = ioremap(rivafb_fix.smem_start, 2014 rivafb_fix.smem_len); 2015 if (!info->screen_base) { 2016 printk(KERN_ERR PFX "cannot ioremap FB base\n"); 2017 ret = -EIO; 2018 goto err_iounmap_pramin; 2019 } 2020 2021#ifdef CONFIG_MTRR 2022 if (!nomtrr) { 2023 default_par->mtrr.vram = mtrr_add(rivafb_fix.smem_start, 2024 rivafb_fix.smem_len, 2025 MTRR_TYPE_WRCOMB, 1); 2026 if (default_par->mtrr.vram < 0) { 2027 printk(KERN_ERR PFX "unable to setup MTRR\n"); 2028 } else { 2029 default_par->mtrr.vram_valid = 1; 2030 /* let there be speed */ 2031 printk(KERN_INFO PFX "RIVA MTRR set to ON\n"); 2032 } 2033 } 2034#endif /* CONFIG_MTRR */ 2035 2036 info->fbops = &riva_fb_ops; 2037 info->fix = rivafb_fix; 2038 riva_get_EDID(info, pd); 2039 riva_get_edidinfo(info); 2040 2041 ret=riva_set_fbinfo(info); 2042 if (ret < 0) { 2043 printk(KERN_ERR PFX "error setting initial video mode\n"); 2044 goto err_iounmap_screen_base; 2045 } 2046 2047 fb_destroy_modedb(info->monspecs.modedb); 2048 info->monspecs.modedb = NULL; 2049 2050 pci_set_drvdata(pd, info); 2051 2052 if (backlight) 2053 riva_bl_init(info->par); 2054 2055 ret = register_framebuffer(info); 2056 if (ret < 0) { 2057 printk(KERN_ERR PFX 2058 "error registering riva framebuffer\n"); 2059 goto err_iounmap_screen_base; 2060 } 2061 2062 printk(KERN_INFO PFX 2063 "PCI nVidia %s framebuffer ver %s (%dMB @ 0x%lX)\n", 2064 info->fix.id, 2065 RIVAFB_VERSION, 2066 info->fix.smem_len / (1024 * 1024), 2067 info->fix.smem_start); 2068 2069 NVTRACE_LEAVE(); 2070 return 0; 2071 2072err_iounmap_screen_base: 2073#ifdef CONFIG_FB_RIVA_I2C 2074 riva_delete_i2c_busses(info->par); 2075#endif 2076 iounmap(info->screen_base); 2077err_iounmap_pramin: 2078 if (default_par->riva.Architecture == NV_ARCH_03) 2079 iounmap(default_par->riva.PRAMIN); 2080err_iounmap_ctrl_base: 2081 iounmap(default_par->ctrl_base); 2082err_release_region: 2083 pci_release_regions(pd); 2084err_disable_device: 2085err_free_pixmap: 2086 kfree(info->pixmap.addr); 2087err_framebuffer_release: 2088 framebuffer_release(info); 2089err_ret: 2090 return ret; 2091} 2092 2093static void rivafb_remove(struct pci_dev *pd) 2094{ 2095 struct fb_info *info = pci_get_drvdata(pd); 2096 struct riva_par *par = info->par; 2097 2098 NVTRACE_ENTER(); 2099 2100#ifdef CONFIG_FB_RIVA_I2C 2101 riva_delete_i2c_busses(par); 2102 kfree(par->EDID); 2103#endif 2104 2105 unregister_framebuffer(info); 2106 2107 riva_bl_exit(info); 2108 2109#ifdef CONFIG_MTRR 2110 if (par->mtrr.vram_valid) 2111 mtrr_del(par->mtrr.vram, info->fix.smem_start, 2112 info->fix.smem_len); 2113#endif /* CONFIG_MTRR */ 2114 2115 iounmap(par->ctrl_base); 2116 iounmap(info->screen_base); 2117 if (par->riva.Architecture == NV_ARCH_03) 2118 iounmap(par->riva.PRAMIN); 2119 pci_release_regions(pd); 2120 kfree(info->pixmap.addr); 2121 framebuffer_release(info); 2122 NVTRACE_LEAVE(); 2123} 2124 2125/* ------------------------------------------------------------------------- * 2126 * 2127 * initialization 2128 * 2129 * ------------------------------------------------------------------------- */ 2130 2131#ifndef MODULE 2132static int rivafb_setup(char *options) 2133{ 2134 char *this_opt; 2135 2136 NVTRACE_ENTER(); 2137 if (!options || !*options) 2138 return 0; 2139 2140 while ((this_opt = strsep(&options, ",")) != NULL) { 2141 if (!strncmp(this_opt, "forceCRTC", 9)) { 2142 char *p; 2143 2144 p = this_opt + 9; 2145 if (!*p || !*(++p)) continue; 2146 forceCRTC = *p - '0'; 2147 if (forceCRTC < 0 || forceCRTC > 1) 2148 forceCRTC = -1; 2149 } else if (!strncmp(this_opt, "flatpanel", 9)) { 2150 flatpanel = 1; 2151 } else if (!strncmp(this_opt, "backlight:", 10)) { 2152 backlight = simple_strtoul(this_opt+10, NULL, 0); 2153#ifdef CONFIG_MTRR 2154 } else if (!strncmp(this_opt, "nomtrr", 6)) { 2155 nomtrr = 1; 2156#endif 2157 } else if (!strncmp(this_opt, "strictmode", 10)) { 2158 strictmode = 1; 2159 } else if (!strncmp(this_opt, "noaccel", 7)) { 2160 noaccel = 1; 2161 } else 2162 mode_option = this_opt; 2163 } 2164 NVTRACE_LEAVE(); 2165 return 0; 2166} 2167#endif /* !MODULE */ 2168 2169static struct pci_driver rivafb_driver = { 2170 .name = "rivafb", 2171 .id_table = rivafb_pci_tbl, 2172 .probe = rivafb_probe, 2173 .remove = rivafb_remove, 2174}; 2175 2176 2177 2178/* ------------------------------------------------------------------------- * 2179 * 2180 * modularization 2181 * 2182 * ------------------------------------------------------------------------- */ 2183 2184static int rivafb_init(void) 2185{ 2186#ifndef MODULE 2187 char *option = NULL; 2188 2189 if (fb_get_options("rivafb", &option)) 2190 return -ENODEV; 2191 rivafb_setup(option); 2192#endif 2193 return pci_register_driver(&rivafb_driver); 2194} 2195 2196 2197module_init(rivafb_init); 2198 2199static void __exit rivafb_exit(void) 2200{ 2201 pci_unregister_driver(&rivafb_driver); 2202} 2203 2204module_exit(rivafb_exit); 2205 2206module_param(noaccel, bool, 0); 2207MODULE_PARM_DESC(noaccel, "bool: disable acceleration"); 2208module_param(flatpanel, int, 0); 2209MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)"); 2210module_param(forceCRTC, int, 0); 2211MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)"); 2212#ifdef CONFIG_MTRR 2213module_param(nomtrr, bool, 0); 2214MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)"); 2215#endif 2216module_param(strictmode, bool, 0); 2217MODULE_PARM_DESC(strictmode, "Only use video modes from EDID"); 2218 2219MODULE_AUTHOR("Ani Joshi, maintainer"); 2220MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series"); 2221MODULE_LICENSE("GPL"); 2222