1/* 2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18#ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H 19#define __LINUX_IRQCHIP_ARM_GIC_V3_H 20 21#include <asm/sysreg.h> 22 23/* 24 * Distributor registers. We assume we're running non-secure, with ARE 25 * being set. Secure-only and non-ARE registers are not described. 26 */ 27#define GICD_CTLR 0x0000 28#define GICD_TYPER 0x0004 29#define GICD_IIDR 0x0008 30#define GICD_STATUSR 0x0010 31#define GICD_SETSPI_NSR 0x0040 32#define GICD_CLRSPI_NSR 0x0048 33#define GICD_SETSPI_SR 0x0050 34#define GICD_CLRSPI_SR 0x0058 35#define GICD_SEIR 0x0068 36#define GICD_IGROUPR 0x0080 37#define GICD_ISENABLER 0x0100 38#define GICD_ICENABLER 0x0180 39#define GICD_ISPENDR 0x0200 40#define GICD_ICPENDR 0x0280 41#define GICD_ISACTIVER 0x0300 42#define GICD_ICACTIVER 0x0380 43#define GICD_IPRIORITYR 0x0400 44#define GICD_ICFGR 0x0C00 45#define GICD_IGRPMODR 0x0D00 46#define GICD_NSACR 0x0E00 47#define GICD_IROUTER 0x6000 48#define GICD_IDREGS 0xFFD0 49#define GICD_PIDR2 0xFFE8 50 51/* 52 * Those registers are actually from GICv2, but the spec demands that they 53 * are implemented as RES0 if ARE is 1 (which we do in KVM's emulated GICv3). 54 */ 55#define GICD_ITARGETSR 0x0800 56#define GICD_SGIR 0x0F00 57#define GICD_CPENDSGIR 0x0F10 58#define GICD_SPENDSGIR 0x0F20 59 60#define GICD_CTLR_RWP (1U << 31) 61#define GICD_CTLR_DS (1U << 6) 62#define GICD_CTLR_ARE_NS (1U << 4) 63#define GICD_CTLR_ENABLE_G1A (1U << 1) 64#define GICD_CTLR_ENABLE_G1 (1U << 0) 65 66/* 67 * In systems with a single security state (what we emulate in KVM) 68 * the meaning of the interrupt group enable bits is slightly different 69 */ 70#define GICD_CTLR_ENABLE_SS_G1 (1U << 1) 71#define GICD_CTLR_ENABLE_SS_G0 (1U << 0) 72 73#define GICD_TYPER_LPIS (1U << 17) 74#define GICD_TYPER_MBIS (1U << 16) 75 76#define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1) 77#define GICD_TYPER_IRQS(typer) ((((typer) & 0x1f) + 1) * 32) 78#define GICD_TYPER_LPIS (1U << 17) 79 80#define GICD_IROUTER_SPI_MODE_ONE (0U << 31) 81#define GICD_IROUTER_SPI_MODE_ANY (1U << 31) 82 83#define GIC_PIDR2_ARCH_MASK 0xf0 84#define GIC_PIDR2_ARCH_GICv3 0x30 85#define GIC_PIDR2_ARCH_GICv4 0x40 86 87#define GIC_V3_DIST_SIZE 0x10000 88 89/* 90 * Re-Distributor registers, offsets from RD_base 91 */ 92#define GICR_CTLR GICD_CTLR 93#define GICR_IIDR 0x0004 94#define GICR_TYPER 0x0008 95#define GICR_STATUSR GICD_STATUSR 96#define GICR_WAKER 0x0014 97#define GICR_SETLPIR 0x0040 98#define GICR_CLRLPIR 0x0048 99#define GICR_SEIR GICD_SEIR 100#define GICR_PROPBASER 0x0070 101#define GICR_PENDBASER 0x0078 102#define GICR_INVLPIR 0x00A0 103#define GICR_INVALLR 0x00B0 104#define GICR_SYNCR 0x00C0 105#define GICR_MOVLPIR 0x0100 106#define GICR_MOVALLR 0x0110 107#define GICR_IDREGS GICD_IDREGS 108#define GICR_PIDR2 GICD_PIDR2 109 110#define GICR_CTLR_ENABLE_LPIS (1UL << 0) 111 112#define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff) 113 114#define GICR_WAKER_ProcessorSleep (1U << 1) 115#define GICR_WAKER_ChildrenAsleep (1U << 2) 116 117#define GICR_PROPBASER_NonShareable (0U << 10) 118#define GICR_PROPBASER_InnerShareable (1U << 10) 119#define GICR_PROPBASER_OuterShareable (2U << 10) 120#define GICR_PROPBASER_SHAREABILITY_MASK (3UL << 10) 121#define GICR_PROPBASER_nCnB (0U << 7) 122#define GICR_PROPBASER_nC (1U << 7) 123#define GICR_PROPBASER_RaWt (2U << 7) 124#define GICR_PROPBASER_RaWb (3U << 7) 125#define GICR_PROPBASER_WaWt (4U << 7) 126#define GICR_PROPBASER_WaWb (5U << 7) 127#define GICR_PROPBASER_RaWaWt (6U << 7) 128#define GICR_PROPBASER_RaWaWb (7U << 7) 129#define GICR_PROPBASER_CACHEABILITY_MASK (7U << 7) 130#define GICR_PROPBASER_IDBITS_MASK (0x1f) 131 132#define GICR_PENDBASER_NonShareable (0U << 10) 133#define GICR_PENDBASER_InnerShareable (1U << 10) 134#define GICR_PENDBASER_OuterShareable (2U << 10) 135#define GICR_PENDBASER_SHAREABILITY_MASK (3UL << 10) 136#define GICR_PENDBASER_nCnB (0U << 7) 137#define GICR_PENDBASER_nC (1U << 7) 138#define GICR_PENDBASER_RaWt (2U << 7) 139#define GICR_PENDBASER_RaWb (3U << 7) 140#define GICR_PENDBASER_WaWt (4U << 7) 141#define GICR_PENDBASER_WaWb (5U << 7) 142#define GICR_PENDBASER_RaWaWt (6U << 7) 143#define GICR_PENDBASER_RaWaWb (7U << 7) 144#define GICR_PENDBASER_CACHEABILITY_MASK (7U << 7) 145 146/* 147 * Re-Distributor registers, offsets from SGI_base 148 */ 149#define GICR_IGROUPR0 GICD_IGROUPR 150#define GICR_ISENABLER0 GICD_ISENABLER 151#define GICR_ICENABLER0 GICD_ICENABLER 152#define GICR_ISPENDR0 GICD_ISPENDR 153#define GICR_ICPENDR0 GICD_ICPENDR 154#define GICR_ISACTIVER0 GICD_ISACTIVER 155#define GICR_ICACTIVER0 GICD_ICACTIVER 156#define GICR_IPRIORITYR0 GICD_IPRIORITYR 157#define GICR_ICFGR0 GICD_ICFGR 158#define GICR_IGRPMODR0 GICD_IGRPMODR 159#define GICR_NSACR GICD_NSACR 160 161#define GICR_TYPER_PLPIS (1U << 0) 162#define GICR_TYPER_VLPIS (1U << 1) 163#define GICR_TYPER_LAST (1U << 4) 164 165#define GIC_V3_REDIST_SIZE 0x20000 166 167#define LPI_PROP_GROUP1 (1 << 1) 168#define LPI_PROP_ENABLED (1 << 0) 169 170/* 171 * ITS registers, offsets from ITS_base 172 */ 173#define GITS_CTLR 0x0000 174#define GITS_IIDR 0x0004 175#define GITS_TYPER 0x0008 176#define GITS_CBASER 0x0080 177#define GITS_CWRITER 0x0088 178#define GITS_CREADR 0x0090 179#define GITS_BASER 0x0100 180#define GITS_PIDR2 GICR_PIDR2 181 182#define GITS_TRANSLATER 0x10040 183 184#define GITS_CTLR_ENABLE (1U << 0) 185#define GITS_CTLR_QUIESCENT (1U << 31) 186 187#define GITS_TYPER_DEVBITS_SHIFT 13 188#define GITS_TYPER_DEVBITS(r) ((((r) >> GITS_TYPER_DEVBITS_SHIFT) & 0x1f) + 1) 189#define GITS_TYPER_PTA (1UL << 19) 190 191#define GITS_CBASER_VALID (1UL << 63) 192#define GITS_CBASER_nCnB (0UL << 59) 193#define GITS_CBASER_nC (1UL << 59) 194#define GITS_CBASER_RaWt (2UL << 59) 195#define GITS_CBASER_RaWb (3UL << 59) 196#define GITS_CBASER_WaWt (4UL << 59) 197#define GITS_CBASER_WaWb (5UL << 59) 198#define GITS_CBASER_RaWaWt (6UL << 59) 199#define GITS_CBASER_RaWaWb (7UL << 59) 200#define GITS_CBASER_CACHEABILITY_MASK (7UL << 59) 201#define GITS_CBASER_NonShareable (0UL << 10) 202#define GITS_CBASER_InnerShareable (1UL << 10) 203#define GITS_CBASER_OuterShareable (2UL << 10) 204#define GITS_CBASER_SHAREABILITY_MASK (3UL << 10) 205 206#define GITS_BASER_NR_REGS 8 207 208#define GITS_BASER_VALID (1UL << 63) 209#define GITS_BASER_nCnB (0UL << 59) 210#define GITS_BASER_nC (1UL << 59) 211#define GITS_BASER_RaWt (2UL << 59) 212#define GITS_BASER_RaWb (3UL << 59) 213#define GITS_BASER_WaWt (4UL << 59) 214#define GITS_BASER_WaWb (5UL << 59) 215#define GITS_BASER_RaWaWt (6UL << 59) 216#define GITS_BASER_RaWaWb (7UL << 59) 217#define GITS_BASER_CACHEABILITY_MASK (7UL << 59) 218#define GITS_BASER_TYPE_SHIFT (56) 219#define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7) 220#define GITS_BASER_ENTRY_SIZE_SHIFT (48) 221#define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0xff) + 1) 222#define GITS_BASER_NonShareable (0UL << 10) 223#define GITS_BASER_InnerShareable (1UL << 10) 224#define GITS_BASER_OuterShareable (2UL << 10) 225#define GITS_BASER_SHAREABILITY_SHIFT (10) 226#define GITS_BASER_SHAREABILITY_MASK (3UL << GITS_BASER_SHAREABILITY_SHIFT) 227#define GITS_BASER_PAGE_SIZE_SHIFT (8) 228#define GITS_BASER_PAGE_SIZE_4K (0UL << GITS_BASER_PAGE_SIZE_SHIFT) 229#define GITS_BASER_PAGE_SIZE_16K (1UL << GITS_BASER_PAGE_SIZE_SHIFT) 230#define GITS_BASER_PAGE_SIZE_64K (2UL << GITS_BASER_PAGE_SIZE_SHIFT) 231#define GITS_BASER_PAGE_SIZE_MASK (3UL << GITS_BASER_PAGE_SIZE_SHIFT) 232 233#define GITS_BASER_TYPE_NONE 0 234#define GITS_BASER_TYPE_DEVICE 1 235#define GITS_BASER_TYPE_VCPU 2 236#define GITS_BASER_TYPE_CPU 3 237#define GITS_BASER_TYPE_COLLECTION 4 238#define GITS_BASER_TYPE_RESERVED5 5 239#define GITS_BASER_TYPE_RESERVED6 6 240#define GITS_BASER_TYPE_RESERVED7 7 241 242/* 243 * ITS commands 244 */ 245#define GITS_CMD_MAPD 0x08 246#define GITS_CMD_MAPC 0x09 247#define GITS_CMD_MAPVI 0x0a 248#define GITS_CMD_MOVI 0x01 249#define GITS_CMD_DISCARD 0x0f 250#define GITS_CMD_INV 0x0c 251#define GITS_CMD_MOVALL 0x0e 252#define GITS_CMD_INVALL 0x0d 253#define GITS_CMD_INT 0x03 254#define GITS_CMD_CLEAR 0x04 255#define GITS_CMD_SYNC 0x05 256 257/* 258 * CPU interface registers 259 */ 260#define ICC_CTLR_EL1_EOImode_drop_dir (0U << 1) 261#define ICC_CTLR_EL1_EOImode_drop (1U << 1) 262#define ICC_SRE_EL1_SRE (1U << 0) 263 264/* 265 * Hypervisor interface registers (SRE only) 266 */ 267#define ICH_LR_VIRTUAL_ID_MASK ((1UL << 32) - 1) 268 269#define ICH_LR_EOI (1UL << 41) 270#define ICH_LR_GROUP (1UL << 60) 271#define ICH_LR_STATE (3UL << 62) 272#define ICH_LR_PENDING_BIT (1UL << 62) 273#define ICH_LR_ACTIVE_BIT (1UL << 63) 274 275#define ICH_MISR_EOI (1 << 0) 276#define ICH_MISR_U (1 << 1) 277 278#define ICH_HCR_EN (1 << 0) 279#define ICH_HCR_UIE (1 << 1) 280 281#define ICH_VMCR_CTLR_SHIFT 0 282#define ICH_VMCR_CTLR_MASK (0x21f << ICH_VMCR_CTLR_SHIFT) 283#define ICH_VMCR_BPR1_SHIFT 18 284#define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT) 285#define ICH_VMCR_BPR0_SHIFT 21 286#define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT) 287#define ICH_VMCR_PMR_SHIFT 24 288#define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT) 289 290#define ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) 291#define ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) 292#define ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5) 293#define ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) 294#define ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4) 295#define ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5) 296#define ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) 297 298#define ICC_IAR1_EL1_SPURIOUS 0x3ff 299 300#define ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5) 301 302#define ICC_SRE_EL2_SRE (1 << 0) 303#define ICC_SRE_EL2_ENABLE (1 << 3) 304 305#define ICC_SGI1R_TARGET_LIST_SHIFT 0 306#define ICC_SGI1R_TARGET_LIST_MASK (0xffff << ICC_SGI1R_TARGET_LIST_SHIFT) 307#define ICC_SGI1R_AFFINITY_1_SHIFT 16 308#define ICC_SGI1R_AFFINITY_1_MASK (0xff << ICC_SGI1R_AFFINITY_1_SHIFT) 309#define ICC_SGI1R_SGI_ID_SHIFT 24 310#define ICC_SGI1R_SGI_ID_MASK (0xfULL << ICC_SGI1R_SGI_ID_SHIFT) 311#define ICC_SGI1R_AFFINITY_2_SHIFT 32 312#define ICC_SGI1R_AFFINITY_2_MASK (0xffULL << ICC_SGI1R_AFFINITY_1_SHIFT) 313#define ICC_SGI1R_IRQ_ROUTING_MODE_BIT 40 314#define ICC_SGI1R_AFFINITY_3_SHIFT 48 315#define ICC_SGI1R_AFFINITY_3_MASK (0xffULL << ICC_SGI1R_AFFINITY_1_SHIFT) 316 317/* 318 * System register definitions 319 */ 320#define ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4) 321#define ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0) 322#define ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1) 323#define ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2) 324#define ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3) 325#define ICH_ELSR_EL2 sys_reg(3, 4, 12, 11, 5) 326#define ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7) 327 328#define __LR0_EL2(x) sys_reg(3, 4, 12, 12, x) 329#define __LR8_EL2(x) sys_reg(3, 4, 12, 13, x) 330 331#define ICH_LR0_EL2 __LR0_EL2(0) 332#define ICH_LR1_EL2 __LR0_EL2(1) 333#define ICH_LR2_EL2 __LR0_EL2(2) 334#define ICH_LR3_EL2 __LR0_EL2(3) 335#define ICH_LR4_EL2 __LR0_EL2(4) 336#define ICH_LR5_EL2 __LR0_EL2(5) 337#define ICH_LR6_EL2 __LR0_EL2(6) 338#define ICH_LR7_EL2 __LR0_EL2(7) 339#define ICH_LR8_EL2 __LR8_EL2(0) 340#define ICH_LR9_EL2 __LR8_EL2(1) 341#define ICH_LR10_EL2 __LR8_EL2(2) 342#define ICH_LR11_EL2 __LR8_EL2(3) 343#define ICH_LR12_EL2 __LR8_EL2(4) 344#define ICH_LR13_EL2 __LR8_EL2(5) 345#define ICH_LR14_EL2 __LR8_EL2(6) 346#define ICH_LR15_EL2 __LR8_EL2(7) 347 348#define __AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x) 349#define ICH_AP0R0_EL2 __AP0Rx_EL2(0) 350#define ICH_AP0R1_EL2 __AP0Rx_EL2(1) 351#define ICH_AP0R2_EL2 __AP0Rx_EL2(2) 352#define ICH_AP0R3_EL2 __AP0Rx_EL2(3) 353 354#define __AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x) 355#define ICH_AP1R0_EL2 __AP1Rx_EL2(0) 356#define ICH_AP1R1_EL2 __AP1Rx_EL2(1) 357#define ICH_AP1R2_EL2 __AP1Rx_EL2(2) 358#define ICH_AP1R3_EL2 __AP1Rx_EL2(3) 359 360#ifndef __ASSEMBLY__ 361 362#include <linux/stringify.h> 363 364/* 365 * We need a value to serve as a irq-type for LPIs. Choose one that will 366 * hopefully pique the interest of the reviewer. 367 */ 368#define GIC_IRQ_TYPE_LPI 0xa110c8ed 369 370struct rdists { 371 struct { 372 void __iomem *rd_base; 373 struct page *pend_page; 374 phys_addr_t phys_base; 375 } __percpu *rdist; 376 struct page *prop_page; 377 int id_bits; 378 u64 flags; 379}; 380 381static inline void gic_write_eoir(u64 irq) 382{ 383 asm volatile("msr_s " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" (irq)); 384 isb(); 385} 386 387struct irq_domain; 388int its_cpu_init(void); 389int its_init(struct device_node *node, struct rdists *rdists, 390 struct irq_domain *domain); 391 392#endif 393 394#endif 395