1#ifndef __SH_CLOCK_H
2#define __SH_CLOCK_H
3
4#include <linux/list.h>
5#include <linux/seq_file.h>
6#include <linux/cpufreq.h>
7#include <linux/types.h>
8#include <linux/kref.h>
9#include <linux/clk.h>
10#include <linux/err.h>
11
12struct clk;
13
14struct clk_mapping {
15	phys_addr_t		phys;
16	void __iomem		*base;
17	unsigned long		len;
18	struct kref		ref;
19};
20
21struct sh_clk_ops {
22#ifdef CONFIG_SH_CLK_CPG_LEGACY
23	void (*init)(struct clk *clk);
24#endif
25	int (*enable)(struct clk *clk);
26	void (*disable)(struct clk *clk);
27	unsigned long (*recalc)(struct clk *clk);
28	int (*set_rate)(struct clk *clk, unsigned long rate);
29	int (*set_parent)(struct clk *clk, struct clk *parent);
30	long (*round_rate)(struct clk *clk, unsigned long rate);
31};
32
33#define SH_CLK_DIV_MSK(div)	((1 << (div)) - 1)
34#define SH_CLK_DIV4_MSK		SH_CLK_DIV_MSK(4)
35#define SH_CLK_DIV6_MSK		SH_CLK_DIV_MSK(6)
36
37struct clk {
38	struct list_head	node;
39	struct clk		*parent;
40	struct clk		**parent_table;	/* list of parents to */
41	unsigned short		parent_num;	/* choose between */
42	unsigned char		src_shift;	/* source clock field in the */
43	unsigned char		src_width;	/* configuration register */
44	struct sh_clk_ops	*ops;
45
46	struct list_head	children;
47	struct list_head	sibling;	/* node for children */
48
49	int			usecount;
50
51	unsigned long		rate;
52	unsigned long		flags;
53
54	void __iomem		*enable_reg;
55	void __iomem		*status_reg;
56	unsigned int		enable_bit;
57	void __iomem		*mapped_reg;
58
59	unsigned int		div_mask;
60	unsigned long		arch_flags;
61	void			*priv;
62	struct clk_mapping	*mapping;
63	struct cpufreq_frequency_table *freq_table;
64	unsigned int		nr_freqs;
65};
66
67#define CLK_ENABLE_ON_INIT	BIT(0)
68
69#define CLK_ENABLE_REG_32BIT	BIT(1)	/* default access size */
70#define CLK_ENABLE_REG_16BIT	BIT(2)
71#define CLK_ENABLE_REG_8BIT	BIT(3)
72
73#define CLK_MASK_DIV_ON_DISABLE	BIT(4)
74
75#define CLK_ENABLE_REG_MASK	(CLK_ENABLE_REG_32BIT | \
76				 CLK_ENABLE_REG_16BIT | \
77				 CLK_ENABLE_REG_8BIT)
78
79/* drivers/sh/clk.c */
80unsigned long followparent_recalc(struct clk *);
81void recalculate_root_clocks(void);
82void propagate_rate(struct clk *);
83int clk_reparent(struct clk *child, struct clk *parent);
84int clk_register(struct clk *);
85void clk_unregister(struct clk *);
86void clk_enable_init_clocks(void);
87
88struct clk_div_mult_table {
89	unsigned int *divisors;
90	unsigned int nr_divisors;
91	unsigned int *multipliers;
92	unsigned int nr_multipliers;
93};
94
95struct cpufreq_frequency_table;
96void clk_rate_table_build(struct clk *clk,
97			  struct cpufreq_frequency_table *freq_table,
98			  int nr_freqs,
99			  struct clk_div_mult_table *src_table,
100			  unsigned long *bitmap);
101
102long clk_rate_table_round(struct clk *clk,
103			  struct cpufreq_frequency_table *freq_table,
104			  unsigned long rate);
105
106int clk_rate_table_find(struct clk *clk,
107			struct cpufreq_frequency_table *freq_table,
108			unsigned long rate);
109
110long clk_rate_div_range_round(struct clk *clk, unsigned int div_min,
111			      unsigned int div_max, unsigned long rate);
112
113long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min,
114			       unsigned int mult_max, unsigned long rate);
115
116long clk_round_parent(struct clk *clk, unsigned long target,
117		      unsigned long *best_freq, unsigned long *parent_freq,
118		      unsigned int div_min, unsigned int div_max);
119
120#define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _status_reg, _flags) \
121{									\
122	.parent		= _parent,					\
123	.enable_reg	= (void __iomem *)_enable_reg,			\
124	.enable_bit	= _enable_bit,					\
125	.status_reg	= _status_reg,					\
126	.flags		= _flags,					\
127}
128
129#define SH_CLK_MSTP32(_p, _r, _b, _f)				\
130	SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_32BIT)
131
132#define SH_CLK_MSTP32_STS(_p, _r, _b, _s, _f)			\
133	SH_CLK_MSTP(_p, _r, _b, _s, _f | CLK_ENABLE_REG_32BIT)
134
135#define SH_CLK_MSTP16(_p, _r, _b, _f)				\
136	SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_16BIT)
137
138#define SH_CLK_MSTP8(_p, _r, _b, _f)				\
139	SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_8BIT)
140
141int sh_clk_mstp_register(struct clk *clks, int nr);
142
143/*
144 * MSTP registration never really cared about access size, despite the
145 * original enable/disable pairs assuming a 32-bit access. Clocks are
146 * responsible for defining their access sizes either directly or via the
147 * clock definition wrappers.
148 */
149static inline int __deprecated sh_clk_mstp32_register(struct clk *clks, int nr)
150{
151	return sh_clk_mstp_register(clks, nr);
152}
153
154#define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags)	\
155{								\
156	.parent = _parent,					\
157	.enable_reg = (void __iomem *)_reg,			\
158	.enable_bit = _shift,					\
159	.arch_flags = _div_bitmap,				\
160	.div_mask = SH_CLK_DIV4_MSK,				\
161	.flags = _flags,					\
162}
163
164struct clk_div_table {
165	struct clk_div_mult_table *div_mult_table;
166	void (*kick)(struct clk *clk);
167};
168
169#define clk_div4_table clk_div_table
170
171int sh_clk_div4_register(struct clk *clks, int nr,
172			 struct clk_div4_table *table);
173int sh_clk_div4_enable_register(struct clk *clks, int nr,
174			 struct clk_div4_table *table);
175int sh_clk_div4_reparent_register(struct clk *clks, int nr,
176			 struct clk_div4_table *table);
177
178#define SH_CLK_DIV6_EXT(_reg, _flags, _parents,			\
179			_num_parents, _src_shift, _src_width)	\
180{								\
181	.enable_reg = (void __iomem *)_reg,			\
182	.enable_bit = 0, /* unused */				\
183	.flags = _flags | CLK_MASK_DIV_ON_DISABLE,		\
184	.div_mask = SH_CLK_DIV6_MSK,				\
185	.parent_table = _parents,				\
186	.parent_num = _num_parents,				\
187	.src_shift = _src_shift,				\
188	.src_width = _src_width,				\
189}
190
191#define SH_CLK_DIV6(_parent, _reg, _flags)			\
192{								\
193	.parent		= _parent,				\
194	.enable_reg	= (void __iomem *)_reg,			\
195	.enable_bit	= 0,	/* unused */			\
196	.div_mask	= SH_CLK_DIV6_MSK,			\
197	.flags		= _flags | CLK_MASK_DIV_ON_DISABLE,	\
198}
199
200int sh_clk_div6_register(struct clk *clks, int nr);
201int sh_clk_div6_reparent_register(struct clk *clks, int nr);
202
203#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
204#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
205#define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
206
207/* .enable_reg will be updated to .mapping on sh_clk_fsidiv_register() */
208#define SH_CLK_FSIDIV(_reg, _parent)		\
209{						\
210	.enable_reg = (void __iomem *)_reg,	\
211	.parent		= _parent,		\
212}
213
214int sh_clk_fsidiv_register(struct clk *clks, int nr);
215
216#endif /* __SH_CLOCK_H */
217