1/*
2 * rt5677.c  --  RT5677 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Oder Chiou <oder_chiou@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/fs.h>
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
18#include <linux/of_gpio.h>
19#include <linux/regmap.h>
20#include <linux/i2c.h>
21#include <linux/platform_device.h>
22#include <linux/spi/spi.h>
23#include <linux/firmware.h>
24#include <linux/gpio.h>
25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
29#include <sound/soc-dapm.h>
30#include <sound/initval.h>
31#include <sound/tlv.h>
32
33#include "rl6231.h"
34#include "rt5677.h"
35#include "rt5677-spi.h"
36
37#define RT5677_DEVICE_ID 0x6327
38
39#define RT5677_PR_RANGE_BASE (0xff + 1)
40#define RT5677_PR_SPACING 0x100
41
42#define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
43
44static const struct regmap_range_cfg rt5677_ranges[] = {
45	{
46		.name = "PR",
47		.range_min = RT5677_PR_BASE,
48		.range_max = RT5677_PR_BASE + 0xfd,
49		.selector_reg = RT5677_PRIV_INDEX,
50		.selector_mask = 0xff,
51		.selector_shift = 0x0,
52		.window_start = RT5677_PRIV_DATA,
53		.window_len = 0x1,
54	},
55};
56
57static const struct reg_default init_list[] = {
58	{RT5677_ASRC_12,	0x0018},
59	{RT5677_PR_BASE + 0x3d,	0x364d},
60	{RT5677_PR_BASE + 0x17,	0x4fc0},
61	{RT5677_PR_BASE + 0x13,	0x0312},
62	{RT5677_PR_BASE + 0x1e,	0x0000},
63	{RT5677_PR_BASE + 0x12,	0x0eaa},
64	{RT5677_PR_BASE + 0x14,	0x018a},
65	{RT5677_PR_BASE + 0x15,	0x0490},
66	{RT5677_PR_BASE + 0x38,	0x0f71},
67	{RT5677_PR_BASE + 0x39,	0x0f71},
68};
69#define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
70
71static const struct reg_default rt5677_reg[] = {
72	{RT5677_RESET			, 0x0000},
73	{RT5677_LOUT1			, 0xa800},
74	{RT5677_IN1			, 0x0000},
75	{RT5677_MICBIAS			, 0x0000},
76	{RT5677_SLIMBUS_PARAM		, 0x0000},
77	{RT5677_SLIMBUS_RX		, 0x0000},
78	{RT5677_SLIMBUS_CTRL		, 0x0000},
79	{RT5677_SIDETONE_CTRL		, 0x000b},
80	{RT5677_ANA_DAC1_2_3_SRC	, 0x0000},
81	{RT5677_IF_DSP_DAC3_4_MIXER	, 0x1111},
82	{RT5677_DAC4_DIG_VOL		, 0xafaf},
83	{RT5677_DAC3_DIG_VOL		, 0xafaf},
84	{RT5677_DAC1_DIG_VOL		, 0xafaf},
85	{RT5677_DAC2_DIG_VOL		, 0xafaf},
86	{RT5677_IF_DSP_DAC2_MIXER	, 0x0011},
87	{RT5677_STO1_ADC_DIG_VOL	, 0x2f2f},
88	{RT5677_MONO_ADC_DIG_VOL	, 0x2f2f},
89	{RT5677_STO1_2_ADC_BST		, 0x0000},
90	{RT5677_STO2_ADC_DIG_VOL	, 0x2f2f},
91	{RT5677_ADC_BST_CTRL2		, 0x0000},
92	{RT5677_STO3_4_ADC_BST		, 0x0000},
93	{RT5677_STO3_ADC_DIG_VOL	, 0x2f2f},
94	{RT5677_STO4_ADC_DIG_VOL	, 0x2f2f},
95	{RT5677_STO4_ADC_MIXER		, 0xd4c0},
96	{RT5677_STO3_ADC_MIXER		, 0xd4c0},
97	{RT5677_STO2_ADC_MIXER		, 0xd4c0},
98	{RT5677_STO1_ADC_MIXER		, 0xd4c0},
99	{RT5677_MONO_ADC_MIXER		, 0xd4d1},
100	{RT5677_ADC_IF_DSP_DAC1_MIXER	, 0x8080},
101	{RT5677_STO1_DAC_MIXER		, 0xaaaa},
102	{RT5677_MONO_DAC_MIXER		, 0xaaaa},
103	{RT5677_DD1_MIXER		, 0xaaaa},
104	{RT5677_DD2_MIXER		, 0xaaaa},
105	{RT5677_IF3_DATA		, 0x0000},
106	{RT5677_IF4_DATA		, 0x0000},
107	{RT5677_PDM_OUT_CTRL		, 0x8888},
108	{RT5677_PDM_DATA_CTRL1		, 0x0000},
109	{RT5677_PDM_DATA_CTRL2		, 0x0000},
110	{RT5677_PDM1_DATA_CTRL2		, 0x0000},
111	{RT5677_PDM1_DATA_CTRL3		, 0x0000},
112	{RT5677_PDM1_DATA_CTRL4		, 0x0000},
113	{RT5677_PDM2_DATA_CTRL2		, 0x0000},
114	{RT5677_PDM2_DATA_CTRL3		, 0x0000},
115	{RT5677_PDM2_DATA_CTRL4		, 0x0000},
116	{RT5677_TDM1_CTRL1		, 0x0300},
117	{RT5677_TDM1_CTRL2		, 0x0000},
118	{RT5677_TDM1_CTRL3		, 0x4000},
119	{RT5677_TDM1_CTRL4		, 0x0123},
120	{RT5677_TDM1_CTRL5		, 0x4567},
121	{RT5677_TDM2_CTRL1		, 0x0300},
122	{RT5677_TDM2_CTRL2		, 0x0000},
123	{RT5677_TDM2_CTRL3		, 0x4000},
124	{RT5677_TDM2_CTRL4		, 0x0123},
125	{RT5677_TDM2_CTRL5		, 0x4567},
126	{RT5677_I2C_MASTER_CTRL1	, 0x0001},
127	{RT5677_I2C_MASTER_CTRL2	, 0x0000},
128	{RT5677_I2C_MASTER_CTRL3	, 0x0000},
129	{RT5677_I2C_MASTER_CTRL4	, 0x0000},
130	{RT5677_I2C_MASTER_CTRL5	, 0x0000},
131	{RT5677_I2C_MASTER_CTRL6	, 0x0000},
132	{RT5677_I2C_MASTER_CTRL7	, 0x0000},
133	{RT5677_I2C_MASTER_CTRL8	, 0x0000},
134	{RT5677_DMIC_CTRL1		, 0x1505},
135	{RT5677_DMIC_CTRL2		, 0x0055},
136	{RT5677_HAP_GENE_CTRL1		, 0x0111},
137	{RT5677_HAP_GENE_CTRL2		, 0x0064},
138	{RT5677_HAP_GENE_CTRL3		, 0xef0e},
139	{RT5677_HAP_GENE_CTRL4		, 0xf0f0},
140	{RT5677_HAP_GENE_CTRL5		, 0xef0e},
141	{RT5677_HAP_GENE_CTRL6		, 0xf0f0},
142	{RT5677_HAP_GENE_CTRL7		, 0xef0e},
143	{RT5677_HAP_GENE_CTRL8		, 0xf0f0},
144	{RT5677_HAP_GENE_CTRL9		, 0xf000},
145	{RT5677_HAP_GENE_CTRL10		, 0x0000},
146	{RT5677_PWR_DIG1		, 0x0000},
147	{RT5677_PWR_DIG2		, 0x0000},
148	{RT5677_PWR_ANLG1		, 0x0055},
149	{RT5677_PWR_ANLG2		, 0x0000},
150	{RT5677_PWR_DSP1		, 0x0001},
151	{RT5677_PWR_DSP_ST		, 0x0000},
152	{RT5677_PWR_DSP2		, 0x0000},
153	{RT5677_ADC_DAC_HPF_CTRL1	, 0x0e00},
154	{RT5677_PRIV_INDEX		, 0x0000},
155	{RT5677_PRIV_DATA		, 0x0000},
156	{RT5677_I2S4_SDP		, 0x8000},
157	{RT5677_I2S1_SDP		, 0x8000},
158	{RT5677_I2S2_SDP		, 0x8000},
159	{RT5677_I2S3_SDP		, 0x8000},
160	{RT5677_CLK_TREE_CTRL1		, 0x1111},
161	{RT5677_CLK_TREE_CTRL2		, 0x1111},
162	{RT5677_CLK_TREE_CTRL3		, 0x0000},
163	{RT5677_PLL1_CTRL1		, 0x0000},
164	{RT5677_PLL1_CTRL2		, 0x0000},
165	{RT5677_PLL2_CTRL1		, 0x0c60},
166	{RT5677_PLL2_CTRL2		, 0x2000},
167	{RT5677_GLB_CLK1		, 0x0000},
168	{RT5677_GLB_CLK2		, 0x0000},
169	{RT5677_ASRC_1			, 0x0000},
170	{RT5677_ASRC_2			, 0x0000},
171	{RT5677_ASRC_3			, 0x0000},
172	{RT5677_ASRC_4			, 0x0000},
173	{RT5677_ASRC_5			, 0x0000},
174	{RT5677_ASRC_6			, 0x0000},
175	{RT5677_ASRC_7			, 0x0000},
176	{RT5677_ASRC_8			, 0x0000},
177	{RT5677_ASRC_9			, 0x0000},
178	{RT5677_ASRC_10			, 0x0000},
179	{RT5677_ASRC_11			, 0x0000},
180	{RT5677_ASRC_12			, 0x0018},
181	{RT5677_ASRC_13			, 0x0000},
182	{RT5677_ASRC_14			, 0x0000},
183	{RT5677_ASRC_15			, 0x0000},
184	{RT5677_ASRC_16			, 0x0000},
185	{RT5677_ASRC_17			, 0x0000},
186	{RT5677_ASRC_18			, 0x0000},
187	{RT5677_ASRC_19			, 0x0000},
188	{RT5677_ASRC_20			, 0x0000},
189	{RT5677_ASRC_21			, 0x000c},
190	{RT5677_ASRC_22			, 0x0000},
191	{RT5677_ASRC_23			, 0x0000},
192	{RT5677_VAD_CTRL1		, 0x2184},
193	{RT5677_VAD_CTRL2		, 0x010a},
194	{RT5677_VAD_CTRL3		, 0x0aea},
195	{RT5677_VAD_CTRL4		, 0x000c},
196	{RT5677_VAD_CTRL5		, 0x0000},
197	{RT5677_DSP_INB_CTRL1		, 0x0000},
198	{RT5677_DSP_INB_CTRL2		, 0x0000},
199	{RT5677_DSP_IN_OUTB_CTRL	, 0x0000},
200	{RT5677_DSP_OUTB0_1_DIG_VOL	, 0x2f2f},
201	{RT5677_DSP_OUTB2_3_DIG_VOL	, 0x2f2f},
202	{RT5677_DSP_OUTB4_5_DIG_VOL	, 0x2f2f},
203	{RT5677_DSP_OUTB6_7_DIG_VOL	, 0x2f2f},
204	{RT5677_ADC_EQ_CTRL1		, 0x6000},
205	{RT5677_ADC_EQ_CTRL2		, 0x0000},
206	{RT5677_EQ_CTRL1		, 0xc000},
207	{RT5677_EQ_CTRL2		, 0x0000},
208	{RT5677_EQ_CTRL3		, 0x0000},
209	{RT5677_SOFT_VOL_ZERO_CROSS1	, 0x0009},
210	{RT5677_JD_CTRL1		, 0x0000},
211	{RT5677_JD_CTRL2		, 0x0000},
212	{RT5677_JD_CTRL3		, 0x0000},
213	{RT5677_IRQ_CTRL1		, 0x0000},
214	{RT5677_IRQ_CTRL2		, 0x0000},
215	{RT5677_GPIO_ST			, 0x0000},
216	{RT5677_GPIO_CTRL1		, 0x0000},
217	{RT5677_GPIO_CTRL2		, 0x0000},
218	{RT5677_GPIO_CTRL3		, 0x0000},
219	{RT5677_STO1_ADC_HI_FILTER1	, 0xb320},
220	{RT5677_STO1_ADC_HI_FILTER2	, 0x0000},
221	{RT5677_MONO_ADC_HI_FILTER1	, 0xb300},
222	{RT5677_MONO_ADC_HI_FILTER2	, 0x0000},
223	{RT5677_STO2_ADC_HI_FILTER1	, 0xb300},
224	{RT5677_STO2_ADC_HI_FILTER2	, 0x0000},
225	{RT5677_STO3_ADC_HI_FILTER1	, 0xb300},
226	{RT5677_STO3_ADC_HI_FILTER2	, 0x0000},
227	{RT5677_STO4_ADC_HI_FILTER1	, 0xb300},
228	{RT5677_STO4_ADC_HI_FILTER2	, 0x0000},
229	{RT5677_MB_DRC_CTRL1		, 0x0f20},
230	{RT5677_DRC1_CTRL1		, 0x001f},
231	{RT5677_DRC1_CTRL2		, 0x020c},
232	{RT5677_DRC1_CTRL3		, 0x1f00},
233	{RT5677_DRC1_CTRL4		, 0x0000},
234	{RT5677_DRC1_CTRL5		, 0x0000},
235	{RT5677_DRC1_CTRL6		, 0x0029},
236	{RT5677_DRC2_CTRL1		, 0x001f},
237	{RT5677_DRC2_CTRL2		, 0x020c},
238	{RT5677_DRC2_CTRL3		, 0x1f00},
239	{RT5677_DRC2_CTRL4		, 0x0000},
240	{RT5677_DRC2_CTRL5		, 0x0000},
241	{RT5677_DRC2_CTRL6		, 0x0029},
242	{RT5677_DRC1_HL_CTRL1		, 0x8000},
243	{RT5677_DRC1_HL_CTRL2		, 0x0200},
244	{RT5677_DRC2_HL_CTRL1		, 0x8000},
245	{RT5677_DRC2_HL_CTRL2		, 0x0200},
246	{RT5677_DSP_INB1_SRC_CTRL1	, 0x5800},
247	{RT5677_DSP_INB1_SRC_CTRL2	, 0x0000},
248	{RT5677_DSP_INB1_SRC_CTRL3	, 0x0000},
249	{RT5677_DSP_INB1_SRC_CTRL4	, 0x0800},
250	{RT5677_DSP_INB2_SRC_CTRL1	, 0x5800},
251	{RT5677_DSP_INB2_SRC_CTRL2	, 0x0000},
252	{RT5677_DSP_INB2_SRC_CTRL3	, 0x0000},
253	{RT5677_DSP_INB2_SRC_CTRL4	, 0x0800},
254	{RT5677_DSP_INB3_SRC_CTRL1	, 0x5800},
255	{RT5677_DSP_INB3_SRC_CTRL2	, 0x0000},
256	{RT5677_DSP_INB3_SRC_CTRL3	, 0x0000},
257	{RT5677_DSP_INB3_SRC_CTRL4	, 0x0800},
258	{RT5677_DSP_OUTB1_SRC_CTRL1	, 0x5800},
259	{RT5677_DSP_OUTB1_SRC_CTRL2	, 0x0000},
260	{RT5677_DSP_OUTB1_SRC_CTRL3	, 0x0000},
261	{RT5677_DSP_OUTB1_SRC_CTRL4	, 0x0800},
262	{RT5677_DSP_OUTB2_SRC_CTRL1	, 0x5800},
263	{RT5677_DSP_OUTB2_SRC_CTRL2	, 0x0000},
264	{RT5677_DSP_OUTB2_SRC_CTRL3	, 0x0000},
265	{RT5677_DSP_OUTB2_SRC_CTRL4	, 0x0800},
266	{RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
267	{RT5677_DSP_OUTB_45_MIXER_CTRL	, 0xfefe},
268	{RT5677_DSP_OUTB_67_MIXER_CTRL	, 0xfefe},
269	{RT5677_DIG_MISC		, 0x0000},
270	{RT5677_GEN_CTRL1		, 0x0000},
271	{RT5677_GEN_CTRL2		, 0x0000},
272	{RT5677_VENDOR_ID		, 0x0000},
273	{RT5677_VENDOR_ID1		, 0x10ec},
274	{RT5677_VENDOR_ID2		, 0x6327},
275};
276
277static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
278{
279	int i;
280
281	for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
282		if (reg >= rt5677_ranges[i].range_min &&
283			reg <= rt5677_ranges[i].range_max) {
284			return true;
285		}
286	}
287
288	switch (reg) {
289	case RT5677_RESET:
290	case RT5677_SLIMBUS_PARAM:
291	case RT5677_PDM_DATA_CTRL1:
292	case RT5677_PDM_DATA_CTRL2:
293	case RT5677_PDM1_DATA_CTRL4:
294	case RT5677_PDM2_DATA_CTRL4:
295	case RT5677_I2C_MASTER_CTRL1:
296	case RT5677_I2C_MASTER_CTRL7:
297	case RT5677_I2C_MASTER_CTRL8:
298	case RT5677_HAP_GENE_CTRL2:
299	case RT5677_PWR_DSP_ST:
300	case RT5677_PRIV_DATA:
301	case RT5677_PLL1_CTRL2:
302	case RT5677_PLL2_CTRL2:
303	case RT5677_ASRC_22:
304	case RT5677_ASRC_23:
305	case RT5677_VAD_CTRL5:
306	case RT5677_ADC_EQ_CTRL1:
307	case RT5677_EQ_CTRL1:
308	case RT5677_IRQ_CTRL1:
309	case RT5677_IRQ_CTRL2:
310	case RT5677_GPIO_ST:
311	case RT5677_DSP_INB1_SRC_CTRL4:
312	case RT5677_DSP_INB2_SRC_CTRL4:
313	case RT5677_DSP_INB3_SRC_CTRL4:
314	case RT5677_DSP_OUTB1_SRC_CTRL4:
315	case RT5677_DSP_OUTB2_SRC_CTRL4:
316	case RT5677_VENDOR_ID:
317	case RT5677_VENDOR_ID1:
318	case RT5677_VENDOR_ID2:
319		return true;
320	default:
321		return false;
322	}
323}
324
325static bool rt5677_readable_register(struct device *dev, unsigned int reg)
326{
327	int i;
328
329	for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
330		if (reg >= rt5677_ranges[i].range_min &&
331			reg <= rt5677_ranges[i].range_max) {
332			return true;
333		}
334	}
335
336	switch (reg) {
337	case RT5677_RESET:
338	case RT5677_LOUT1:
339	case RT5677_IN1:
340	case RT5677_MICBIAS:
341	case RT5677_SLIMBUS_PARAM:
342	case RT5677_SLIMBUS_RX:
343	case RT5677_SLIMBUS_CTRL:
344	case RT5677_SIDETONE_CTRL:
345	case RT5677_ANA_DAC1_2_3_SRC:
346	case RT5677_IF_DSP_DAC3_4_MIXER:
347	case RT5677_DAC4_DIG_VOL:
348	case RT5677_DAC3_DIG_VOL:
349	case RT5677_DAC1_DIG_VOL:
350	case RT5677_DAC2_DIG_VOL:
351	case RT5677_IF_DSP_DAC2_MIXER:
352	case RT5677_STO1_ADC_DIG_VOL:
353	case RT5677_MONO_ADC_DIG_VOL:
354	case RT5677_STO1_2_ADC_BST:
355	case RT5677_STO2_ADC_DIG_VOL:
356	case RT5677_ADC_BST_CTRL2:
357	case RT5677_STO3_4_ADC_BST:
358	case RT5677_STO3_ADC_DIG_VOL:
359	case RT5677_STO4_ADC_DIG_VOL:
360	case RT5677_STO4_ADC_MIXER:
361	case RT5677_STO3_ADC_MIXER:
362	case RT5677_STO2_ADC_MIXER:
363	case RT5677_STO1_ADC_MIXER:
364	case RT5677_MONO_ADC_MIXER:
365	case RT5677_ADC_IF_DSP_DAC1_MIXER:
366	case RT5677_STO1_DAC_MIXER:
367	case RT5677_MONO_DAC_MIXER:
368	case RT5677_DD1_MIXER:
369	case RT5677_DD2_MIXER:
370	case RT5677_IF3_DATA:
371	case RT5677_IF4_DATA:
372	case RT5677_PDM_OUT_CTRL:
373	case RT5677_PDM_DATA_CTRL1:
374	case RT5677_PDM_DATA_CTRL2:
375	case RT5677_PDM1_DATA_CTRL2:
376	case RT5677_PDM1_DATA_CTRL3:
377	case RT5677_PDM1_DATA_CTRL4:
378	case RT5677_PDM2_DATA_CTRL2:
379	case RT5677_PDM2_DATA_CTRL3:
380	case RT5677_PDM2_DATA_CTRL4:
381	case RT5677_TDM1_CTRL1:
382	case RT5677_TDM1_CTRL2:
383	case RT5677_TDM1_CTRL3:
384	case RT5677_TDM1_CTRL4:
385	case RT5677_TDM1_CTRL5:
386	case RT5677_TDM2_CTRL1:
387	case RT5677_TDM2_CTRL2:
388	case RT5677_TDM2_CTRL3:
389	case RT5677_TDM2_CTRL4:
390	case RT5677_TDM2_CTRL5:
391	case RT5677_I2C_MASTER_CTRL1:
392	case RT5677_I2C_MASTER_CTRL2:
393	case RT5677_I2C_MASTER_CTRL3:
394	case RT5677_I2C_MASTER_CTRL4:
395	case RT5677_I2C_MASTER_CTRL5:
396	case RT5677_I2C_MASTER_CTRL6:
397	case RT5677_I2C_MASTER_CTRL7:
398	case RT5677_I2C_MASTER_CTRL8:
399	case RT5677_DMIC_CTRL1:
400	case RT5677_DMIC_CTRL2:
401	case RT5677_HAP_GENE_CTRL1:
402	case RT5677_HAP_GENE_CTRL2:
403	case RT5677_HAP_GENE_CTRL3:
404	case RT5677_HAP_GENE_CTRL4:
405	case RT5677_HAP_GENE_CTRL5:
406	case RT5677_HAP_GENE_CTRL6:
407	case RT5677_HAP_GENE_CTRL7:
408	case RT5677_HAP_GENE_CTRL8:
409	case RT5677_HAP_GENE_CTRL9:
410	case RT5677_HAP_GENE_CTRL10:
411	case RT5677_PWR_DIG1:
412	case RT5677_PWR_DIG2:
413	case RT5677_PWR_ANLG1:
414	case RT5677_PWR_ANLG2:
415	case RT5677_PWR_DSP1:
416	case RT5677_PWR_DSP_ST:
417	case RT5677_PWR_DSP2:
418	case RT5677_ADC_DAC_HPF_CTRL1:
419	case RT5677_PRIV_INDEX:
420	case RT5677_PRIV_DATA:
421	case RT5677_I2S4_SDP:
422	case RT5677_I2S1_SDP:
423	case RT5677_I2S2_SDP:
424	case RT5677_I2S3_SDP:
425	case RT5677_CLK_TREE_CTRL1:
426	case RT5677_CLK_TREE_CTRL2:
427	case RT5677_CLK_TREE_CTRL3:
428	case RT5677_PLL1_CTRL1:
429	case RT5677_PLL1_CTRL2:
430	case RT5677_PLL2_CTRL1:
431	case RT5677_PLL2_CTRL2:
432	case RT5677_GLB_CLK1:
433	case RT5677_GLB_CLK2:
434	case RT5677_ASRC_1:
435	case RT5677_ASRC_2:
436	case RT5677_ASRC_3:
437	case RT5677_ASRC_4:
438	case RT5677_ASRC_5:
439	case RT5677_ASRC_6:
440	case RT5677_ASRC_7:
441	case RT5677_ASRC_8:
442	case RT5677_ASRC_9:
443	case RT5677_ASRC_10:
444	case RT5677_ASRC_11:
445	case RT5677_ASRC_12:
446	case RT5677_ASRC_13:
447	case RT5677_ASRC_14:
448	case RT5677_ASRC_15:
449	case RT5677_ASRC_16:
450	case RT5677_ASRC_17:
451	case RT5677_ASRC_18:
452	case RT5677_ASRC_19:
453	case RT5677_ASRC_20:
454	case RT5677_ASRC_21:
455	case RT5677_ASRC_22:
456	case RT5677_ASRC_23:
457	case RT5677_VAD_CTRL1:
458	case RT5677_VAD_CTRL2:
459	case RT5677_VAD_CTRL3:
460	case RT5677_VAD_CTRL4:
461	case RT5677_VAD_CTRL5:
462	case RT5677_DSP_INB_CTRL1:
463	case RT5677_DSP_INB_CTRL2:
464	case RT5677_DSP_IN_OUTB_CTRL:
465	case RT5677_DSP_OUTB0_1_DIG_VOL:
466	case RT5677_DSP_OUTB2_3_DIG_VOL:
467	case RT5677_DSP_OUTB4_5_DIG_VOL:
468	case RT5677_DSP_OUTB6_7_DIG_VOL:
469	case RT5677_ADC_EQ_CTRL1:
470	case RT5677_ADC_EQ_CTRL2:
471	case RT5677_EQ_CTRL1:
472	case RT5677_EQ_CTRL2:
473	case RT5677_EQ_CTRL3:
474	case RT5677_SOFT_VOL_ZERO_CROSS1:
475	case RT5677_JD_CTRL1:
476	case RT5677_JD_CTRL2:
477	case RT5677_JD_CTRL3:
478	case RT5677_IRQ_CTRL1:
479	case RT5677_IRQ_CTRL2:
480	case RT5677_GPIO_ST:
481	case RT5677_GPIO_CTRL1:
482	case RT5677_GPIO_CTRL2:
483	case RT5677_GPIO_CTRL3:
484	case RT5677_STO1_ADC_HI_FILTER1:
485	case RT5677_STO1_ADC_HI_FILTER2:
486	case RT5677_MONO_ADC_HI_FILTER1:
487	case RT5677_MONO_ADC_HI_FILTER2:
488	case RT5677_STO2_ADC_HI_FILTER1:
489	case RT5677_STO2_ADC_HI_FILTER2:
490	case RT5677_STO3_ADC_HI_FILTER1:
491	case RT5677_STO3_ADC_HI_FILTER2:
492	case RT5677_STO4_ADC_HI_FILTER1:
493	case RT5677_STO4_ADC_HI_FILTER2:
494	case RT5677_MB_DRC_CTRL1:
495	case RT5677_DRC1_CTRL1:
496	case RT5677_DRC1_CTRL2:
497	case RT5677_DRC1_CTRL3:
498	case RT5677_DRC1_CTRL4:
499	case RT5677_DRC1_CTRL5:
500	case RT5677_DRC1_CTRL6:
501	case RT5677_DRC2_CTRL1:
502	case RT5677_DRC2_CTRL2:
503	case RT5677_DRC2_CTRL3:
504	case RT5677_DRC2_CTRL4:
505	case RT5677_DRC2_CTRL5:
506	case RT5677_DRC2_CTRL6:
507	case RT5677_DRC1_HL_CTRL1:
508	case RT5677_DRC1_HL_CTRL2:
509	case RT5677_DRC2_HL_CTRL1:
510	case RT5677_DRC2_HL_CTRL2:
511	case RT5677_DSP_INB1_SRC_CTRL1:
512	case RT5677_DSP_INB1_SRC_CTRL2:
513	case RT5677_DSP_INB1_SRC_CTRL3:
514	case RT5677_DSP_INB1_SRC_CTRL4:
515	case RT5677_DSP_INB2_SRC_CTRL1:
516	case RT5677_DSP_INB2_SRC_CTRL2:
517	case RT5677_DSP_INB2_SRC_CTRL3:
518	case RT5677_DSP_INB2_SRC_CTRL4:
519	case RT5677_DSP_INB3_SRC_CTRL1:
520	case RT5677_DSP_INB3_SRC_CTRL2:
521	case RT5677_DSP_INB3_SRC_CTRL3:
522	case RT5677_DSP_INB3_SRC_CTRL4:
523	case RT5677_DSP_OUTB1_SRC_CTRL1:
524	case RT5677_DSP_OUTB1_SRC_CTRL2:
525	case RT5677_DSP_OUTB1_SRC_CTRL3:
526	case RT5677_DSP_OUTB1_SRC_CTRL4:
527	case RT5677_DSP_OUTB2_SRC_CTRL1:
528	case RT5677_DSP_OUTB2_SRC_CTRL2:
529	case RT5677_DSP_OUTB2_SRC_CTRL3:
530	case RT5677_DSP_OUTB2_SRC_CTRL4:
531	case RT5677_DSP_OUTB_0123_MIXER_CTRL:
532	case RT5677_DSP_OUTB_45_MIXER_CTRL:
533	case RT5677_DSP_OUTB_67_MIXER_CTRL:
534	case RT5677_DIG_MISC:
535	case RT5677_GEN_CTRL1:
536	case RT5677_GEN_CTRL2:
537	case RT5677_VENDOR_ID:
538	case RT5677_VENDOR_ID1:
539	case RT5677_VENDOR_ID2:
540		return true;
541	default:
542		return false;
543	}
544}
545
546/**
547 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
548 * @rt5677: Private Data.
549 * @addr: Address index.
550 * @value: Address data.
551 *
552 *
553 * Returns 0 for success or negative error code.
554 */
555static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677,
556		unsigned int addr, unsigned int value, unsigned int opcode)
557{
558	struct snd_soc_codec *codec = rt5677->codec;
559	int ret;
560
561	mutex_lock(&rt5677->dsp_cmd_lock);
562
563	ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
564		addr >> 16);
565	if (ret < 0) {
566		dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
567		goto err;
568	}
569
570	ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
571		addr & 0xffff);
572	if (ret < 0) {
573		dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
574		goto err;
575	}
576
577	ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
578		value >> 16);
579	if (ret < 0) {
580		dev_err(codec->dev, "Failed to set data msb value: %d\n", ret);
581		goto err;
582	}
583
584	ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
585		value & 0xffff);
586	if (ret < 0) {
587		dev_err(codec->dev, "Failed to set data lsb value: %d\n", ret);
588		goto err;
589	}
590
591	ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
592		opcode);
593	if (ret < 0) {
594		dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
595		goto err;
596	}
597
598err:
599	mutex_unlock(&rt5677->dsp_cmd_lock);
600
601	return ret;
602}
603
604/**
605 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
606 * rt5677: Private Data.
607 * @addr: Address index.
608 * @value: Address data.
609 *
610 *
611 * Returns 0 for success or negative error code.
612 */
613static int rt5677_dsp_mode_i2c_read_addr(
614	struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value)
615{
616	struct snd_soc_codec *codec = rt5677->codec;
617	int ret;
618	unsigned int msb, lsb;
619
620	mutex_lock(&rt5677->dsp_cmd_lock);
621
622	ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
623		addr >> 16);
624	if (ret < 0) {
625		dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
626		goto err;
627	}
628
629	ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
630		addr & 0xffff);
631	if (ret < 0) {
632		dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
633		goto err;
634	}
635
636	ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
637		0x0002);
638	if (ret < 0) {
639		dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
640		goto err;
641	}
642
643	regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
644	regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
645	*value = (msb << 16) | lsb;
646
647err:
648	mutex_unlock(&rt5677->dsp_cmd_lock);
649
650	return ret;
651}
652
653/**
654 * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
655 * rt5677: Private Data.
656 * @reg: Register index.
657 * @value: Register data.
658 *
659 *
660 * Returns 0 for success or negative error code.
661 */
662static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677,
663		unsigned int reg, unsigned int value)
664{
665	return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2,
666		value, 0x0001);
667}
668
669/**
670 * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
671 * @codec: SoC audio codec device.
672 * @reg: Register index.
673 * @value: Register data.
674 *
675 *
676 * Returns 0 for success or negative error code.
677 */
678static int rt5677_dsp_mode_i2c_read(
679	struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value)
680{
681	int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2,
682		value);
683
684	*value &= 0xffff;
685
686	return ret;
687}
688
689static void rt5677_set_dsp_mode(struct snd_soc_codec *codec, bool on)
690{
691	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
692
693	if (on) {
694		regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x2);
695		rt5677->is_dsp_mode = true;
696	} else {
697		regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x0);
698		rt5677->is_dsp_mode = false;
699	}
700}
701
702static int rt5677_set_dsp_vad(struct snd_soc_codec *codec, bool on)
703{
704	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
705	static bool activity;
706	int ret;
707
708	if (!IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI))
709		return -ENXIO;
710
711	if (on && !activity) {
712		activity = true;
713
714		regcache_cache_only(rt5677->regmap, false);
715		regcache_cache_bypass(rt5677->regmap, true);
716
717		regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1);
718		regmap_update_bits(rt5677->regmap,
719			RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00);
720		regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
721			RT5677_LDO1_SEL_MASK, 0x0);
722		regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
723			RT5677_PWR_LDO1, RT5677_PWR_LDO1);
724		switch (rt5677->type) {
725		case RT5677:
726			regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
727				RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC);
728			regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
729				RT5677_PLL2_PR_SRC_MASK |
730				RT5677_DSP_CLK_SRC_MASK,
731				RT5677_PLL2_PR_SRC_MCLK2 |
732				RT5677_DSP_CLK_SRC_BYPASS);
733			break;
734		case RT5676:
735			regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
736				RT5677_DSP_CLK_SRC_MASK,
737				RT5677_DSP_CLK_SRC_BYPASS);
738			break;
739		default:
740			break;
741		}
742		regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff);
743		regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd);
744		rt5677_set_dsp_mode(codec, true);
745
746		ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1,
747			codec->dev);
748		if (ret == 0) {
749			rt5677_spi_burst_write(0x50000000, rt5677->fw1);
750			release_firmware(rt5677->fw1);
751		}
752
753		ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2,
754			codec->dev);
755		if (ret == 0) {
756			rt5677_spi_burst_write(0x60000000, rt5677->fw2);
757			release_firmware(rt5677->fw2);
758		}
759
760		regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0);
761
762		regcache_cache_bypass(rt5677->regmap, false);
763		regcache_cache_only(rt5677->regmap, true);
764	} else if (!on && activity) {
765		activity = false;
766
767		regcache_cache_only(rt5677->regmap, false);
768		regcache_cache_bypass(rt5677->regmap, true);
769
770		regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1);
771		rt5677_set_dsp_mode(codec, false);
772		regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001);
773
774		regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
775
776		regcache_cache_bypass(rt5677->regmap, false);
777		regcache_mark_dirty(rt5677->regmap);
778		regcache_sync(rt5677->regmap);
779	}
780
781	return 0;
782}
783
784static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
785static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
786static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
787static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
788static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
789static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
790
791/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
792static unsigned int bst_tlv[] = {
793	TLV_DB_RANGE_HEAD(7),
794	0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
795	1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
796	2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
797	3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
798	6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
799	7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
800	8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
801};
802
803static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
804		struct snd_ctl_elem_value *ucontrol)
805{
806	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
807	struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
808
809	ucontrol->value.integer.value[0] = rt5677->dsp_vad_en;
810
811	return 0;
812}
813
814static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
815		struct snd_ctl_elem_value *ucontrol)
816{
817	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
818	struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
819	struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
820
821	rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0];
822
823	if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
824		rt5677_set_dsp_vad(codec, rt5677->dsp_vad_en);
825
826	return 0;
827}
828
829static const struct snd_kcontrol_new rt5677_snd_controls[] = {
830	/* OUTPUT Control */
831	SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
832		RT5677_LOUT1_L_MUTE_SFT, 1, 1),
833	SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
834		RT5677_LOUT2_L_MUTE_SFT, 1, 1),
835	SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
836		RT5677_LOUT3_L_MUTE_SFT, 1, 1),
837
838	/* DAC Digital Volume */
839	SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
840		RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
841	SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
842		RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
843	SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
844		RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
845	SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
846		RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
847
848	/* IN1/IN2 Control */
849	SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
850	SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
851
852	/* ADC Digital Volume Control */
853	SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
854		RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
855	SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
856		RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
857	SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
858		RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
859	SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
860		RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
861	SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
862		RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
863
864	SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
865		RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
866		adc_vol_tlv),
867	SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
868		RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
869		adc_vol_tlv),
870	SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
871		RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
872		adc_vol_tlv),
873	SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
874		RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
875		adc_vol_tlv),
876	SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
877		RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0,
878		adc_vol_tlv),
879
880	/* Sidetone Control */
881	SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL,
882		RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv),
883
884	/* ADC Boost Volume Control */
885	SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
886		RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
887		adc_bst_tlv),
888	SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
889		RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
890		adc_bst_tlv),
891	SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
892		RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
893		adc_bst_tlv),
894	SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
895		RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
896		adc_bst_tlv),
897	SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
898		RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
899		adc_bst_tlv),
900
901	SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0,
902		rt5677_dsp_vad_get, rt5677_dsp_vad_put),
903};
904
905/**
906 * set_dmic_clk - Set parameter of dmic.
907 *
908 * @w: DAPM widget.
909 * @kcontrol: The kcontrol of this widget.
910 * @event: Event id.
911 *
912 * Choose dmic clock between 1MHz and 3MHz.
913 * It is better for clock to approximate 3MHz.
914 */
915static int set_dmic_clk(struct snd_soc_dapm_widget *w,
916	struct snd_kcontrol *kcontrol, int event)
917{
918	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
919	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
920	int idx = rl6231_calc_dmic_clk(rt5677->lrck[RT5677_AIF1] << 8);
921
922	if (idx < 0)
923		dev_err(codec->dev, "Failed to set DMIC clock\n");
924	else
925		regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
926			RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
927	return idx;
928}
929
930static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
931			 struct snd_soc_dapm_widget *sink)
932{
933	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
934	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
935	unsigned int val;
936
937	regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
938	val &= RT5677_SCLK_SRC_MASK;
939	if (val == RT5677_SCLK_SRC_PLL1)
940		return 1;
941	else
942		return 0;
943}
944
945static int is_using_asrc(struct snd_soc_dapm_widget *source,
946			 struct snd_soc_dapm_widget *sink)
947{
948	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
949	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
950	unsigned int reg, shift, val;
951
952	if (source->reg == RT5677_ASRC_1) {
953		switch (source->shift) {
954		case 12:
955			reg = RT5677_ASRC_4;
956			shift = 0;
957			break;
958		case 13:
959			reg = RT5677_ASRC_4;
960			shift = 4;
961			break;
962		case 14:
963			reg = RT5677_ASRC_4;
964			shift = 8;
965			break;
966		case 15:
967			reg = RT5677_ASRC_4;
968			shift = 12;
969			break;
970		default:
971			return 0;
972		}
973	} else {
974		switch (source->shift) {
975		case 0:
976			reg = RT5677_ASRC_6;
977			shift = 8;
978			break;
979		case 1:
980			reg = RT5677_ASRC_6;
981			shift = 12;
982			break;
983		case 2:
984			reg = RT5677_ASRC_5;
985			shift = 0;
986			break;
987		case 3:
988			reg = RT5677_ASRC_5;
989			shift = 4;
990			break;
991		case 4:
992			reg = RT5677_ASRC_5;
993			shift = 8;
994			break;
995		case 5:
996			reg = RT5677_ASRC_5;
997			shift = 12;
998			break;
999		case 12:
1000			reg = RT5677_ASRC_3;
1001			shift = 0;
1002			break;
1003		case 13:
1004			reg = RT5677_ASRC_3;
1005			shift = 4;
1006			break;
1007		case 14:
1008			reg = RT5677_ASRC_3;
1009			shift = 12;
1010			break;
1011		default:
1012			return 0;
1013		}
1014	}
1015
1016	regmap_read(rt5677->regmap, reg, &val);
1017	val = (val >> shift) & 0xf;
1018
1019	switch (val) {
1020	case 1 ... 6:
1021		return 1;
1022	default:
1023		return 0;
1024	}
1025
1026}
1027
1028static int can_use_asrc(struct snd_soc_dapm_widget *source,
1029			 struct snd_soc_dapm_widget *sink)
1030{
1031	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1032	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1033
1034	if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384)
1035		return 1;
1036
1037	return 0;
1038}
1039
1040/**
1041 * rt5677_sel_asrc_clk_src - select ASRC clock source for a set of filters
1042 * @codec: SoC audio codec device.
1043 * @filter_mask: mask of filters.
1044 * @clk_src: clock source
1045 *
1046 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5677 can
1047 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1048 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1049 * ASRC function will track i2s clock and generate a corresponding system clock
1050 * for codec. This function provides an API to select the clock source for a
1051 * set of filters specified by the mask. And the codec driver will turn on ASRC
1052 * for these filters if ASRC is selected as their clock source.
1053 */
1054int rt5677_sel_asrc_clk_src(struct snd_soc_codec *codec,
1055		unsigned int filter_mask, unsigned int clk_src)
1056{
1057	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1058	unsigned int asrc3_mask = 0, asrc3_value = 0;
1059	unsigned int asrc4_mask = 0, asrc4_value = 0;
1060	unsigned int asrc5_mask = 0, asrc5_value = 0;
1061	unsigned int asrc6_mask = 0, asrc6_value = 0;
1062	unsigned int asrc7_mask = 0, asrc7_value = 0;
1063
1064	switch (clk_src) {
1065	case RT5677_CLK_SEL_SYS:
1066	case RT5677_CLK_SEL_I2S1_ASRC:
1067	case RT5677_CLK_SEL_I2S2_ASRC:
1068	case RT5677_CLK_SEL_I2S3_ASRC:
1069	case RT5677_CLK_SEL_I2S4_ASRC:
1070	case RT5677_CLK_SEL_I2S5_ASRC:
1071	case RT5677_CLK_SEL_I2S6_ASRC:
1072	case RT5677_CLK_SEL_SYS2:
1073	case RT5677_CLK_SEL_SYS3:
1074	case RT5677_CLK_SEL_SYS4:
1075	case RT5677_CLK_SEL_SYS5:
1076	case RT5677_CLK_SEL_SYS6:
1077	case RT5677_CLK_SEL_SYS7:
1078		break;
1079
1080	default:
1081		return -EINVAL;
1082	}
1083
1084	/* ASRC 3 */
1085	if (filter_mask & RT5677_DA_STEREO_FILTER) {
1086		asrc3_mask |= RT5677_DA_STO_CLK_SEL_MASK;
1087		asrc3_value = (asrc3_value & ~RT5677_DA_STO_CLK_SEL_MASK)
1088			| (clk_src << RT5677_DA_STO_CLK_SEL_SFT);
1089	}
1090
1091	if (filter_mask & RT5677_DA_MONO2_L_FILTER) {
1092		asrc3_mask |= RT5677_DA_MONO2L_CLK_SEL_MASK;
1093		asrc3_value = (asrc3_value & ~RT5677_DA_MONO2L_CLK_SEL_MASK)
1094			| (clk_src << RT5677_DA_MONO2L_CLK_SEL_SFT);
1095	}
1096
1097	if (filter_mask & RT5677_DA_MONO2_R_FILTER) {
1098		asrc3_mask |= RT5677_DA_MONO2R_CLK_SEL_MASK;
1099		asrc3_value = (asrc3_value & ~RT5677_DA_MONO2R_CLK_SEL_MASK)
1100			| (clk_src << RT5677_DA_MONO2R_CLK_SEL_SFT);
1101	}
1102
1103	if (asrc3_mask)
1104		regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask,
1105			asrc3_value);
1106
1107	/* ASRC 4 */
1108	if (filter_mask & RT5677_DA_MONO3_L_FILTER) {
1109		asrc4_mask |= RT5677_DA_MONO3L_CLK_SEL_MASK;
1110		asrc4_value = (asrc4_value & ~RT5677_DA_MONO3L_CLK_SEL_MASK)
1111			| (clk_src << RT5677_DA_MONO3L_CLK_SEL_SFT);
1112	}
1113
1114	if (filter_mask & RT5677_DA_MONO3_R_FILTER) {
1115		asrc4_mask |= RT5677_DA_MONO3R_CLK_SEL_MASK;
1116		asrc4_value = (asrc4_value & ~RT5677_DA_MONO3R_CLK_SEL_MASK)
1117			| (clk_src << RT5677_DA_MONO3R_CLK_SEL_SFT);
1118	}
1119
1120	if (filter_mask & RT5677_DA_MONO4_L_FILTER) {
1121		asrc4_mask |= RT5677_DA_MONO4L_CLK_SEL_MASK;
1122		asrc4_value = (asrc4_value & ~RT5677_DA_MONO4L_CLK_SEL_MASK)
1123			| (clk_src << RT5677_DA_MONO4L_CLK_SEL_SFT);
1124	}
1125
1126	if (filter_mask & RT5677_DA_MONO4_R_FILTER) {
1127		asrc4_mask |= RT5677_DA_MONO4R_CLK_SEL_MASK;
1128		asrc4_value = (asrc4_value & ~RT5677_DA_MONO4R_CLK_SEL_MASK)
1129			| (clk_src << RT5677_DA_MONO4R_CLK_SEL_SFT);
1130	}
1131
1132	if (asrc4_mask)
1133		regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask,
1134			asrc4_value);
1135
1136	/* ASRC 5 */
1137	if (filter_mask & RT5677_AD_STEREO1_FILTER) {
1138		asrc5_mask |= RT5677_AD_STO1_CLK_SEL_MASK;
1139		asrc5_value = (asrc5_value & ~RT5677_AD_STO1_CLK_SEL_MASK)
1140			| (clk_src << RT5677_AD_STO1_CLK_SEL_SFT);
1141	}
1142
1143	if (filter_mask & RT5677_AD_STEREO2_FILTER) {
1144		asrc5_mask |= RT5677_AD_STO2_CLK_SEL_MASK;
1145		asrc5_value = (asrc5_value & ~RT5677_AD_STO2_CLK_SEL_MASK)
1146			| (clk_src << RT5677_AD_STO2_CLK_SEL_SFT);
1147	}
1148
1149	if (filter_mask & RT5677_AD_STEREO3_FILTER) {
1150		asrc5_mask |= RT5677_AD_STO3_CLK_SEL_MASK;
1151		asrc5_value = (asrc5_value & ~RT5677_AD_STO3_CLK_SEL_MASK)
1152			| (clk_src << RT5677_AD_STO3_CLK_SEL_SFT);
1153	}
1154
1155	if (filter_mask & RT5677_AD_STEREO4_FILTER) {
1156		asrc5_mask |= RT5677_AD_STO4_CLK_SEL_MASK;
1157		asrc5_value = (asrc5_value & ~RT5677_AD_STO4_CLK_SEL_MASK)
1158			| (clk_src << RT5677_AD_STO4_CLK_SEL_SFT);
1159	}
1160
1161	if (asrc5_mask)
1162		regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask,
1163			asrc5_value);
1164
1165	/* ASRC 6 */
1166	if (filter_mask & RT5677_AD_MONO_L_FILTER) {
1167		asrc6_mask |= RT5677_AD_MONOL_CLK_SEL_MASK;
1168		asrc6_value = (asrc6_value & ~RT5677_AD_MONOL_CLK_SEL_MASK)
1169			| (clk_src << RT5677_AD_MONOL_CLK_SEL_SFT);
1170	}
1171
1172	if (filter_mask & RT5677_AD_MONO_R_FILTER) {
1173		asrc6_mask |= RT5677_AD_MONOR_CLK_SEL_MASK;
1174		asrc6_value = (asrc6_value & ~RT5677_AD_MONOR_CLK_SEL_MASK)
1175			| (clk_src << RT5677_AD_MONOR_CLK_SEL_SFT);
1176	}
1177
1178	if (asrc6_mask)
1179		regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask,
1180			asrc6_value);
1181
1182	/* ASRC 7 */
1183	if (filter_mask & RT5677_DSP_OB_0_3_FILTER) {
1184		asrc7_mask |= RT5677_DSP_OB_0_3_CLK_SEL_MASK;
1185		asrc7_value = (asrc7_value & ~RT5677_DSP_OB_0_3_CLK_SEL_MASK)
1186			| (clk_src << RT5677_DSP_OB_0_3_CLK_SEL_SFT);
1187	}
1188
1189	if (filter_mask & RT5677_DSP_OB_4_7_FILTER) {
1190		asrc7_mask |= RT5677_DSP_OB_4_7_CLK_SEL_MASK;
1191		asrc7_value = (asrc7_value & ~RT5677_DSP_OB_4_7_CLK_SEL_MASK)
1192			| (clk_src << RT5677_DSP_OB_4_7_CLK_SEL_SFT);
1193	}
1194
1195	if (asrc7_mask)
1196		regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask,
1197			asrc7_value);
1198
1199	return 0;
1200}
1201EXPORT_SYMBOL_GPL(rt5677_sel_asrc_clk_src);
1202
1203/* Digital Mixer */
1204static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
1205	SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1206			RT5677_M_STO1_ADC_L1_SFT, 1, 1),
1207	SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1208			RT5677_M_STO1_ADC_L2_SFT, 1, 1),
1209};
1210
1211static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
1212	SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1213			RT5677_M_STO1_ADC_R1_SFT, 1, 1),
1214	SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1215			RT5677_M_STO1_ADC_R2_SFT, 1, 1),
1216};
1217
1218static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
1219	SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1220			RT5677_M_STO2_ADC_L1_SFT, 1, 1),
1221	SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1222			RT5677_M_STO2_ADC_L2_SFT, 1, 1),
1223};
1224
1225static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
1226	SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1227			RT5677_M_STO2_ADC_R1_SFT, 1, 1),
1228	SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1229			RT5677_M_STO2_ADC_R2_SFT, 1, 1),
1230};
1231
1232static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
1233	SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1234			RT5677_M_STO3_ADC_L1_SFT, 1, 1),
1235	SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1236			RT5677_M_STO3_ADC_L2_SFT, 1, 1),
1237};
1238
1239static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
1240	SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1241			RT5677_M_STO3_ADC_R1_SFT, 1, 1),
1242	SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1243			RT5677_M_STO3_ADC_R2_SFT, 1, 1),
1244};
1245
1246static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
1247	SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1248			RT5677_M_STO4_ADC_L1_SFT, 1, 1),
1249	SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1250			RT5677_M_STO4_ADC_L2_SFT, 1, 1),
1251};
1252
1253static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
1254	SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1255			RT5677_M_STO4_ADC_R1_SFT, 1, 1),
1256	SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1257			RT5677_M_STO4_ADC_R2_SFT, 1, 1),
1258};
1259
1260static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
1261	SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1262			RT5677_M_MONO_ADC_L1_SFT, 1, 1),
1263	SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1264			RT5677_M_MONO_ADC_L2_SFT, 1, 1),
1265};
1266
1267static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
1268	SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1269			RT5677_M_MONO_ADC_R1_SFT, 1, 1),
1270	SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1271			RT5677_M_MONO_ADC_R2_SFT, 1, 1),
1272};
1273
1274static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
1275	SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1276			RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
1277	SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1278			RT5677_M_DAC1_L_SFT, 1, 1),
1279};
1280
1281static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
1282	SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1283			RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
1284	SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1285			RT5677_M_DAC1_R_SFT, 1, 1),
1286};
1287
1288static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
1289	SOC_DAPM_SINGLE("ST L Switch", RT5677_STO1_DAC_MIXER,
1290			RT5677_M_ST_DAC1_L_SFT, 1, 1),
1291	SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1292			RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
1293	SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
1294			RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
1295	SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1296			RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
1297};
1298
1299static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
1300	SOC_DAPM_SINGLE("ST R Switch", RT5677_STO1_DAC_MIXER,
1301			RT5677_M_ST_DAC1_R_SFT, 1, 1),
1302	SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1303			RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
1304	SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
1305			RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
1306	SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1307			RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
1308};
1309
1310static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
1311	SOC_DAPM_SINGLE("ST L Switch", RT5677_MONO_DAC_MIXER,
1312			RT5677_M_ST_DAC2_L_SFT, 1, 1),
1313	SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
1314			RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
1315	SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1316			RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
1317	SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1318			RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
1319};
1320
1321static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
1322	SOC_DAPM_SINGLE("ST R Switch", RT5677_MONO_DAC_MIXER,
1323			RT5677_M_ST_DAC2_R_SFT, 1, 1),
1324	SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
1325			RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
1326	SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1327			RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
1328	SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1329			RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
1330};
1331
1332static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
1333	SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
1334			RT5677_M_STO_L_DD1_L_SFT, 1, 1),
1335	SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
1336			RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
1337	SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
1338			RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
1339	SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
1340			RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
1341};
1342
1343static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
1344	SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
1345			RT5677_M_STO_R_DD1_R_SFT, 1, 1),
1346	SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
1347			RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
1348	SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
1349			RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
1350	SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
1351			RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
1352};
1353
1354static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
1355	SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
1356			RT5677_M_STO_L_DD2_L_SFT, 1, 1),
1357	SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
1358			RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
1359	SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
1360			RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
1361	SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
1362			RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
1363};
1364
1365static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
1366	SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
1367			RT5677_M_STO_R_DD2_R_SFT, 1, 1),
1368	SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
1369			RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
1370	SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
1371			RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
1372	SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
1373			RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
1374};
1375
1376static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
1377	SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1378			RT5677_DSP_IB_01_H_SFT, 1, 1),
1379	SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1380			RT5677_DSP_IB_23_H_SFT, 1, 1),
1381	SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1382			RT5677_DSP_IB_45_H_SFT, 1, 1),
1383	SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1384			RT5677_DSP_IB_6_H_SFT, 1, 1),
1385	SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1386			RT5677_DSP_IB_7_H_SFT, 1, 1),
1387	SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1388			RT5677_DSP_IB_8_H_SFT, 1, 1),
1389	SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1390			RT5677_DSP_IB_9_H_SFT, 1, 1),
1391};
1392
1393static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
1394	SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1395			RT5677_DSP_IB_01_L_SFT, 1, 1),
1396	SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1397			RT5677_DSP_IB_23_L_SFT, 1, 1),
1398	SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1399			RT5677_DSP_IB_45_L_SFT, 1, 1),
1400	SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1401			RT5677_DSP_IB_6_L_SFT, 1, 1),
1402	SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1403			RT5677_DSP_IB_7_L_SFT, 1, 1),
1404	SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1405			RT5677_DSP_IB_8_L_SFT, 1, 1),
1406	SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1407			RT5677_DSP_IB_9_L_SFT, 1, 1),
1408};
1409
1410static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
1411	SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1412			RT5677_DSP_IB_01_H_SFT, 1, 1),
1413	SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1414			RT5677_DSP_IB_23_H_SFT, 1, 1),
1415	SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1416			RT5677_DSP_IB_45_H_SFT, 1, 1),
1417	SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1418			RT5677_DSP_IB_6_H_SFT, 1, 1),
1419	SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1420			RT5677_DSP_IB_7_H_SFT, 1, 1),
1421	SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1422			RT5677_DSP_IB_8_H_SFT, 1, 1),
1423	SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1424			RT5677_DSP_IB_9_H_SFT, 1, 1),
1425};
1426
1427static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
1428	SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1429			RT5677_DSP_IB_01_L_SFT, 1, 1),
1430	SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1431			RT5677_DSP_IB_23_L_SFT, 1, 1),
1432	SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1433			RT5677_DSP_IB_45_L_SFT, 1, 1),
1434	SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1435			RT5677_DSP_IB_6_L_SFT, 1, 1),
1436	SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1437			RT5677_DSP_IB_7_L_SFT, 1, 1),
1438	SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1439			RT5677_DSP_IB_8_L_SFT, 1, 1),
1440	SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1441			RT5677_DSP_IB_9_L_SFT, 1, 1),
1442};
1443
1444static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
1445	SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1446			RT5677_DSP_IB_01_H_SFT, 1, 1),
1447	SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1448			RT5677_DSP_IB_23_H_SFT, 1, 1),
1449	SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1450			RT5677_DSP_IB_45_H_SFT, 1, 1),
1451	SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1452			RT5677_DSP_IB_6_H_SFT, 1, 1),
1453	SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1454			RT5677_DSP_IB_7_H_SFT, 1, 1),
1455	SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1456			RT5677_DSP_IB_8_H_SFT, 1, 1),
1457	SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1458			RT5677_DSP_IB_9_H_SFT, 1, 1),
1459};
1460
1461static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
1462	SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1463			RT5677_DSP_IB_01_L_SFT, 1, 1),
1464	SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1465			RT5677_DSP_IB_23_L_SFT, 1, 1),
1466	SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1467			RT5677_DSP_IB_45_L_SFT, 1, 1),
1468	SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1469			RT5677_DSP_IB_6_L_SFT, 1, 1),
1470	SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1471			RT5677_DSP_IB_7_L_SFT, 1, 1),
1472	SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1473			RT5677_DSP_IB_8_L_SFT, 1, 1),
1474	SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1475			RT5677_DSP_IB_9_L_SFT, 1, 1),
1476};
1477
1478
1479/* Mux */
1480/* DAC1 L/R Source */ /* MX-29 [10:8] */
1481static const char * const rt5677_dac1_src[] = {
1482	"IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
1483	"OB 01"
1484};
1485
1486static SOC_ENUM_SINGLE_DECL(
1487	rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1488	RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
1489
1490static const struct snd_kcontrol_new rt5677_dac1_mux =
1491	SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
1492
1493/* ADDA1 L/R Source */ /* MX-29 [1:0] */
1494static const char * const rt5677_adda1_src[] = {
1495	"STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
1496};
1497
1498static SOC_ENUM_SINGLE_DECL(
1499	rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1500	RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
1501
1502static const struct snd_kcontrol_new rt5677_adda1_mux =
1503	SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
1504
1505
1506/*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
1507static const char * const rt5677_dac2l_src[] = {
1508	"IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
1509	"OB 2",
1510};
1511
1512static SOC_ENUM_SINGLE_DECL(
1513	rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
1514	RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
1515
1516static const struct snd_kcontrol_new rt5677_dac2_l_mux =
1517	SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
1518
1519static const char * const rt5677_dac2r_src[] = {
1520	"IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
1521	"OB 3", "Haptic Generator", "VAD ADC"
1522};
1523
1524static SOC_ENUM_SINGLE_DECL(
1525	rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
1526	RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
1527
1528static const struct snd_kcontrol_new rt5677_dac2_r_mux =
1529	SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
1530
1531/*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
1532static const char * const rt5677_dac3l_src[] = {
1533	"IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
1534	"SLB DAC 4", "OB 4"
1535};
1536
1537static SOC_ENUM_SINGLE_DECL(
1538	rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1539	RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1540
1541static const struct snd_kcontrol_new rt5677_dac3_l_mux =
1542	SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
1543
1544static const char * const rt5677_dac3r_src[] = {
1545	"IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
1546	"SLB DAC 5", "OB 5"
1547};
1548
1549static SOC_ENUM_SINGLE_DECL(
1550	rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1551	RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1552
1553static const struct snd_kcontrol_new rt5677_dac3_r_mux =
1554	SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
1555
1556/*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
1557static const char * const rt5677_dac4l_src[] = {
1558	"IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1559	"SLB DAC 6", "OB 6"
1560};
1561
1562static SOC_ENUM_SINGLE_DECL(
1563	rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1564	RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1565
1566static const struct snd_kcontrol_new rt5677_dac4_l_mux =
1567	SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
1568
1569static const char * const rt5677_dac4r_src[] = {
1570	"IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
1571	"SLB DAC 7", "OB 7"
1572};
1573
1574static SOC_ENUM_SINGLE_DECL(
1575	rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1576	RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1577
1578static const struct snd_kcontrol_new rt5677_dac4_r_mux =
1579	SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
1580
1581/* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1582static const char * const rt5677_iob_bypass_src[] = {
1583	"Bypass", "Pass SRC"
1584};
1585
1586static SOC_ENUM_SINGLE_DECL(
1587	rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1588	RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1589
1590static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
1591	SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
1592
1593static SOC_ENUM_SINGLE_DECL(
1594	rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1595	RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1596
1597static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
1598	SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
1599
1600static SOC_ENUM_SINGLE_DECL(
1601	rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1602	RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1603
1604static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
1605	SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
1606
1607static SOC_ENUM_SINGLE_DECL(
1608	rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1609	RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1610
1611static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
1612	SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
1613
1614static SOC_ENUM_SINGLE_DECL(
1615	rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1616	RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1617
1618static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
1619	SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
1620
1621/* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
1622static const char * const rt5677_stereo_adc2_src[] = {
1623	"DD MIX1", "DMIC", "Stereo DAC MIX"
1624};
1625
1626static SOC_ENUM_SINGLE_DECL(
1627	rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
1628	RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1629
1630static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
1631	SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
1632
1633static SOC_ENUM_SINGLE_DECL(
1634	rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1635	RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1636
1637static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
1638	SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
1639
1640static SOC_ENUM_SINGLE_DECL(
1641	rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1642	RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1643
1644static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
1645	SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
1646
1647/* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1648static const char * const rt5677_dmic_src[] = {
1649	"DMIC1", "DMIC2", "DMIC3", "DMIC4"
1650};
1651
1652static SOC_ENUM_SINGLE_DECL(
1653	rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
1654	RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1655
1656static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
1657	SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
1658
1659static SOC_ENUM_SINGLE_DECL(
1660	rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1661	RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1662
1663static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
1664	SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
1665
1666static SOC_ENUM_SINGLE_DECL(
1667	rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1668	RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1669
1670static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
1671	SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
1672
1673static SOC_ENUM_SINGLE_DECL(
1674	rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1675	RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1676
1677static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
1678	SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
1679
1680static SOC_ENUM_SINGLE_DECL(
1681	rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1682	RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1683
1684static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
1685	SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
1686
1687static SOC_ENUM_SINGLE_DECL(
1688	rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1689	RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1690
1691static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
1692	SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
1693
1694/* Stereo2 ADC Source */ /* MX-26 [0] */
1695static const char * const rt5677_stereo2_adc_lr_src[] = {
1696	"L", "LR"
1697};
1698
1699static SOC_ENUM_SINGLE_DECL(
1700	rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
1701	RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1702
1703static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
1704	SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
1705
1706/* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
1707static const char * const rt5677_stereo_adc1_src[] = {
1708	"DD MIX1", "ADC1/2", "Stereo DAC MIX"
1709};
1710
1711static SOC_ENUM_SINGLE_DECL(
1712	rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
1713	RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1714
1715static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
1716	SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
1717
1718static SOC_ENUM_SINGLE_DECL(
1719	rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1720	RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1721
1722static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
1723	SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
1724
1725static SOC_ENUM_SINGLE_DECL(
1726	rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1727	RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1728
1729static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
1730	SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
1731
1732/* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
1733static const char * const rt5677_mono_adc2_l_src[] = {
1734	"DD MIX1L", "DMIC", "MONO DAC MIXL"
1735};
1736
1737static SOC_ENUM_SINGLE_DECL(
1738	rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
1739	RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1740
1741static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
1742	SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
1743
1744/* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
1745static const char * const rt5677_mono_adc1_l_src[] = {
1746	"DD MIX1L", "ADC1", "MONO DAC MIXL"
1747};
1748
1749static SOC_ENUM_SINGLE_DECL(
1750	rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
1751	RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1752
1753static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
1754	SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
1755
1756/* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
1757static const char * const rt5677_mono_adc2_r_src[] = {
1758	"DD MIX1R", "DMIC", "MONO DAC MIXR"
1759};
1760
1761static SOC_ENUM_SINGLE_DECL(
1762	rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
1763	RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1764
1765static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
1766	SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
1767
1768/* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
1769static const char * const rt5677_mono_adc1_r_src[] = {
1770	"DD MIX1R", "ADC2", "MONO DAC MIXR"
1771};
1772
1773static SOC_ENUM_SINGLE_DECL(
1774	rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
1775	RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1776
1777static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
1778	SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
1779
1780/* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1781static const char * const rt5677_stereo4_adc2_src[] = {
1782	"DD MIX1", "DMIC", "DD MIX2"
1783};
1784
1785static SOC_ENUM_SINGLE_DECL(
1786	rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
1787	RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1788
1789static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
1790	SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
1791
1792
1793/* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
1794static const char * const rt5677_stereo4_adc1_src[] = {
1795	"DD MIX1", "ADC1/2", "DD MIX2"
1796};
1797
1798static SOC_ENUM_SINGLE_DECL(
1799	rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
1800	RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1801
1802static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
1803	SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
1804
1805/* InBound0/1 Source */ /* MX-A3 [14:12] */
1806static const char * const rt5677_inbound01_src[] = {
1807	"IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
1808	"VAD ADC/DAC1 FS"
1809};
1810
1811static SOC_ENUM_SINGLE_DECL(
1812	rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
1813	RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
1814
1815static const struct snd_kcontrol_new rt5677_ib01_src_mux =
1816	SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
1817
1818/* InBound2/3 Source */ /* MX-A3 [10:8] */
1819static const char * const rt5677_inbound23_src[] = {
1820	"IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
1821	"DAC1 FS", "IF4 DAC"
1822};
1823
1824static SOC_ENUM_SINGLE_DECL(
1825	rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
1826	RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
1827
1828static const struct snd_kcontrol_new rt5677_ib23_src_mux =
1829	SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
1830
1831/* InBound4/5 Source */ /* MX-A3 [6:4] */
1832static const char * const rt5677_inbound45_src[] = {
1833	"IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
1834	"IF3 DAC"
1835};
1836
1837static SOC_ENUM_SINGLE_DECL(
1838	rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
1839	RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
1840
1841static const struct snd_kcontrol_new rt5677_ib45_src_mux =
1842	SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
1843
1844/* InBound6 Source */ /* MX-A3 [2:0] */
1845static const char * const rt5677_inbound6_src[] = {
1846	"IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
1847	"IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
1848};
1849
1850static SOC_ENUM_SINGLE_DECL(
1851	rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
1852	RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
1853
1854static const struct snd_kcontrol_new rt5677_ib6_src_mux =
1855	SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
1856
1857/* InBound7 Source */ /* MX-A4 [14:12] */
1858static const char * const rt5677_inbound7_src[] = {
1859	"IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
1860	"IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
1861};
1862
1863static SOC_ENUM_SINGLE_DECL(
1864	rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
1865	RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
1866
1867static const struct snd_kcontrol_new rt5677_ib7_src_mux =
1868	SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
1869
1870/* InBound8 Source */ /* MX-A4 [10:8] */
1871static const char * const rt5677_inbound8_src[] = {
1872	"STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
1873	"MONO ADC MIX L", "DACL1 FS"
1874};
1875
1876static SOC_ENUM_SINGLE_DECL(
1877	rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
1878	RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
1879
1880static const struct snd_kcontrol_new rt5677_ib8_src_mux =
1881	SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
1882
1883/* InBound9 Source */ /* MX-A4 [6:4] */
1884static const char * const rt5677_inbound9_src[] = {
1885	"STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
1886	"MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
1887};
1888
1889static SOC_ENUM_SINGLE_DECL(
1890	rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
1891	RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
1892
1893static const struct snd_kcontrol_new rt5677_ib9_src_mux =
1894	SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
1895
1896/* VAD Source */ /* MX-9F [6:4] */
1897static const char * const rt5677_vad_src[] = {
1898	"STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
1899	"STO3 ADC MIX L"
1900};
1901
1902static SOC_ENUM_SINGLE_DECL(
1903	rt5677_vad_enum, RT5677_VAD_CTRL4,
1904	RT5677_VAD_SRC_SFT, rt5677_vad_src);
1905
1906static const struct snd_kcontrol_new rt5677_vad_src_mux =
1907	SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
1908
1909/* Sidetone Source */ /* MX-13 [11:9] */
1910static const char * const rt5677_sidetone_src[] = {
1911	"DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
1912};
1913
1914static SOC_ENUM_SINGLE_DECL(
1915	rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
1916	RT5677_ST_SEL_SFT, rt5677_sidetone_src);
1917
1918static const struct snd_kcontrol_new rt5677_sidetone_mux =
1919	SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
1920
1921/* DAC1/2 Source */ /* MX-15 [1:0] */
1922static const char * const rt5677_dac12_src[] = {
1923	"STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1924};
1925
1926static SOC_ENUM_SINGLE_DECL(
1927	rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
1928	RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
1929
1930static const struct snd_kcontrol_new rt5677_dac12_mux =
1931	SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
1932
1933/* DAC3 Source */ /* MX-15 [5:4] */
1934static const char * const rt5677_dac3_src[] = {
1935	"MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
1936};
1937
1938static SOC_ENUM_SINGLE_DECL(
1939	rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
1940	RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
1941
1942static const struct snd_kcontrol_new rt5677_dac3_mux =
1943	SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
1944
1945/* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
1946static const char * const rt5677_pdm_src[] = {
1947	"STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1948};
1949
1950static SOC_ENUM_SINGLE_DECL(
1951	rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
1952	RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
1953
1954static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
1955	SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
1956
1957static SOC_ENUM_SINGLE_DECL(
1958	rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
1959	RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
1960
1961static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
1962	SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
1963
1964static SOC_ENUM_SINGLE_DECL(
1965	rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
1966	RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
1967
1968static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
1969	SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
1970
1971static SOC_ENUM_SINGLE_DECL(
1972	rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
1973	RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
1974
1975static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
1976	SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
1977
1978/* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
1979static const char * const rt5677_if12_adc1_src[] = {
1980	"STO1 ADC MIX", "OB01", "VAD ADC"
1981};
1982
1983static SOC_ENUM_SINGLE_DECL(
1984	rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
1985	RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
1986
1987static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
1988	SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
1989
1990static SOC_ENUM_SINGLE_DECL(
1991	rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
1992	RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
1993
1994static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
1995	SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
1996
1997static SOC_ENUM_SINGLE_DECL(
1998	rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
1999	RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
2000
2001static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
2002	SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
2003
2004/* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
2005static const char * const rt5677_if12_adc2_src[] = {
2006	"STO2 ADC MIX", "OB23"
2007};
2008
2009static SOC_ENUM_SINGLE_DECL(
2010	rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
2011	RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
2012
2013static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
2014	SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
2015
2016static SOC_ENUM_SINGLE_DECL(
2017	rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
2018	RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
2019
2020static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
2021	SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
2022
2023static SOC_ENUM_SINGLE_DECL(
2024	rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
2025	RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
2026
2027static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
2028	SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
2029
2030/* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
2031static const char * const rt5677_if12_adc3_src[] = {
2032	"STO3 ADC MIX", "MONO ADC MIX", "OB45"
2033};
2034
2035static SOC_ENUM_SINGLE_DECL(
2036	rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
2037	RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
2038
2039static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
2040	SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
2041
2042static SOC_ENUM_SINGLE_DECL(
2043	rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
2044	RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
2045
2046static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
2047	SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
2048
2049static SOC_ENUM_SINGLE_DECL(
2050	rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
2051	RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
2052
2053static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
2054	SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
2055
2056/* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
2057static const char * const rt5677_if12_adc4_src[] = {
2058	"STO4 ADC MIX", "OB67", "OB01"
2059};
2060
2061static SOC_ENUM_SINGLE_DECL(
2062	rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
2063	RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
2064
2065static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
2066	SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
2067
2068static SOC_ENUM_SINGLE_DECL(
2069	rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
2070	RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
2071
2072static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
2073	SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
2074
2075static SOC_ENUM_SINGLE_DECL(
2076	rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
2077	RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
2078
2079static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
2080	SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
2081
2082/* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
2083static const char * const rt5677_if34_adc_src[] = {
2084	"STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
2085	"MONO ADC MIX", "OB01", "OB23", "VAD ADC"
2086};
2087
2088static SOC_ENUM_SINGLE_DECL(
2089	rt5677_if3_adc_enum, RT5677_IF3_DATA,
2090	RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
2091
2092static const struct snd_kcontrol_new rt5677_if3_adc_mux =
2093	SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
2094
2095static SOC_ENUM_SINGLE_DECL(
2096	rt5677_if4_adc_enum, RT5677_IF4_DATA,
2097	RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
2098
2099static const struct snd_kcontrol_new rt5677_if4_adc_mux =
2100	SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
2101
2102/* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
2103static const char * const rt5677_if12_adc_swap_src[] = {
2104	"L/R", "R/L", "L/L", "R/R"
2105};
2106
2107static SOC_ENUM_SINGLE_DECL(
2108	rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1,
2109	RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src);
2110
2111static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux =
2112	SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum);
2113
2114static SOC_ENUM_SINGLE_DECL(
2115	rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1,
2116	RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2117
2118static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux =
2119	SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum);
2120
2121static SOC_ENUM_SINGLE_DECL(
2122	rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1,
2123	RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
2124
2125static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux =
2126	SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum);
2127
2128static SOC_ENUM_SINGLE_DECL(
2129	rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1,
2130	RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
2131
2132static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux =
2133	SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum);
2134
2135static SOC_ENUM_SINGLE_DECL(
2136	rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1,
2137	RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2138
2139static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux =
2140	SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum);
2141
2142static SOC_ENUM_SINGLE_DECL(
2143	rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1,
2144	RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2145
2146static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux =
2147	SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum);
2148
2149static SOC_ENUM_SINGLE_DECL(
2150	rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1,
2151	RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
2152
2153static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux =
2154	SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum);
2155
2156static SOC_ENUM_SINGLE_DECL(
2157	rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1,
2158	RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
2159
2160static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux =
2161	SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum);
2162
2163/* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
2164static const char * const rt5677_if1_adc_tdm_swap_src[] = {
2165	"1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2166	"3/1/2/4", "3/4/1/2"
2167};
2168
2169static SOC_ENUM_SINGLE_DECL(
2170	rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2,
2171	RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src);
2172
2173static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux =
2174	SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum);
2175
2176/* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
2177static const char * const rt5677_if2_adc_tdm_swap_src[] = {
2178	"1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2179	"2/3/1/4", "3/4/1/2"
2180};
2181
2182static SOC_ENUM_SINGLE_DECL(
2183	rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2,
2184	RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src);
2185
2186static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux =
2187	SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum);
2188
2189/* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0]
2190					MX-3F[14:12][10:8][6:4][2:0]
2191					MX-43[14:12][10:8][6:4][2:0]
2192					MX-44[14:12][10:8][6:4][2:0] */
2193static const char * const rt5677_if12_dac_tdm_sel_src[] = {
2194	"Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
2195};
2196
2197static SOC_ENUM_SINGLE_DECL(
2198	rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4,
2199	RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2200
2201static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux =
2202	SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum);
2203
2204static SOC_ENUM_SINGLE_DECL(
2205	rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4,
2206	RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2207
2208static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux =
2209	SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum);
2210
2211static SOC_ENUM_SINGLE_DECL(
2212	rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4,
2213	RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2214
2215static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux =
2216	SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum);
2217
2218static SOC_ENUM_SINGLE_DECL(
2219	rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4,
2220	RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2221
2222static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux =
2223	SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum);
2224
2225static SOC_ENUM_SINGLE_DECL(
2226	rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5,
2227	RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2228
2229static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux =
2230	SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum);
2231
2232static SOC_ENUM_SINGLE_DECL(
2233	rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5,
2234	RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2235
2236static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux =
2237	SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum);
2238
2239static SOC_ENUM_SINGLE_DECL(
2240	rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5,
2241	RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2242
2243static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux =
2244	SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum);
2245
2246static SOC_ENUM_SINGLE_DECL(
2247	rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5,
2248	RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2249
2250static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux =
2251	SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum);
2252
2253static SOC_ENUM_SINGLE_DECL(
2254	rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4,
2255	RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2256
2257static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux =
2258	SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum);
2259
2260static SOC_ENUM_SINGLE_DECL(
2261	rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4,
2262	RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2263
2264static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux =
2265	SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum);
2266
2267static SOC_ENUM_SINGLE_DECL(
2268	rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4,
2269	RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2270
2271static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux =
2272	SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum);
2273
2274static SOC_ENUM_SINGLE_DECL(
2275	rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4,
2276	RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2277
2278static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux =
2279	SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum);
2280
2281static SOC_ENUM_SINGLE_DECL(
2282	rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5,
2283	RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2284
2285static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux =
2286	SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum);
2287
2288static SOC_ENUM_SINGLE_DECL(
2289	rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5,
2290	RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2291
2292static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux =
2293	SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum);
2294
2295static SOC_ENUM_SINGLE_DECL(
2296	rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5,
2297	RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2298
2299static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux =
2300	SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum);
2301
2302static SOC_ENUM_SINGLE_DECL(
2303	rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5,
2304	RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2305
2306static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux =
2307	SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum);
2308
2309static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
2310	struct snd_kcontrol *kcontrol, int event)
2311{
2312	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2313	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2314
2315	switch (event) {
2316	case SND_SOC_DAPM_POST_PMU:
2317		regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2318			RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
2319		break;
2320
2321	case SND_SOC_DAPM_PRE_PMD:
2322		regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2323			RT5677_PWR_BST1_P, 0);
2324		break;
2325
2326	default:
2327		return 0;
2328	}
2329
2330	return 0;
2331}
2332
2333static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
2334	struct snd_kcontrol *kcontrol, int event)
2335{
2336	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2337	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2338
2339	switch (event) {
2340	case SND_SOC_DAPM_POST_PMU:
2341		regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2342			RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
2343		break;
2344
2345	case SND_SOC_DAPM_PRE_PMD:
2346		regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2347			RT5677_PWR_BST2_P, 0);
2348		break;
2349
2350	default:
2351		return 0;
2352	}
2353
2354	return 0;
2355}
2356
2357static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
2358	struct snd_kcontrol *kcontrol, int event)
2359{
2360	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2361	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2362
2363	switch (event) {
2364	case SND_SOC_DAPM_PRE_PMU:
2365		regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
2366		break;
2367
2368	case SND_SOC_DAPM_POST_PMU:
2369		regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
2370		break;
2371
2372	default:
2373		return 0;
2374	}
2375
2376	return 0;
2377}
2378
2379static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
2380	struct snd_kcontrol *kcontrol, int event)
2381{
2382	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2383	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2384
2385	switch (event) {
2386	case SND_SOC_DAPM_PRE_PMU:
2387		regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
2388		break;
2389
2390	case SND_SOC_DAPM_POST_PMU:
2391		regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
2392		break;
2393
2394	default:
2395		return 0;
2396	}
2397
2398	return 0;
2399}
2400
2401static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
2402	struct snd_kcontrol *kcontrol, int event)
2403{
2404	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2405	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2406
2407	switch (event) {
2408	case SND_SOC_DAPM_POST_PMU:
2409		regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2410			RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2411			RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
2412			RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
2413		break;
2414
2415	case SND_SOC_DAPM_PRE_PMD:
2416		regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2417			RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2418			RT5677_PWR_CLK_MB, 0);
2419		break;
2420
2421	default:
2422		return 0;
2423	}
2424
2425	return 0;
2426}
2427
2428static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w,
2429	struct snd_kcontrol *kcontrol, int event)
2430{
2431	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2432	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2433	unsigned int value;
2434
2435	switch (event) {
2436	case SND_SOC_DAPM_PRE_PMU:
2437		regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
2438		if (value & RT5677_IF1_ADC_CTRL_MASK)
2439			regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
2440				RT5677_IF1_ADC_MODE_MASK,
2441				RT5677_IF1_ADC_MODE_TDM);
2442		break;
2443
2444	default:
2445		return 0;
2446	}
2447
2448	return 0;
2449}
2450
2451static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w,
2452	struct snd_kcontrol *kcontrol, int event)
2453{
2454	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2455	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2456	unsigned int value;
2457
2458	switch (event) {
2459	case SND_SOC_DAPM_PRE_PMU:
2460		regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
2461		if (value & RT5677_IF2_ADC_CTRL_MASK)
2462			regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
2463				RT5677_IF2_ADC_MODE_MASK,
2464				RT5677_IF2_ADC_MODE_TDM);
2465		break;
2466
2467	default:
2468		return 0;
2469	}
2470
2471	return 0;
2472}
2473
2474static int rt5677_vref_event(struct snd_soc_dapm_widget *w,
2475	struct snd_kcontrol *kcontrol, int event)
2476{
2477	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2478	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2479
2480	switch (event) {
2481	case SND_SOC_DAPM_POST_PMU:
2482		if (codec->dapm.bias_level != SND_SOC_BIAS_ON &&
2483			!rt5677->is_vref_slow) {
2484			mdelay(20);
2485			regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
2486				RT5677_PWR_FV1 | RT5677_PWR_FV2,
2487				RT5677_PWR_FV1 | RT5677_PWR_FV2);
2488			rt5677->is_vref_slow = true;
2489		}
2490		break;
2491
2492	default:
2493		return 0;
2494	}
2495
2496	return 0;
2497}
2498
2499static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
2500	SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
2501		0, rt5677_set_pll1_event, SND_SOC_DAPM_PRE_PMU |
2502		SND_SOC_DAPM_POST_PMU),
2503	SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
2504		0, rt5677_set_pll2_event, SND_SOC_DAPM_PRE_PMU |
2505		SND_SOC_DAPM_POST_PMU),
2506
2507	/* ASRC */
2508	SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0),
2509	SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5677_ASRC_1, 1, 0, NULL, 0),
2510	SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5677_ASRC_1, 2, 0, NULL, 0),
2511	SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5677_ASRC_1, 3, 0, NULL, 0),
2512	SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5677_ASRC_2, 14, 0, NULL, 0),
2513	SND_SOC_DAPM_SUPPLY_S("DAC MONO2 L ASRC", 1, RT5677_ASRC_2, 13, 0, NULL,
2514		0),
2515	SND_SOC_DAPM_SUPPLY_S("DAC MONO2 R ASRC", 1, RT5677_ASRC_2, 12, 0, NULL,
2516		0),
2517	SND_SOC_DAPM_SUPPLY_S("DAC MONO3 L ASRC", 1, RT5677_ASRC_1, 15, 0, NULL,
2518		0),
2519	SND_SOC_DAPM_SUPPLY_S("DAC MONO3 R ASRC", 1, RT5677_ASRC_1, 14, 0, NULL,
2520		0),
2521	SND_SOC_DAPM_SUPPLY_S("DAC MONO4 L ASRC", 1, RT5677_ASRC_1, 13, 0, NULL,
2522		0),
2523	SND_SOC_DAPM_SUPPLY_S("DAC MONO4 R ASRC", 1, RT5677_ASRC_1, 12, 0, NULL,
2524		0),
2525	SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL,
2526		0),
2527	SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL,
2528		0),
2529	SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL,
2530		0),
2531	SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL,
2532		0),
2533	SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL,
2534		0),
2535	SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL,
2536		0),
2537	SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5677_ASRC_2, 5, 0, NULL, 0),
2538	SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5677_ASRC_2, 4, 0, NULL, 0),
2539	SND_SOC_DAPM_SUPPLY_S("ADC STO3 ASRC", 1, RT5677_ASRC_2, 3, 0, NULL, 0),
2540	SND_SOC_DAPM_SUPPLY_S("ADC STO4 ASRC", 1, RT5677_ASRC_2, 2, 0, NULL, 0),
2541	SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5677_ASRC_2, 1, 0, NULL,
2542		0),
2543	SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5677_ASRC_2, 0, 0, NULL,
2544		0),
2545
2546	/* Input Side */
2547	/* micbias */
2548	SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
2549		0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
2550		SND_SOC_DAPM_POST_PMU),
2551
2552	/* Input Lines */
2553	SND_SOC_DAPM_INPUT("DMIC L1"),
2554	SND_SOC_DAPM_INPUT("DMIC R1"),
2555	SND_SOC_DAPM_INPUT("DMIC L2"),
2556	SND_SOC_DAPM_INPUT("DMIC R2"),
2557	SND_SOC_DAPM_INPUT("DMIC L3"),
2558	SND_SOC_DAPM_INPUT("DMIC R3"),
2559	SND_SOC_DAPM_INPUT("DMIC L4"),
2560	SND_SOC_DAPM_INPUT("DMIC R4"),
2561
2562	SND_SOC_DAPM_INPUT("IN1P"),
2563	SND_SOC_DAPM_INPUT("IN1N"),
2564	SND_SOC_DAPM_INPUT("IN2P"),
2565	SND_SOC_DAPM_INPUT("IN2N"),
2566
2567	SND_SOC_DAPM_INPUT("Haptic Generator"),
2568
2569	SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2570	SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2571	SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2572	SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2573
2574	SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
2575		RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
2576	SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
2577		RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
2578	SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
2579		RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
2580	SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
2581		RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
2582
2583	SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2584		set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2585
2586	/* Boost */
2587	SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
2588		RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
2589		SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2590	SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
2591		RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
2592		SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2593
2594	/* ADCs */
2595	SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
2596		0, 0),
2597	SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
2598		0, 0),
2599	SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
2600
2601	SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
2602		RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
2603	SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
2604		RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
2605	SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
2606		RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
2607	SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
2608		RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
2609
2610	/* ADC Mux */
2611	SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2612				&rt5677_sto1_dmic_mux),
2613	SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2614				&rt5677_sto1_adc1_mux),
2615	SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2616				&rt5677_sto1_adc2_mux),
2617	SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
2618				&rt5677_sto2_dmic_mux),
2619	SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2620				&rt5677_sto2_adc1_mux),
2621	SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2622				&rt5677_sto2_adc2_mux),
2623	SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
2624				&rt5677_sto2_adc_lr_mux),
2625	SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
2626				&rt5677_sto3_dmic_mux),
2627	SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2628				&rt5677_sto3_adc1_mux),
2629	SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2630				&rt5677_sto3_adc2_mux),
2631	SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
2632				&rt5677_sto4_dmic_mux),
2633	SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2634				&rt5677_sto4_adc1_mux),
2635	SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2636				&rt5677_sto4_adc2_mux),
2637	SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2638				&rt5677_mono_dmic_l_mux),
2639	SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2640				&rt5677_mono_dmic_r_mux),
2641	SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
2642				&rt5677_mono_adc2_l_mux),
2643	SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
2644				&rt5677_mono_adc1_l_mux),
2645	SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
2646				&rt5677_mono_adc1_r_mux),
2647	SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
2648				&rt5677_mono_adc2_r_mux),
2649
2650	/* ADC Mixer */
2651	SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
2652		RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
2653	SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
2654		RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
2655	SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
2656		RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
2657	SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
2658		RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
2659	SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2660		rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
2661	SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2662		rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
2663	SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
2664		rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
2665	SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
2666		rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
2667	SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
2668		rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
2669	SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
2670		rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
2671	SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
2672		rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
2673	SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
2674		rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
2675	SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
2676		RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2677	SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2678		rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
2679	SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
2680		RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2681	SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2682		rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
2683
2684	/* ADC PGA */
2685	SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2686	SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2687	SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2688	SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2689	SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2690	SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2691	SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2692	SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2693	SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2694	SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2695	SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2696	SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2697	SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2698	SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2699	SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2700	SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2701
2702	/* DSP */
2703	SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
2704			&rt5677_ib9_src_mux),
2705	SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
2706			&rt5677_ib8_src_mux),
2707	SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
2708			&rt5677_ib7_src_mux),
2709	SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
2710			&rt5677_ib6_src_mux),
2711	SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
2712			&rt5677_ib45_src_mux),
2713	SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
2714			&rt5677_ib23_src_mux),
2715	SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
2716			&rt5677_ib01_src_mux),
2717	SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
2718			&rt5677_ib45_bypass_src_mux),
2719	SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2720			&rt5677_ib23_bypass_src_mux),
2721	SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2722			&rt5677_ib01_bypass_src_mux),
2723	SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2724			&rt5677_ob23_bypass_src_mux),
2725	SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2726			&rt5677_ob01_bypass_src_mux),
2727
2728	SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
2729	SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
2730
2731	SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
2732	SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
2733	SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
2734	SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
2735	SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
2736	SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
2737
2738	/* Digital Interface */
2739	SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
2740		RT5677_PWR_I2S1_BIT, 0, NULL, 0),
2741	SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2742	SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2743	SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2744	SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2745	SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2746	SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2747	SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2748	SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2749	SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2750	SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2751	SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2752	SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2753	SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2754	SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2755	SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2756	SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2757
2758	SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
2759		RT5677_PWR_I2S2_BIT, 0, NULL, 0),
2760	SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2761	SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2762	SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2763	SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2764	SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2765	SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2766	SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2767	SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2768	SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2769	SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2770	SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2771	SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2772	SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2773	SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2774	SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2775	SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2776
2777	SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
2778		RT5677_PWR_I2S3_BIT, 0, NULL, 0),
2779	SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2780	SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2781	SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2782	SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2783	SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2784	SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2785
2786	SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
2787		RT5677_PWR_I2S4_BIT, 0, NULL, 0),
2788	SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2789	SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2790	SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2791	SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2792	SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2793	SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2794
2795	SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
2796		RT5677_PWR_SLB_BIT, 0, NULL, 0),
2797	SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2798	SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2799	SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2800	SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2801	SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2802	SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2803	SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2804	SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2805	SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2806	SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2807	SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2808	SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2809	SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2810	SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2811	SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2812	SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2813
2814	/* Digital Interface Select */
2815	SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2816			&rt5677_if1_adc1_mux),
2817	SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2818			&rt5677_if1_adc2_mux),
2819	SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2820			&rt5677_if1_adc3_mux),
2821	SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2822			&rt5677_if1_adc4_mux),
2823	SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2824			&rt5677_if1_adc1_swap_mux),
2825	SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2826			&rt5677_if1_adc2_swap_mux),
2827	SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2828			&rt5677_if1_adc3_swap_mux),
2829	SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2830			&rt5677_if1_adc4_swap_mux),
2831	SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2832			&rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event,
2833			SND_SOC_DAPM_PRE_PMU),
2834	SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2835			&rt5677_if2_adc1_mux),
2836	SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2837			&rt5677_if2_adc2_mux),
2838	SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2839			&rt5677_if2_adc3_mux),
2840	SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2841			&rt5677_if2_adc4_mux),
2842	SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2843			&rt5677_if2_adc1_swap_mux),
2844	SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2845			&rt5677_if2_adc2_swap_mux),
2846	SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2847			&rt5677_if2_adc3_swap_mux),
2848	SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2849			&rt5677_if2_adc4_swap_mux),
2850	SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2851			&rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event,
2852			SND_SOC_DAPM_PRE_PMU),
2853	SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2854			&rt5677_if3_adc_mux),
2855	SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
2856			&rt5677_if4_adc_mux),
2857	SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
2858			&rt5677_slb_adc1_mux),
2859	SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
2860			&rt5677_slb_adc2_mux),
2861	SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
2862			&rt5677_slb_adc3_mux),
2863	SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
2864			&rt5677_slb_adc4_mux),
2865
2866	SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2867			&rt5677_if1_dac0_tdm_sel_mux),
2868	SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2869			&rt5677_if1_dac1_tdm_sel_mux),
2870	SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2871			&rt5677_if1_dac2_tdm_sel_mux),
2872	SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2873			&rt5677_if1_dac3_tdm_sel_mux),
2874	SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2875			&rt5677_if1_dac4_tdm_sel_mux),
2876	SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2877			&rt5677_if1_dac5_tdm_sel_mux),
2878	SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2879			&rt5677_if1_dac6_tdm_sel_mux),
2880	SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2881			&rt5677_if1_dac7_tdm_sel_mux),
2882
2883	SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2884			&rt5677_if2_dac0_tdm_sel_mux),
2885	SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2886			&rt5677_if2_dac1_tdm_sel_mux),
2887	SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2888			&rt5677_if2_dac2_tdm_sel_mux),
2889	SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2890			&rt5677_if2_dac3_tdm_sel_mux),
2891	SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2892			&rt5677_if2_dac4_tdm_sel_mux),
2893	SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2894			&rt5677_if2_dac5_tdm_sel_mux),
2895	SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2896			&rt5677_if2_dac6_tdm_sel_mux),
2897	SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2898			&rt5677_if2_dac7_tdm_sel_mux),
2899
2900	/* Audio Interface */
2901	SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2902	SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2903	SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2904	SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2905	SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
2906	SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
2907	SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
2908	SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
2909	SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
2910	SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
2911
2912	/* Sidetone Mux */
2913	SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
2914			&rt5677_sidetone_mux),
2915	SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL,
2916		RT5677_ST_EN_SFT, 0, NULL, 0),
2917
2918	/* VAD Mux*/
2919	SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
2920			&rt5677_vad_src_mux),
2921
2922	/* Tensilica DSP */
2923	SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
2924	SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
2925		rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
2926	SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
2927		rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
2928	SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
2929		rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
2930	SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
2931		rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
2932	SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
2933		rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
2934	SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
2935		rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
2936
2937	/* Output Side */
2938	/* DAC mixer before sound effect */
2939	SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2940		rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
2941	SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
2942		rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
2943	SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
2944
2945	/* DAC Mux */
2946	SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
2947				&rt5677_dac1_mux),
2948	SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
2949				&rt5677_adda1_mux),
2950	SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
2951				&rt5677_dac12_mux),
2952	SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
2953				&rt5677_dac3_mux),
2954
2955	/* DAC2 channel Mux */
2956	SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2957				&rt5677_dac2_l_mux),
2958	SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2959				&rt5677_dac2_r_mux),
2960
2961	/* DAC3 channel Mux */
2962	SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
2963			&rt5677_dac3_l_mux),
2964	SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
2965			&rt5677_dac3_r_mux),
2966
2967	/* DAC4 channel Mux */
2968	SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
2969			&rt5677_dac4_l_mux),
2970	SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
2971			&rt5677_dac4_r_mux),
2972
2973	/* DAC Mixer */
2974	SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
2975		RT5677_PWR_DAC_S1F_BIT, 0, NULL, 0),
2976	SND_SOC_DAPM_SUPPLY("dac mono2 left filter", RT5677_PWR_DIG2,
2977		RT5677_PWR_DAC_M2F_L_BIT, 0, NULL, 0),
2978	SND_SOC_DAPM_SUPPLY("dac mono2 right filter", RT5677_PWR_DIG2,
2979		RT5677_PWR_DAC_M2F_R_BIT, 0, NULL, 0),
2980	SND_SOC_DAPM_SUPPLY("dac mono3 left filter", RT5677_PWR_DIG2,
2981		RT5677_PWR_DAC_M3F_L_BIT, 0, NULL, 0),
2982	SND_SOC_DAPM_SUPPLY("dac mono3 right filter", RT5677_PWR_DIG2,
2983		RT5677_PWR_DAC_M3F_R_BIT, 0, NULL, 0),
2984	SND_SOC_DAPM_SUPPLY("dac mono4 left filter", RT5677_PWR_DIG2,
2985		RT5677_PWR_DAC_M4F_L_BIT, 0, NULL, 0),
2986	SND_SOC_DAPM_SUPPLY("dac mono4 right filter", RT5677_PWR_DIG2,
2987		RT5677_PWR_DAC_M4F_R_BIT, 0, NULL, 0),
2988
2989	SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2990		rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
2991	SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2992		rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
2993	SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2994		rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
2995	SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2996		rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
2997	SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
2998		rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
2999	SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
3000		rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
3001	SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
3002		rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
3003	SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
3004		rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
3005	SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3006	SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3007	SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3008	SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3009
3010	/* DACs */
3011	SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
3012		RT5677_PWR_DAC1_BIT, 0),
3013	SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
3014		RT5677_PWR_DAC2_BIT, 0),
3015	SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
3016		RT5677_PWR_DAC3_BIT, 0),
3017
3018	/* PDM */
3019	SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
3020		RT5677_PWR_PDM1_BIT, 0, NULL, 0),
3021	SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
3022		RT5677_PWR_PDM2_BIT, 0, NULL, 0),
3023
3024	SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
3025		1, &rt5677_pdm1_l_mux),
3026	SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
3027		1, &rt5677_pdm1_r_mux),
3028	SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
3029		1, &rt5677_pdm2_l_mux),
3030	SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
3031		1, &rt5677_pdm2_r_mux),
3032
3033	SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
3034		0, NULL, 0),
3035	SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
3036		0, NULL, 0),
3037	SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
3038		0, NULL, 0),
3039
3040	SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0,
3041		rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3042	SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0,
3043		rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3044	SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0,
3045		rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3046
3047	/* Output Lines */
3048	SND_SOC_DAPM_OUTPUT("LOUT1"),
3049	SND_SOC_DAPM_OUTPUT("LOUT2"),
3050	SND_SOC_DAPM_OUTPUT("LOUT3"),
3051	SND_SOC_DAPM_OUTPUT("PDM1L"),
3052	SND_SOC_DAPM_OUTPUT("PDM1R"),
3053	SND_SOC_DAPM_OUTPUT("PDM2L"),
3054	SND_SOC_DAPM_OUTPUT("PDM2R"),
3055
3056	SND_SOC_DAPM_POST("vref", rt5677_vref_event),
3057};
3058
3059static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
3060	{ "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", can_use_asrc },
3061	{ "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", can_use_asrc },
3062	{ "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", can_use_asrc },
3063	{ "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", can_use_asrc },
3064	{ "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", can_use_asrc },
3065	{ "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", can_use_asrc },
3066	{ "I2S1", NULL, "I2S1 ASRC", can_use_asrc},
3067	{ "I2S2", NULL, "I2S2 ASRC", can_use_asrc},
3068	{ "I2S3", NULL, "I2S3 ASRC", can_use_asrc},
3069	{ "I2S4", NULL, "I2S4 ASRC", can_use_asrc},
3070
3071	{ "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
3072	{ "dac mono2 left filter", NULL, "DAC MONO2 L ASRC", is_using_asrc },
3073	{ "dac mono2 right filter", NULL, "DAC MONO2 R ASRC", is_using_asrc },
3074	{ "dac mono3 left filter", NULL, "DAC MONO3 L ASRC", is_using_asrc },
3075	{ "dac mono3 right filter", NULL, "DAC MONO3 R ASRC", is_using_asrc },
3076	{ "dac mono4 left filter", NULL, "DAC MONO4 L ASRC", is_using_asrc },
3077	{ "dac mono4 right filter", NULL, "DAC MONO4 R ASRC", is_using_asrc },
3078	{ "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
3079	{ "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc },
3080	{ "adc stereo3 filter", NULL, "ADC STO3 ASRC", is_using_asrc },
3081	{ "adc stereo4 filter", NULL, "ADC STO4 ASRC", is_using_asrc },
3082	{ "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
3083	{ "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
3084
3085	{ "DMIC1", NULL, "DMIC L1" },
3086	{ "DMIC1", NULL, "DMIC R1" },
3087	{ "DMIC2", NULL, "DMIC L2" },
3088	{ "DMIC2", NULL, "DMIC R2" },
3089	{ "DMIC3", NULL, "DMIC L3" },
3090	{ "DMIC3", NULL, "DMIC R3" },
3091	{ "DMIC4", NULL, "DMIC L4" },
3092	{ "DMIC4", NULL, "DMIC R4" },
3093
3094	{ "DMIC L1", NULL, "DMIC CLK" },
3095	{ "DMIC R1", NULL, "DMIC CLK" },
3096	{ "DMIC L2", NULL, "DMIC CLK" },
3097	{ "DMIC R2", NULL, "DMIC CLK" },
3098	{ "DMIC L3", NULL, "DMIC CLK" },
3099	{ "DMIC R3", NULL, "DMIC CLK" },
3100	{ "DMIC L4", NULL, "DMIC CLK" },
3101	{ "DMIC R4", NULL, "DMIC CLK" },
3102
3103	{ "DMIC L1", NULL, "DMIC1 power" },
3104	{ "DMIC R1", NULL, "DMIC1 power" },
3105	{ "DMIC L3", NULL, "DMIC3 power" },
3106	{ "DMIC R3", NULL, "DMIC3 power" },
3107	{ "DMIC L4", NULL, "DMIC4 power" },
3108	{ "DMIC R4", NULL, "DMIC4 power" },
3109
3110	{ "BST1", NULL, "IN1P" },
3111	{ "BST1", NULL, "IN1N" },
3112	{ "BST2", NULL, "IN2P" },
3113	{ "BST2", NULL, "IN2N" },
3114
3115	{ "IN1P", NULL, "MICBIAS1" },
3116	{ "IN1N", NULL, "MICBIAS1" },
3117	{ "IN2P", NULL, "MICBIAS1" },
3118	{ "IN2N", NULL, "MICBIAS1" },
3119
3120	{ "ADC 1", NULL, "BST1" },
3121	{ "ADC 1", NULL, "ADC 1 power" },
3122	{ "ADC 1", NULL, "ADC1 clock" },
3123	{ "ADC 2", NULL, "BST2" },
3124	{ "ADC 2", NULL, "ADC 2 power" },
3125	{ "ADC 2", NULL, "ADC2 clock" },
3126
3127	{ "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
3128	{ "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
3129	{ "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
3130	{ "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
3131
3132	{ "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
3133	{ "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
3134	{ "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
3135	{ "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
3136
3137	{ "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
3138	{ "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
3139	{ "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
3140	{ "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
3141
3142	{ "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
3143	{ "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
3144	{ "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
3145	{ "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
3146
3147	{ "Mono DMIC L Mux", "DMIC1", "DMIC1" },
3148	{ "Mono DMIC L Mux", "DMIC2", "DMIC2" },
3149	{ "Mono DMIC L Mux", "DMIC3", "DMIC3" },
3150	{ "Mono DMIC L Mux", "DMIC4", "DMIC4" },
3151
3152	{ "Mono DMIC R Mux", "DMIC1", "DMIC1" },
3153	{ "Mono DMIC R Mux", "DMIC2", "DMIC2" },
3154	{ "Mono DMIC R Mux", "DMIC3", "DMIC3" },
3155	{ "Mono DMIC R Mux", "DMIC4", "DMIC4" },
3156
3157	{ "ADC 1_2", NULL, "ADC 1" },
3158	{ "ADC 1_2", NULL, "ADC 2" },
3159
3160	{ "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3161	{ "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3162	{ "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3163
3164	{ "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3165	{ "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
3166	{ "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3167
3168	{ "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3169	{ "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3170	{ "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3171
3172	{ "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3173	{ "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
3174	{ "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3175
3176	{ "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3177	{ "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3178	{ "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3179
3180	{ "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3181	{ "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3182	{ "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3183
3184	{ "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3185	{ "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3186	{ "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
3187
3188	{ "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3189	{ "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3190	{ "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
3191
3192	{ "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
3193	{ "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
3194	{ "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3195
3196	{ "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
3197	{ "Mono ADC1 L Mux", "ADC1", "ADC 1" },
3198	{ "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3199
3200	{ "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
3201	{ "Mono ADC1 R Mux", "ADC2", "ADC 2" },
3202	{ "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3203
3204	{ "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
3205	{ "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
3206	{ "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3207
3208	{ "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3209	{ "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3210	{ "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3211	{ "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3212
3213	{ "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
3214	{ "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
3215	{ "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
3216	{ "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
3217	{ "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3218
3219	{ "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
3220	{ "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
3221
3222	{ "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3223	{ "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3224	{ "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3225	{ "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3226
3227	{ "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
3228	{ "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
3229
3230	{ "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
3231	{ "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
3232
3233	{ "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
3234	{ "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
3235	{ "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
3236	{ "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
3237	{ "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
3238
3239	{ "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
3240	{ "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
3241
3242	{ "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3243	{ "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3244	{ "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3245	{ "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3246
3247	{ "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
3248	{ "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
3249	{ "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
3250	{ "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
3251	{ "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
3252
3253	{ "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
3254	{ "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
3255
3256	{ "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3257	{ "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3258	{ "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3259	{ "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3260
3261	{ "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
3262	{ "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
3263	{ "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
3264	{ "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
3265	{ "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
3266
3267	{ "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
3268	{ "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
3269
3270	{ "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
3271	{ "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
3272	{ "Mono ADC MIXL", NULL, "adc mono left filter" },
3273	{ "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
3274
3275	{ "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
3276	{ "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
3277	{ "Mono ADC MIXR", NULL, "adc mono right filter" },
3278	{ "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
3279
3280	{ "Mono ADC MIX", NULL, "Mono ADC MIXL" },
3281	{ "Mono ADC MIX", NULL, "Mono ADC MIXR" },
3282
3283	{ "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3284	{ "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3285	{ "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3286	{ "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3287	{ "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3288
3289	{ "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3290	{ "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3291	{ "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3292
3293	{ "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3294	{ "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3295
3296	{ "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3297	{ "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3298	{ "IF1 ADC3 Mux", "OB45", "OB45" },
3299
3300	{ "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3301	{ "IF1 ADC4 Mux", "OB67", "OB67" },
3302	{ "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3303
3304	{ "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" },
3305	{ "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" },
3306	{ "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" },
3307	{ "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" },
3308
3309	{ "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" },
3310	{ "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" },
3311	{ "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" },
3312	{ "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" },
3313
3314	{ "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" },
3315	{ "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" },
3316	{ "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" },
3317	{ "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" },
3318
3319	{ "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" },
3320	{ "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" },
3321	{ "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" },
3322	{ "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" },
3323
3324	{ "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" },
3325	{ "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" },
3326	{ "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" },
3327	{ "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" },
3328
3329	{ "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" },
3330	{ "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" },
3331	{ "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" },
3332	{ "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" },
3333	{ "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" },
3334	{ "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" },
3335	{ "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" },
3336	{ "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" },
3337
3338	{ "AIF1TX", NULL, "I2S1" },
3339	{ "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" },
3340
3341	{ "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3342	{ "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3343	{ "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3344
3345	{ "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3346	{ "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3347
3348	{ "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3349	{ "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3350	{ "IF2 ADC3 Mux", "OB45", "OB45" },
3351
3352	{ "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3353	{ "IF2 ADC4 Mux", "OB67", "OB67" },
3354	{ "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3355
3356	{ "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" },
3357	{ "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" },
3358	{ "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" },
3359	{ "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" },
3360
3361	{ "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" },
3362	{ "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" },
3363	{ "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" },
3364	{ "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" },
3365
3366	{ "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" },
3367	{ "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" },
3368	{ "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" },
3369	{ "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" },
3370
3371	{ "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" },
3372	{ "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" },
3373	{ "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" },
3374	{ "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" },
3375
3376	{ "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" },
3377	{ "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" },
3378	{ "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" },
3379	{ "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" },
3380
3381	{ "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" },
3382	{ "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" },
3383	{ "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" },
3384	{ "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" },
3385	{ "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" },
3386	{ "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" },
3387	{ "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" },
3388	{ "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" },
3389
3390	{ "AIF2TX", NULL, "I2S2" },
3391	{ "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" },
3392
3393	{ "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3394	{ "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3395	{ "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3396	{ "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3397	{ "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3398	{ "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
3399	{ "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
3400	{ "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3401
3402	{ "AIF3TX", NULL, "I2S3" },
3403	{ "AIF3TX", NULL, "IF3 ADC Mux" },
3404
3405	{ "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3406	{ "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3407	{ "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3408	{ "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3409	{ "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3410	{ "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
3411	{ "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
3412	{ "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3413
3414	{ "AIF4TX", NULL, "I2S4" },
3415	{ "AIF4TX", NULL, "IF4 ADC Mux" },
3416
3417	{ "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3418	{ "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3419	{ "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3420
3421	{ "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3422	{ "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3423
3424	{ "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3425	{ "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3426	{ "SLB ADC3 Mux", "OB45", "OB45" },
3427
3428	{ "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3429	{ "SLB ADC4 Mux", "OB67", "OB67" },
3430	{ "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3431
3432	{ "SLBTX", NULL, "SLB" },
3433	{ "SLBTX", NULL, "SLB ADC1 Mux" },
3434	{ "SLBTX", NULL, "SLB ADC2 Mux" },
3435	{ "SLBTX", NULL, "SLB ADC3 Mux" },
3436	{ "SLBTX", NULL, "SLB ADC4 Mux" },
3437
3438	{ "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
3439	{ "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
3440	{ "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
3441	{ "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3442	{ "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
3443
3444	{ "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
3445	{ "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
3446
3447	{ "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
3448	{ "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
3449	{ "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
3450	{ "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3451	{ "IB23 Mux", "DAC1 FS", "DAC1 FS" },
3452	{ "IB23 Mux", "IF4 DAC", "IF4 DAC" },
3453
3454	{ "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
3455	{ "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
3456
3457	{ "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
3458	{ "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
3459	{ "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
3460	{ "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3461	{ "IB45 Mux", "IF3 DAC", "IF3 DAC" },
3462
3463	{ "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
3464	{ "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
3465
3466	{ "IB6 Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3467	{ "IB6 Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
3468	{ "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
3469	{ "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3470	{ "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
3471	{ "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3472	{ "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3473	{ "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3474
3475	{ "IB7 Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3476	{ "IB7 Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
3477	{ "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
3478	{ "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3479	{ "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
3480	{ "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3481	{ "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3482	{ "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3483
3484	{ "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3485	{ "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3486	{ "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3487	{ "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3488	{ "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3489	{ "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
3490
3491	{ "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3492	{ "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3493	{ "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3494	{ "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3495	{ "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3496	{ "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
3497	{ "IB9 Mux", "DAC1 FS", "DAC1 FS" },
3498
3499	{ "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3500	{ "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3501	{ "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3502	{ "OB01 MIX", "IB6 Switch", "IB6 Mux" },
3503	{ "OB01 MIX", "IB7 Switch", "IB7 Mux" },
3504	{ "OB01 MIX", "IB8 Switch", "IB8 Mux" },
3505	{ "OB01 MIX", "IB9 Switch", "IB9 Mux" },
3506
3507	{ "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3508	{ "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3509	{ "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3510	{ "OB23 MIX", "IB6 Switch", "IB6 Mux" },
3511	{ "OB23 MIX", "IB7 Switch", "IB7 Mux" },
3512	{ "OB23 MIX", "IB8 Switch", "IB8 Mux" },
3513	{ "OB23 MIX", "IB9 Switch", "IB9 Mux" },
3514
3515	{ "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3516	{ "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3517	{ "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3518	{ "OB4 MIX", "IB6 Switch", "IB6 Mux" },
3519	{ "OB4 MIX", "IB7 Switch", "IB7 Mux" },
3520	{ "OB4 MIX", "IB8 Switch", "IB8 Mux" },
3521	{ "OB4 MIX", "IB9 Switch", "IB9 Mux" },
3522
3523	{ "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3524	{ "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3525	{ "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3526	{ "OB5 MIX", "IB6 Switch", "IB6 Mux" },
3527	{ "OB5 MIX", "IB7 Switch", "IB7 Mux" },
3528	{ "OB5 MIX", "IB8 Switch", "IB8 Mux" },
3529	{ "OB5 MIX", "IB9 Switch", "IB9 Mux" },
3530
3531	{ "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3532	{ "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3533	{ "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3534	{ "OB6 MIX", "IB6 Switch", "IB6 Mux" },
3535	{ "OB6 MIX", "IB7 Switch", "IB7 Mux" },
3536	{ "OB6 MIX", "IB8 Switch", "IB8 Mux" },
3537	{ "OB6 MIX", "IB9 Switch", "IB9 Mux" },
3538
3539	{ "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3540	{ "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3541	{ "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3542	{ "OB7 MIX", "IB6 Switch", "IB6 Mux" },
3543	{ "OB7 MIX", "IB7 Switch", "IB7 Mux" },
3544	{ "OB7 MIX", "IB8 Switch", "IB8 Mux" },
3545	{ "OB7 MIX", "IB9 Switch", "IB9 Mux" },
3546
3547	{ "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
3548	{ "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
3549	{ "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
3550	{ "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
3551
3552	{ "OutBound2", NULL, "OB23 Bypass Mux" },
3553	{ "OutBound3", NULL, "OB23 Bypass Mux" },
3554	{ "OutBound4", NULL, "OB4 MIX" },
3555	{ "OutBound5", NULL, "OB5 MIX" },
3556	{ "OutBound6", NULL, "OB6 MIX" },
3557	{ "OutBound7", NULL, "OB7 MIX" },
3558
3559	{ "OB45", NULL, "OutBound4" },
3560	{ "OB45", NULL, "OutBound5" },
3561	{ "OB67", NULL, "OutBound6" },
3562	{ "OB67", NULL, "OutBound7" },
3563
3564	{ "IF1 DAC0", NULL, "AIF1RX" },
3565	{ "IF1 DAC1", NULL, "AIF1RX" },
3566	{ "IF1 DAC2", NULL, "AIF1RX" },
3567	{ "IF1 DAC3", NULL, "AIF1RX" },
3568	{ "IF1 DAC4", NULL, "AIF1RX" },
3569	{ "IF1 DAC5", NULL, "AIF1RX" },
3570	{ "IF1 DAC6", NULL, "AIF1RX" },
3571	{ "IF1 DAC7", NULL, "AIF1RX" },
3572	{ "IF1 DAC0", NULL, "I2S1" },
3573	{ "IF1 DAC1", NULL, "I2S1" },
3574	{ "IF1 DAC2", NULL, "I2S1" },
3575	{ "IF1 DAC3", NULL, "I2S1" },
3576	{ "IF1 DAC4", NULL, "I2S1" },
3577	{ "IF1 DAC5", NULL, "I2S1" },
3578	{ "IF1 DAC6", NULL, "I2S1" },
3579	{ "IF1 DAC7", NULL, "I2S1" },
3580
3581	{ "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" },
3582	{ "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" },
3583	{ "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" },
3584	{ "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" },
3585	{ "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" },
3586	{ "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" },
3587	{ "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" },
3588	{ "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" },
3589
3590	{ "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" },
3591	{ "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" },
3592	{ "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" },
3593	{ "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" },
3594	{ "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" },
3595	{ "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" },
3596	{ "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" },
3597	{ "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" },
3598
3599	{ "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" },
3600	{ "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" },
3601	{ "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" },
3602	{ "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" },
3603	{ "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" },
3604	{ "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" },
3605	{ "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" },
3606	{ "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" },
3607
3608	{ "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" },
3609	{ "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" },
3610	{ "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" },
3611	{ "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" },
3612	{ "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" },
3613	{ "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" },
3614	{ "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" },
3615	{ "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" },
3616
3617	{ "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" },
3618	{ "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" },
3619	{ "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" },
3620	{ "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" },
3621	{ "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" },
3622	{ "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" },
3623	{ "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" },
3624	{ "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" },
3625
3626	{ "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" },
3627	{ "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" },
3628	{ "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" },
3629	{ "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" },
3630	{ "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" },
3631	{ "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" },
3632	{ "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" },
3633	{ "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" },
3634
3635	{ "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" },
3636	{ "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" },
3637	{ "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" },
3638	{ "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" },
3639	{ "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" },
3640	{ "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" },
3641	{ "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" },
3642	{ "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" },
3643
3644	{ "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" },
3645	{ "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" },
3646	{ "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" },
3647	{ "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" },
3648	{ "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" },
3649	{ "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" },
3650	{ "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" },
3651	{ "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" },
3652
3653	{ "IF1 DAC01", NULL, "IF1 DAC0 Mux" },
3654	{ "IF1 DAC01", NULL, "IF1 DAC1 Mux" },
3655	{ "IF1 DAC23", NULL, "IF1 DAC2 Mux" },
3656	{ "IF1 DAC23", NULL, "IF1 DAC3 Mux" },
3657	{ "IF1 DAC45", NULL, "IF1 DAC4 Mux" },
3658	{ "IF1 DAC45", NULL, "IF1 DAC5 Mux" },
3659	{ "IF1 DAC67", NULL, "IF1 DAC6 Mux" },
3660	{ "IF1 DAC67", NULL, "IF1 DAC7 Mux" },
3661
3662	{ "IF2 DAC0", NULL, "AIF2RX" },
3663	{ "IF2 DAC1", NULL, "AIF2RX" },
3664	{ "IF2 DAC2", NULL, "AIF2RX" },
3665	{ "IF2 DAC3", NULL, "AIF2RX" },
3666	{ "IF2 DAC4", NULL, "AIF2RX" },
3667	{ "IF2 DAC5", NULL, "AIF2RX" },
3668	{ "IF2 DAC6", NULL, "AIF2RX" },
3669	{ "IF2 DAC7", NULL, "AIF2RX" },
3670	{ "IF2 DAC0", NULL, "I2S2" },
3671	{ "IF2 DAC1", NULL, "I2S2" },
3672	{ "IF2 DAC2", NULL, "I2S2" },
3673	{ "IF2 DAC3", NULL, "I2S2" },
3674	{ "IF2 DAC4", NULL, "I2S2" },
3675	{ "IF2 DAC5", NULL, "I2S2" },
3676	{ "IF2 DAC6", NULL, "I2S2" },
3677	{ "IF2 DAC7", NULL, "I2S2" },
3678
3679	{ "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" },
3680	{ "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" },
3681	{ "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" },
3682	{ "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" },
3683	{ "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" },
3684	{ "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" },
3685	{ "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" },
3686	{ "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" },
3687
3688	{ "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" },
3689	{ "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" },
3690	{ "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" },
3691	{ "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" },
3692	{ "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" },
3693	{ "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" },
3694	{ "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" },
3695	{ "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" },
3696
3697	{ "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" },
3698	{ "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" },
3699	{ "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" },
3700	{ "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" },
3701	{ "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" },
3702	{ "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" },
3703	{ "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" },
3704	{ "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" },
3705
3706	{ "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" },
3707	{ "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" },
3708	{ "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" },
3709	{ "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" },
3710	{ "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" },
3711	{ "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" },
3712	{ "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" },
3713	{ "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" },
3714
3715	{ "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" },
3716	{ "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" },
3717	{ "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" },
3718	{ "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" },
3719	{ "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" },
3720	{ "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" },
3721	{ "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" },
3722	{ "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" },
3723
3724	{ "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" },
3725	{ "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" },
3726	{ "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" },
3727	{ "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" },
3728	{ "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" },
3729	{ "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" },
3730	{ "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" },
3731	{ "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" },
3732
3733	{ "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" },
3734	{ "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" },
3735	{ "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" },
3736	{ "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" },
3737	{ "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" },
3738	{ "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" },
3739	{ "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" },
3740	{ "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" },
3741
3742	{ "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" },
3743	{ "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" },
3744	{ "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" },
3745	{ "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" },
3746	{ "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" },
3747	{ "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" },
3748	{ "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" },
3749	{ "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" },
3750
3751	{ "IF2 DAC01", NULL, "IF2 DAC0 Mux" },
3752	{ "IF2 DAC01", NULL, "IF2 DAC1 Mux" },
3753	{ "IF2 DAC23", NULL, "IF2 DAC2 Mux" },
3754	{ "IF2 DAC23", NULL, "IF2 DAC3 Mux" },
3755	{ "IF2 DAC45", NULL, "IF2 DAC4 Mux" },
3756	{ "IF2 DAC45", NULL, "IF2 DAC5 Mux" },
3757	{ "IF2 DAC67", NULL, "IF2 DAC6 Mux" },
3758	{ "IF2 DAC67", NULL, "IF2 DAC7 Mux" },
3759
3760	{ "IF3 DAC", NULL, "AIF3RX" },
3761	{ "IF3 DAC", NULL, "I2S3" },
3762
3763	{ "IF4 DAC", NULL, "AIF4RX" },
3764	{ "IF4 DAC", NULL, "I2S4" },
3765
3766	{ "IF3 DAC L", NULL, "IF3 DAC" },
3767	{ "IF3 DAC R", NULL, "IF3 DAC" },
3768
3769	{ "IF4 DAC L", NULL, "IF4 DAC" },
3770	{ "IF4 DAC R", NULL, "IF4 DAC" },
3771
3772	{ "SLB DAC0", NULL, "SLBRX" },
3773	{ "SLB DAC1", NULL, "SLBRX" },
3774	{ "SLB DAC2", NULL, "SLBRX" },
3775	{ "SLB DAC3", NULL, "SLBRX" },
3776	{ "SLB DAC4", NULL, "SLBRX" },
3777	{ "SLB DAC5", NULL, "SLBRX" },
3778	{ "SLB DAC6", NULL, "SLBRX" },
3779	{ "SLB DAC7", NULL, "SLBRX" },
3780	{ "SLB DAC0", NULL, "SLB" },
3781	{ "SLB DAC1", NULL, "SLB" },
3782	{ "SLB DAC2", NULL, "SLB" },
3783	{ "SLB DAC3", NULL, "SLB" },
3784	{ "SLB DAC4", NULL, "SLB" },
3785	{ "SLB DAC5", NULL, "SLB" },
3786	{ "SLB DAC6", NULL, "SLB" },
3787	{ "SLB DAC7", NULL, "SLB" },
3788
3789	{ "SLB DAC01", NULL, "SLB DAC0" },
3790	{ "SLB DAC01", NULL, "SLB DAC1" },
3791	{ "SLB DAC23", NULL, "SLB DAC2" },
3792	{ "SLB DAC23", NULL, "SLB DAC3" },
3793	{ "SLB DAC45", NULL, "SLB DAC4" },
3794	{ "SLB DAC45", NULL, "SLB DAC5" },
3795	{ "SLB DAC67", NULL, "SLB DAC6" },
3796	{ "SLB DAC67", NULL, "SLB DAC7" },
3797
3798	{ "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3799	{ "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3800	{ "ADDA1 Mux", "OB 67", "OB67" },
3801
3802	{ "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
3803	{ "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
3804	{ "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
3805	{ "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
3806	{ "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
3807	{ "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
3808
3809	{ "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
3810	{ "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
3811	{ "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
3812	{ "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
3813
3814	{ "DAC1 FS", NULL, "DAC1 MIXL" },
3815	{ "DAC1 FS", NULL, "DAC1 MIXR" },
3816
3817	{ "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2 Mux" },
3818	{ "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2 Mux" },
3819	{ "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
3820	{ "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
3821	{ "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
3822	{ "DAC2 L Mux", "OB 2", "OutBound2" },
3823
3824	{ "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3 Mux" },
3825	{ "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3 Mux" },
3826	{ "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
3827	{ "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
3828	{ "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
3829	{ "DAC2 R Mux", "OB 3", "OutBound3" },
3830	{ "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
3831	{ "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
3832
3833	{ "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4 Mux" },
3834	{ "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4 Mux" },
3835	{ "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
3836	{ "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
3837	{ "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
3838	{ "DAC3 L Mux", "OB 4", "OutBound4" },
3839
3840	{ "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC5 Mux" },
3841	{ "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC5 Mux" },
3842	{ "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
3843	{ "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
3844	{ "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
3845	{ "DAC3 R Mux", "OB 5", "OutBound5" },
3846
3847	{ "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3848	{ "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
3849	{ "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
3850	{ "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
3851	{ "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
3852	{ "DAC4 L Mux", "OB 6", "OutBound6" },
3853
3854	{ "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3855	{ "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
3856	{ "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
3857	{ "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
3858	{ "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
3859	{ "DAC4 R Mux", "OB 7", "OutBound7" },
3860
3861	{ "Sidetone Mux", "DMIC1 L", "DMIC L1" },
3862	{ "Sidetone Mux", "DMIC2 L", "DMIC L2" },
3863	{ "Sidetone Mux", "DMIC3 L", "DMIC L3" },
3864	{ "Sidetone Mux", "DMIC4 L", "DMIC L4" },
3865	{ "Sidetone Mux", "ADC1", "ADC 1" },
3866	{ "Sidetone Mux", "ADC2", "ADC 2" },
3867	{ "Sidetone Mux", NULL, "Sidetone Power" },
3868
3869	{ "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
3870	{ "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3871	{ "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3872	{ "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
3873	{ "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
3874	{ "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
3875	{ "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3876	{ "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3877	{ "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
3878	{ "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
3879	{ "dac stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3880
3881	{ "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
3882	{ "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3883	{ "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3884	{ "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
3885	{ "Mono DAC MIXL", NULL, "dac mono2 left filter" },
3886	{ "dac mono2 left filter", NULL, "PLL1", is_sys_clk_from_pll },
3887	{ "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
3888	{ "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3889	{ "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3890	{ "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
3891	{ "Mono DAC MIXR", NULL, "dac mono2 right filter" },
3892	{ "dac mono2 right filter", NULL, "PLL1", is_sys_clk_from_pll },
3893
3894	{ "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
3895	{ "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
3896	{ "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
3897	{ "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
3898	{ "DD1 MIXL", NULL, "dac mono3 left filter" },
3899	{ "dac mono3 left filter", NULL, "PLL1", is_sys_clk_from_pll },
3900	{ "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
3901	{ "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
3902	{ "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
3903	{ "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
3904	{ "DD1 MIXR", NULL, "dac mono3 right filter" },
3905	{ "dac mono3 right filter", NULL, "PLL1", is_sys_clk_from_pll },
3906
3907	{ "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
3908	{ "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
3909	{ "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
3910	{ "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
3911	{ "DD2 MIXL", NULL, "dac mono4 left filter" },
3912	{ "dac mono4 left filter", NULL, "PLL1", is_sys_clk_from_pll },
3913	{ "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
3914	{ "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
3915	{ "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
3916	{ "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
3917	{ "DD2 MIXR", NULL, "dac mono4 right filter" },
3918	{ "dac mono4 right filter", NULL, "PLL1", is_sys_clk_from_pll },
3919
3920	{ "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
3921	{ "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
3922	{ "Mono DAC MIX", NULL, "Mono DAC MIXL" },
3923	{ "Mono DAC MIX", NULL, "Mono DAC MIXR" },
3924	{ "DD1 MIX", NULL, "DD1 MIXL" },
3925	{ "DD1 MIX", NULL, "DD1 MIXR" },
3926	{ "DD2 MIX", NULL, "DD2 MIXL" },
3927	{ "DD2 MIX", NULL, "DD2 MIXR" },
3928
3929	{ "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
3930	{ "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
3931	{ "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
3932	{ "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
3933
3934	{ "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3935	{ "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3936	{ "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
3937	{ "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
3938
3939	{ "DAC 1", NULL, "DAC12 SRC Mux" },
3940	{ "DAC 2", NULL, "DAC12 SRC Mux" },
3941	{ "DAC 3", NULL, "DAC3 SRC Mux" },
3942
3943	{ "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
3944	{ "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
3945	{ "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
3946	{ "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
3947	{ "PDM1 L Mux", NULL, "PDM1 Power" },
3948	{ "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
3949	{ "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
3950	{ "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
3951	{ "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
3952	{ "PDM1 R Mux", NULL, "PDM1 Power" },
3953	{ "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
3954	{ "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
3955	{ "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
3956	{ "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
3957	{ "PDM2 L Mux", NULL, "PDM2 Power" },
3958	{ "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
3959	{ "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
3960	{ "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
3961	{ "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
3962	{ "PDM2 R Mux", NULL, "PDM2 Power" },
3963
3964	{ "LOUT1 amp", NULL, "DAC 1" },
3965	{ "LOUT2 amp", NULL, "DAC 2" },
3966	{ "LOUT3 amp", NULL, "DAC 3" },
3967
3968	{ "LOUT1 vref", NULL, "LOUT1 amp" },
3969	{ "LOUT2 vref", NULL, "LOUT2 amp" },
3970	{ "LOUT3 vref", NULL, "LOUT3 amp" },
3971
3972	{ "LOUT1", NULL, "LOUT1 vref" },
3973	{ "LOUT2", NULL, "LOUT2 vref" },
3974	{ "LOUT3", NULL, "LOUT3 vref" },
3975
3976	{ "PDM1L", NULL, "PDM1 L Mux" },
3977	{ "PDM1R", NULL, "PDM1 R Mux" },
3978	{ "PDM2L", NULL, "PDM2 L Mux" },
3979	{ "PDM2R", NULL, "PDM2 R Mux" },
3980};
3981
3982static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = {
3983	{ "DMIC L2", NULL, "DMIC1 power" },
3984	{ "DMIC R2", NULL, "DMIC1 power" },
3985};
3986
3987static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = {
3988	{ "DMIC L2", NULL, "DMIC2 power" },
3989	{ "DMIC R2", NULL, "DMIC2 power" },
3990};
3991
3992static int rt5677_hw_params(struct snd_pcm_substream *substream,
3993	struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
3994{
3995	struct snd_soc_codec *codec = dai->codec;
3996	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3997	unsigned int val_len = 0, val_clk, mask_clk;
3998	int pre_div, bclk_ms, frame_size;
3999
4000	rt5677->lrck[dai->id] = params_rate(params);
4001	pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
4002	if (pre_div < 0) {
4003		dev_err(codec->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n",
4004			rt5677->sysclk, rt5677->lrck[dai->id]);
4005		return -EINVAL;
4006	}
4007	frame_size = snd_soc_params_to_frame_size(params);
4008	if (frame_size < 0) {
4009		dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
4010		return -EINVAL;
4011	}
4012	bclk_ms = frame_size > 32;
4013	rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
4014
4015	dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
4016		rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
4017	dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
4018				bclk_ms, pre_div, dai->id);
4019
4020	switch (params_width(params)) {
4021	case 16:
4022		break;
4023	case 20:
4024		val_len |= RT5677_I2S_DL_20;
4025		break;
4026	case 24:
4027		val_len |= RT5677_I2S_DL_24;
4028		break;
4029	case 8:
4030		val_len |= RT5677_I2S_DL_8;
4031		break;
4032	default:
4033		return -EINVAL;
4034	}
4035
4036	switch (dai->id) {
4037	case RT5677_AIF1:
4038		mask_clk = RT5677_I2S_PD1_MASK;
4039		val_clk = pre_div << RT5677_I2S_PD1_SFT;
4040		regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4041			RT5677_I2S_DL_MASK, val_len);
4042		regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4043			mask_clk, val_clk);
4044		break;
4045	case RT5677_AIF2:
4046		mask_clk = RT5677_I2S_PD2_MASK;
4047		val_clk = pre_div << RT5677_I2S_PD2_SFT;
4048		regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4049			RT5677_I2S_DL_MASK, val_len);
4050		regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4051			mask_clk, val_clk);
4052		break;
4053	case RT5677_AIF3:
4054		mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
4055		val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
4056			pre_div << RT5677_I2S_PD3_SFT;
4057		regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4058			RT5677_I2S_DL_MASK, val_len);
4059		regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4060			mask_clk, val_clk);
4061		break;
4062	case RT5677_AIF4:
4063		mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
4064		val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
4065			pre_div << RT5677_I2S_PD4_SFT;
4066		regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4067			RT5677_I2S_DL_MASK, val_len);
4068		regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4069			mask_clk, val_clk);
4070		break;
4071	default:
4072		break;
4073	}
4074
4075	return 0;
4076}
4077
4078static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
4079{
4080	struct snd_soc_codec *codec = dai->codec;
4081	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4082	unsigned int reg_val = 0;
4083
4084	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4085	case SND_SOC_DAIFMT_CBM_CFM:
4086		rt5677->master[dai->id] = 1;
4087		break;
4088	case SND_SOC_DAIFMT_CBS_CFS:
4089		reg_val |= RT5677_I2S_MS_S;
4090		rt5677->master[dai->id] = 0;
4091		break;
4092	default:
4093		return -EINVAL;
4094	}
4095
4096	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
4097	case SND_SOC_DAIFMT_NB_NF:
4098		break;
4099	case SND_SOC_DAIFMT_IB_NF:
4100		reg_val |= RT5677_I2S_BP_INV;
4101		break;
4102	default:
4103		return -EINVAL;
4104	}
4105
4106	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
4107	case SND_SOC_DAIFMT_I2S:
4108		break;
4109	case SND_SOC_DAIFMT_LEFT_J:
4110		reg_val |= RT5677_I2S_DF_LEFT;
4111		break;
4112	case SND_SOC_DAIFMT_DSP_A:
4113		reg_val |= RT5677_I2S_DF_PCM_A;
4114		break;
4115	case SND_SOC_DAIFMT_DSP_B:
4116		reg_val |= RT5677_I2S_DF_PCM_B;
4117		break;
4118	default:
4119		return -EINVAL;
4120	}
4121
4122	switch (dai->id) {
4123	case RT5677_AIF1:
4124		regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4125			RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4126			RT5677_I2S_DF_MASK, reg_val);
4127		break;
4128	case RT5677_AIF2:
4129		regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4130			RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4131			RT5677_I2S_DF_MASK, reg_val);
4132		break;
4133	case RT5677_AIF3:
4134		regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4135			RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4136			RT5677_I2S_DF_MASK, reg_val);
4137		break;
4138	case RT5677_AIF4:
4139		regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4140			RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4141			RT5677_I2S_DF_MASK, reg_val);
4142		break;
4143	default:
4144		break;
4145	}
4146
4147
4148	return 0;
4149}
4150
4151static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
4152		int clk_id, unsigned int freq, int dir)
4153{
4154	struct snd_soc_codec *codec = dai->codec;
4155	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4156	unsigned int reg_val = 0;
4157
4158	if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
4159		return 0;
4160
4161	switch (clk_id) {
4162	case RT5677_SCLK_S_MCLK:
4163		reg_val |= RT5677_SCLK_SRC_MCLK;
4164		break;
4165	case RT5677_SCLK_S_PLL1:
4166		reg_val |= RT5677_SCLK_SRC_PLL1;
4167		break;
4168	case RT5677_SCLK_S_RCCLK:
4169		reg_val |= RT5677_SCLK_SRC_RCCLK;
4170		break;
4171	default:
4172		dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
4173		return -EINVAL;
4174	}
4175	regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4176		RT5677_SCLK_SRC_MASK, reg_val);
4177	rt5677->sysclk = freq;
4178	rt5677->sysclk_src = clk_id;
4179
4180	dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
4181
4182	return 0;
4183}
4184
4185/**
4186 * rt5677_pll_calc - Calcualte PLL M/N/K code.
4187 * @freq_in: external clock provided to codec.
4188 * @freq_out: target clock which codec works on.
4189 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
4190 *
4191 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
4192 *
4193 * Returns 0 for success or negative error code.
4194 */
4195static int rt5677_pll_calc(const unsigned int freq_in,
4196	const unsigned int freq_out, struct rl6231_pll_code *pll_code)
4197{
4198	if (RT5677_PLL_INP_MIN > freq_in)
4199		return -EINVAL;
4200
4201	return rl6231_pll_calc(freq_in, freq_out, pll_code);
4202}
4203
4204static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
4205			unsigned int freq_in, unsigned int freq_out)
4206{
4207	struct snd_soc_codec *codec = dai->codec;
4208	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4209	struct rl6231_pll_code pll_code;
4210	int ret;
4211
4212	if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
4213	    freq_out == rt5677->pll_out)
4214		return 0;
4215
4216	if (!freq_in || !freq_out) {
4217		dev_dbg(codec->dev, "PLL disabled\n");
4218
4219		rt5677->pll_in = 0;
4220		rt5677->pll_out = 0;
4221		regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4222			RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
4223		return 0;
4224	}
4225
4226	switch (source) {
4227	case RT5677_PLL1_S_MCLK:
4228		regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4229			RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
4230		break;
4231	case RT5677_PLL1_S_BCLK1:
4232	case RT5677_PLL1_S_BCLK2:
4233	case RT5677_PLL1_S_BCLK3:
4234	case RT5677_PLL1_S_BCLK4:
4235		switch (dai->id) {
4236		case RT5677_AIF1:
4237			regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4238				RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
4239			break;
4240		case RT5677_AIF2:
4241			regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4242				RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
4243			break;
4244		case RT5677_AIF3:
4245			regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4246				RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
4247			break;
4248		case RT5677_AIF4:
4249			regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4250				RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
4251			break;
4252		default:
4253			break;
4254		}
4255		break;
4256	default:
4257		dev_err(codec->dev, "Unknown PLL source %d\n", source);
4258		return -EINVAL;
4259	}
4260
4261	ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
4262	if (ret < 0) {
4263		dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
4264		return ret;
4265	}
4266
4267	dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n",
4268		pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4269		pll_code.n_code, pll_code.k_code);
4270
4271	regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
4272		pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
4273	regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
4274		(pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
4275		pll_code.m_bp << RT5677_PLL_M_BP_SFT);
4276
4277	rt5677->pll_in = freq_in;
4278	rt5677->pll_out = freq_out;
4279	rt5677->pll_src = source;
4280
4281	return 0;
4282}
4283
4284static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
4285			unsigned int rx_mask, int slots, int slot_width)
4286{
4287	struct snd_soc_codec *codec = dai->codec;
4288	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4289	unsigned int val = 0, slot_width_25 = 0;
4290
4291	if (rx_mask || tx_mask)
4292		val |= (1 << 12);
4293
4294	switch (slots) {
4295	case 4:
4296		val |= (1 << 10);
4297		break;
4298	case 6:
4299		val |= (2 << 10);
4300		break;
4301	case 8:
4302		val |= (3 << 10);
4303		break;
4304	case 2:
4305	default:
4306		break;
4307	}
4308
4309	switch (slot_width) {
4310	case 20:
4311		val |= (1 << 8);
4312		break;
4313	case 25:
4314		slot_width_25 = 0x8080;
4315	case 24:
4316		val |= (2 << 8);
4317		break;
4318	case 32:
4319		val |= (3 << 8);
4320		break;
4321	case 16:
4322	default:
4323		break;
4324	}
4325
4326	switch (dai->id) {
4327	case RT5677_AIF1:
4328		regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00,
4329			val);
4330		regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000,
4331			slot_width_25);
4332		break;
4333	case RT5677_AIF2:
4334		regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00,
4335			val);
4336		regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80,
4337			slot_width_25);
4338		break;
4339	default:
4340		break;
4341	}
4342
4343	return 0;
4344}
4345
4346static int rt5677_set_bias_level(struct snd_soc_codec *codec,
4347			enum snd_soc_bias_level level)
4348{
4349	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4350
4351	switch (level) {
4352	case SND_SOC_BIAS_ON:
4353		break;
4354
4355	case SND_SOC_BIAS_PREPARE:
4356		if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
4357			rt5677_set_dsp_vad(codec, false);
4358
4359			regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4360				RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
4361				0x0055);
4362			regmap_update_bits(rt5677->regmap,
4363				RT5677_PR_BASE + RT5677_BIAS_CUR4,
4364				0x0f00, 0x0f00);
4365			regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4366				RT5677_PWR_FV1 | RT5677_PWR_FV2 |
4367				RT5677_PWR_VREF1 | RT5677_PWR_MB |
4368				RT5677_PWR_BG | RT5677_PWR_VREF2,
4369				RT5677_PWR_VREF1 | RT5677_PWR_MB |
4370				RT5677_PWR_BG | RT5677_PWR_VREF2);
4371			rt5677->is_vref_slow = false;
4372			regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
4373				RT5677_PWR_CORE, RT5677_PWR_CORE);
4374			regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
4375				0x1, 0x1);
4376		}
4377		break;
4378
4379	case SND_SOC_BIAS_STANDBY:
4380		break;
4381
4382	case SND_SOC_BIAS_OFF:
4383		regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
4384		regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
4385		regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
4386		regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022);
4387		regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
4388		regmap_update_bits(rt5677->regmap,
4389			RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
4390
4391		if (rt5677->dsp_vad_en)
4392			rt5677_set_dsp_vad(codec, true);
4393		break;
4394
4395	default:
4396		break;
4397	}
4398	codec->dapm.bias_level = level;
4399
4400	return 0;
4401}
4402
4403#ifdef CONFIG_GPIOLIB
4404static inline struct rt5677_priv *gpio_to_rt5677(struct gpio_chip *chip)
4405{
4406	return container_of(chip, struct rt5677_priv, gpio_chip);
4407}
4408
4409static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
4410{
4411	struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4412
4413	switch (offset) {
4414	case RT5677_GPIO1 ... RT5677_GPIO5:
4415		regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4416			0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1));
4417		break;
4418
4419	case RT5677_GPIO6:
4420		regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4421			RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT);
4422		break;
4423
4424	default:
4425		break;
4426	}
4427}
4428
4429static int rt5677_gpio_direction_out(struct gpio_chip *chip,
4430				     unsigned offset, int value)
4431{
4432	struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4433
4434	switch (offset) {
4435	case RT5677_GPIO1 ... RT5677_GPIO5:
4436		regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4437			0x3 << (offset * 3 + 1),
4438			(0x2 | !!value) << (offset * 3 + 1));
4439		break;
4440
4441	case RT5677_GPIO6:
4442		regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4443			RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK,
4444			RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT);
4445		break;
4446
4447	default:
4448		break;
4449	}
4450
4451	return 0;
4452}
4453
4454static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
4455{
4456	struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4457	int value, ret;
4458
4459	ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
4460	if (ret < 0)
4461		return ret;
4462
4463	return (value & (0x1 << offset)) >> offset;
4464}
4465
4466static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
4467{
4468	struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4469
4470	switch (offset) {
4471	case RT5677_GPIO1 ... RT5677_GPIO5:
4472		regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4473			0x1 << (offset * 3 + 2), 0x0);
4474		break;
4475
4476	case RT5677_GPIO6:
4477		regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4478			RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN);
4479		break;
4480
4481	default:
4482		break;
4483	}
4484
4485	return 0;
4486}
4487
4488/** Configures the gpio as
4489 *   0 - floating
4490 *   1 - pull down
4491 *   2 - pull up
4492 */
4493static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4494		int value)
4495{
4496	int shift;
4497
4498	switch (offset) {
4499	case RT5677_GPIO1 ... RT5677_GPIO2:
4500		shift = 2 * (1 - offset);
4501		regmap_update_bits(rt5677->regmap,
4502			RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2,
4503			0x3 << shift,
4504			(value & 0x3) << shift);
4505		break;
4506
4507	case RT5677_GPIO3 ... RT5677_GPIO6:
4508		shift = 2 * (9 - offset);
4509		regmap_update_bits(rt5677->regmap,
4510			RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3,
4511			0x3 << shift,
4512			(value & 0x3) << shift);
4513		break;
4514
4515	default:
4516		break;
4517	}
4518}
4519
4520static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset)
4521{
4522	struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4523	struct regmap_irq_chip_data *data = rt5677->irq_data;
4524	int irq;
4525
4526	if (offset >= RT5677_GPIO1 && offset <= RT5677_GPIO3) {
4527		if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
4528			(rt5677->pdata.jd1_gpio == 2 &&
4529				offset == RT5677_GPIO2) ||
4530			(rt5677->pdata.jd1_gpio == 3 &&
4531				offset == RT5677_GPIO3)) {
4532			irq = RT5677_IRQ_JD1;
4533		} else {
4534			return -ENXIO;
4535		}
4536	}
4537
4538	if (offset >= RT5677_GPIO4 && offset <= RT5677_GPIO6) {
4539		if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
4540			(rt5677->pdata.jd2_gpio == 2 &&
4541				offset == RT5677_GPIO5) ||
4542			(rt5677->pdata.jd2_gpio == 3 &&
4543				offset == RT5677_GPIO6)) {
4544			irq = RT5677_IRQ_JD2;
4545		} else if ((rt5677->pdata.jd3_gpio == 1 &&
4546				offset == RT5677_GPIO4) ||
4547			(rt5677->pdata.jd3_gpio == 2 &&
4548				offset == RT5677_GPIO5) ||
4549			(rt5677->pdata.jd3_gpio == 3 &&
4550				offset == RT5677_GPIO6)) {
4551			irq = RT5677_IRQ_JD3;
4552		} else {
4553			return -ENXIO;
4554		}
4555	}
4556
4557	return regmap_irq_get_virq(data, irq);
4558}
4559
4560static struct gpio_chip rt5677_template_chip = {
4561	.label			= "rt5677",
4562	.owner			= THIS_MODULE,
4563	.direction_output	= rt5677_gpio_direction_out,
4564	.set			= rt5677_gpio_set,
4565	.direction_input	= rt5677_gpio_direction_in,
4566	.get			= rt5677_gpio_get,
4567	.to_irq			= rt5677_to_irq,
4568	.can_sleep		= 1,
4569};
4570
4571static void rt5677_init_gpio(struct i2c_client *i2c)
4572{
4573	struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4574	int ret;
4575
4576	rt5677->gpio_chip = rt5677_template_chip;
4577	rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
4578	rt5677->gpio_chip.dev = &i2c->dev;
4579	rt5677->gpio_chip.base = -1;
4580
4581	ret = gpiochip_add(&rt5677->gpio_chip);
4582	if (ret != 0)
4583		dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
4584}
4585
4586static void rt5677_free_gpio(struct i2c_client *i2c)
4587{
4588	struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4589
4590	gpiochip_remove(&rt5677->gpio_chip);
4591}
4592#else
4593static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4594		int value)
4595{
4596}
4597
4598static void rt5677_init_gpio(struct i2c_client *i2c)
4599{
4600}
4601
4602static void rt5677_free_gpio(struct i2c_client *i2c)
4603{
4604}
4605#endif
4606
4607static int rt5677_probe(struct snd_soc_codec *codec)
4608{
4609	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4610	int i;
4611
4612	rt5677->codec = codec;
4613
4614	if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
4615		snd_soc_dapm_add_routes(&codec->dapm,
4616			rt5677_dmic2_clk_2,
4617			ARRAY_SIZE(rt5677_dmic2_clk_2));
4618	} else { /*use dmic1 clock by default*/
4619		snd_soc_dapm_add_routes(&codec->dapm,
4620			rt5677_dmic2_clk_1,
4621			ARRAY_SIZE(rt5677_dmic2_clk_1));
4622	}
4623
4624	rt5677_set_bias_level(codec, SND_SOC_BIAS_OFF);
4625
4626	regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
4627	regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
4628
4629	for (i = 0; i < RT5677_GPIO_NUM; i++)
4630		rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
4631
4632	if (rt5677->irq_data) {
4633		regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 0x8000,
4634			0x8000);
4635		regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x0018,
4636			0x0008);
4637
4638		if (rt5677->pdata.jd1_gpio)
4639			regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4640				RT5677_SEL_GPIO_JD1_MASK,
4641				rt5677->pdata.jd1_gpio <<
4642				RT5677_SEL_GPIO_JD1_SFT);
4643
4644		if (rt5677->pdata.jd2_gpio)
4645			regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4646				RT5677_SEL_GPIO_JD2_MASK,
4647				rt5677->pdata.jd2_gpio <<
4648				RT5677_SEL_GPIO_JD2_SFT);
4649
4650		if (rt5677->pdata.jd3_gpio)
4651			regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4652				RT5677_SEL_GPIO_JD3_MASK,
4653				rt5677->pdata.jd3_gpio <<
4654				RT5677_SEL_GPIO_JD3_SFT);
4655	}
4656
4657	mutex_init(&rt5677->dsp_cmd_lock);
4658	mutex_init(&rt5677->dsp_pri_lock);
4659
4660	return 0;
4661}
4662
4663static int rt5677_remove(struct snd_soc_codec *codec)
4664{
4665	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4666
4667	regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
4668	if (gpio_is_valid(rt5677->pow_ldo2))
4669		gpio_set_value_cansleep(rt5677->pow_ldo2, 0);
4670
4671	return 0;
4672}
4673
4674#ifdef CONFIG_PM
4675static int rt5677_suspend(struct snd_soc_codec *codec)
4676{
4677	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4678
4679	if (!rt5677->dsp_vad_en) {
4680		regcache_cache_only(rt5677->regmap, true);
4681		regcache_mark_dirty(rt5677->regmap);
4682
4683		if (gpio_is_valid(rt5677->pow_ldo2))
4684			gpio_set_value_cansleep(rt5677->pow_ldo2, 0);
4685	}
4686
4687	return 0;
4688}
4689
4690static int rt5677_resume(struct snd_soc_codec *codec)
4691{
4692	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4693
4694	if (!rt5677->dsp_vad_en) {
4695		if (gpio_is_valid(rt5677->pow_ldo2)) {
4696			gpio_set_value_cansleep(rt5677->pow_ldo2, 1);
4697			msleep(10);
4698		}
4699
4700		regcache_cache_only(rt5677->regmap, false);
4701		regcache_sync(rt5677->regmap);
4702	}
4703
4704	return 0;
4705}
4706#else
4707#define rt5677_suspend NULL
4708#define rt5677_resume NULL
4709#endif
4710
4711static int rt5677_read(void *context, unsigned int reg, unsigned int *val)
4712{
4713	struct i2c_client *client = context;
4714	struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4715
4716	if (rt5677->is_dsp_mode) {
4717		if (reg > 0xff) {
4718			mutex_lock(&rt5677->dsp_pri_lock);
4719			rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4720				reg & 0xff);
4721			rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val);
4722			mutex_unlock(&rt5677->dsp_pri_lock);
4723		} else {
4724			rt5677_dsp_mode_i2c_read(rt5677, reg, val);
4725		}
4726	} else {
4727		regmap_read(rt5677->regmap_physical, reg, val);
4728	}
4729
4730	return 0;
4731}
4732
4733static int rt5677_write(void *context, unsigned int reg, unsigned int val)
4734{
4735	struct i2c_client *client = context;
4736	struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4737
4738	if (rt5677->is_dsp_mode) {
4739		if (reg > 0xff) {
4740			mutex_lock(&rt5677->dsp_pri_lock);
4741			rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4742				reg & 0xff);
4743			rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA,
4744				val);
4745			mutex_unlock(&rt5677->dsp_pri_lock);
4746		} else {
4747			rt5677_dsp_mode_i2c_write(rt5677, reg, val);
4748		}
4749	} else {
4750		regmap_write(rt5677->regmap_physical, reg, val);
4751	}
4752
4753	return 0;
4754}
4755
4756#define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
4757#define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4758			SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4759
4760static struct snd_soc_dai_ops rt5677_aif_dai_ops = {
4761	.hw_params = rt5677_hw_params,
4762	.set_fmt = rt5677_set_dai_fmt,
4763	.set_sysclk = rt5677_set_dai_sysclk,
4764	.set_pll = rt5677_set_dai_pll,
4765	.set_tdm_slot = rt5677_set_tdm_slot,
4766};
4767
4768static struct snd_soc_dai_driver rt5677_dai[] = {
4769	{
4770		.name = "rt5677-aif1",
4771		.id = RT5677_AIF1,
4772		.playback = {
4773			.stream_name = "AIF1 Playback",
4774			.channels_min = 1,
4775			.channels_max = 2,
4776			.rates = RT5677_STEREO_RATES,
4777			.formats = RT5677_FORMATS,
4778		},
4779		.capture = {
4780			.stream_name = "AIF1 Capture",
4781			.channels_min = 1,
4782			.channels_max = 2,
4783			.rates = RT5677_STEREO_RATES,
4784			.formats = RT5677_FORMATS,
4785		},
4786		.ops = &rt5677_aif_dai_ops,
4787	},
4788	{
4789		.name = "rt5677-aif2",
4790		.id = RT5677_AIF2,
4791		.playback = {
4792			.stream_name = "AIF2 Playback",
4793			.channels_min = 1,
4794			.channels_max = 2,
4795			.rates = RT5677_STEREO_RATES,
4796			.formats = RT5677_FORMATS,
4797		},
4798		.capture = {
4799			.stream_name = "AIF2 Capture",
4800			.channels_min = 1,
4801			.channels_max = 2,
4802			.rates = RT5677_STEREO_RATES,
4803			.formats = RT5677_FORMATS,
4804		},
4805		.ops = &rt5677_aif_dai_ops,
4806	},
4807	{
4808		.name = "rt5677-aif3",
4809		.id = RT5677_AIF3,
4810		.playback = {
4811			.stream_name = "AIF3 Playback",
4812			.channels_min = 1,
4813			.channels_max = 2,
4814			.rates = RT5677_STEREO_RATES,
4815			.formats = RT5677_FORMATS,
4816		},
4817		.capture = {
4818			.stream_name = "AIF3 Capture",
4819			.channels_min = 1,
4820			.channels_max = 2,
4821			.rates = RT5677_STEREO_RATES,
4822			.formats = RT5677_FORMATS,
4823		},
4824		.ops = &rt5677_aif_dai_ops,
4825	},
4826	{
4827		.name = "rt5677-aif4",
4828		.id = RT5677_AIF4,
4829		.playback = {
4830			.stream_name = "AIF4 Playback",
4831			.channels_min = 1,
4832			.channels_max = 2,
4833			.rates = RT5677_STEREO_RATES,
4834			.formats = RT5677_FORMATS,
4835		},
4836		.capture = {
4837			.stream_name = "AIF4 Capture",
4838			.channels_min = 1,
4839			.channels_max = 2,
4840			.rates = RT5677_STEREO_RATES,
4841			.formats = RT5677_FORMATS,
4842		},
4843		.ops = &rt5677_aif_dai_ops,
4844	},
4845	{
4846		.name = "rt5677-slimbus",
4847		.id = RT5677_AIF5,
4848		.playback = {
4849			.stream_name = "SLIMBus Playback",
4850			.channels_min = 1,
4851			.channels_max = 2,
4852			.rates = RT5677_STEREO_RATES,
4853			.formats = RT5677_FORMATS,
4854		},
4855		.capture = {
4856			.stream_name = "SLIMBus Capture",
4857			.channels_min = 1,
4858			.channels_max = 2,
4859			.rates = RT5677_STEREO_RATES,
4860			.formats = RT5677_FORMATS,
4861		},
4862		.ops = &rt5677_aif_dai_ops,
4863	},
4864};
4865
4866static struct snd_soc_codec_driver soc_codec_dev_rt5677 = {
4867	.probe = rt5677_probe,
4868	.remove = rt5677_remove,
4869	.suspend = rt5677_suspend,
4870	.resume = rt5677_resume,
4871	.set_bias_level = rt5677_set_bias_level,
4872	.idle_bias_off = true,
4873	.controls = rt5677_snd_controls,
4874	.num_controls = ARRAY_SIZE(rt5677_snd_controls),
4875	.dapm_widgets = rt5677_dapm_widgets,
4876	.num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
4877	.dapm_routes = rt5677_dapm_routes,
4878	.num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
4879};
4880
4881static const struct regmap_config rt5677_regmap_physical = {
4882	.name = "physical",
4883	.reg_bits = 8,
4884	.val_bits = 16,
4885
4886	.max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4887						RT5677_PR_SPACING),
4888	.readable_reg = rt5677_readable_register,
4889
4890	.cache_type = REGCACHE_NONE,
4891	.ranges = rt5677_ranges,
4892	.num_ranges = ARRAY_SIZE(rt5677_ranges),
4893};
4894
4895static const struct regmap_config rt5677_regmap = {
4896	.reg_bits = 8,
4897	.val_bits = 16,
4898
4899	.max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4900						RT5677_PR_SPACING),
4901
4902	.volatile_reg = rt5677_volatile_register,
4903	.readable_reg = rt5677_readable_register,
4904	.reg_read = rt5677_read,
4905	.reg_write = rt5677_write,
4906
4907	.cache_type = REGCACHE_RBTREE,
4908	.reg_defaults = rt5677_reg,
4909	.num_reg_defaults = ARRAY_SIZE(rt5677_reg),
4910	.ranges = rt5677_ranges,
4911	.num_ranges = ARRAY_SIZE(rt5677_ranges),
4912};
4913
4914static const struct i2c_device_id rt5677_i2c_id[] = {
4915	{ "rt5677", RT5677 },
4916	{ "rt5676", RT5676 },
4917	{ }
4918};
4919MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id);
4920
4921static int rt5677_parse_dt(struct rt5677_priv *rt5677, struct device_node *np)
4922{
4923	rt5677->pdata.in1_diff = of_property_read_bool(np,
4924					"realtek,in1-differential");
4925	rt5677->pdata.in2_diff = of_property_read_bool(np,
4926					"realtek,in2-differential");
4927	rt5677->pdata.lout1_diff = of_property_read_bool(np,
4928					"realtek,lout1-differential");
4929	rt5677->pdata.lout2_diff = of_property_read_bool(np,
4930					"realtek,lout2-differential");
4931	rt5677->pdata.lout3_diff = of_property_read_bool(np,
4932					"realtek,lout3-differential");
4933
4934	rt5677->pow_ldo2 = of_get_named_gpio(np,
4935					"realtek,pow-ldo2-gpio", 0);
4936
4937	/*
4938	 * POW_LDO2 is optional (it may be statically tied on the board).
4939	 * -ENOENT means that the property doesn't exist, i.e. there is no
4940	 * GPIO, so is not an error. Any other error code means the property
4941	 * exists, but could not be parsed.
4942	 */
4943	if (!gpio_is_valid(rt5677->pow_ldo2) &&
4944			(rt5677->pow_ldo2 != -ENOENT))
4945		return rt5677->pow_ldo2;
4946
4947	of_property_read_u8_array(np, "realtek,gpio-config",
4948		rt5677->pdata.gpio_config, RT5677_GPIO_NUM);
4949
4950	of_property_read_u32(np, "realtek,jd1-gpio", &rt5677->pdata.jd1_gpio);
4951	of_property_read_u32(np, "realtek,jd2-gpio", &rt5677->pdata.jd2_gpio);
4952	of_property_read_u32(np, "realtek,jd3-gpio", &rt5677->pdata.jd3_gpio);
4953
4954	return 0;
4955}
4956
4957static struct regmap_irq rt5677_irqs[] = {
4958	[RT5677_IRQ_JD1] = {
4959		.reg_offset = 0,
4960		.mask = RT5677_EN_IRQ_GPIO_JD1,
4961	},
4962	[RT5677_IRQ_JD2] = {
4963		.reg_offset = 0,
4964		.mask = RT5677_EN_IRQ_GPIO_JD2,
4965	},
4966	[RT5677_IRQ_JD3] = {
4967		.reg_offset = 0,
4968		.mask = RT5677_EN_IRQ_GPIO_JD3,
4969	},
4970};
4971
4972static struct regmap_irq_chip rt5677_irq_chip = {
4973	.name = "rt5677",
4974	.irqs = rt5677_irqs,
4975	.num_irqs = ARRAY_SIZE(rt5677_irqs),
4976
4977	.num_regs = 1,
4978	.status_base = RT5677_IRQ_CTRL1,
4979	.mask_base = RT5677_IRQ_CTRL1,
4980	.mask_invert = 1,
4981};
4982
4983static int rt5677_init_irq(struct i2c_client *i2c)
4984{
4985	int ret;
4986	struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4987
4988	if (!rt5677->pdata.jd1_gpio &&
4989		!rt5677->pdata.jd2_gpio &&
4990		!rt5677->pdata.jd3_gpio)
4991		return 0;
4992
4993	if (!i2c->irq) {
4994		dev_err(&i2c->dev, "No interrupt specified\n");
4995		return -EINVAL;
4996	}
4997
4998	ret = regmap_add_irq_chip(rt5677->regmap, i2c->irq,
4999		IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 0,
5000		&rt5677_irq_chip, &rt5677->irq_data);
5001
5002	if (ret != 0) {
5003		dev_err(&i2c->dev, "Failed to register IRQ chip: %d\n", ret);
5004		return ret;
5005	}
5006
5007	return 0;
5008}
5009
5010static void rt5677_free_irq(struct i2c_client *i2c)
5011{
5012	struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
5013
5014	if (rt5677->irq_data)
5015		regmap_del_irq_chip(i2c->irq, rt5677->irq_data);
5016}
5017
5018static int rt5677_i2c_probe(struct i2c_client *i2c,
5019		    const struct i2c_device_id *id)
5020{
5021	struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev);
5022	struct rt5677_priv *rt5677;
5023	int ret;
5024	unsigned int val;
5025
5026	rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
5027				GFP_KERNEL);
5028	if (rt5677 == NULL)
5029		return -ENOMEM;
5030
5031	i2c_set_clientdata(i2c, rt5677);
5032
5033	rt5677->type = id->driver_data;
5034
5035	if (pdata)
5036		rt5677->pdata = *pdata;
5037
5038	if (i2c->dev.of_node) {
5039		ret = rt5677_parse_dt(rt5677, i2c->dev.of_node);
5040		if (ret) {
5041			dev_err(&i2c->dev, "Failed to parse device tree: %d\n",
5042				ret);
5043			return ret;
5044		}
5045	} else {
5046		rt5677->pow_ldo2 = -EINVAL;
5047	}
5048
5049	if (gpio_is_valid(rt5677->pow_ldo2)) {
5050		ret = devm_gpio_request_one(&i2c->dev, rt5677->pow_ldo2,
5051					    GPIOF_OUT_INIT_HIGH,
5052					    "RT5677 POW_LDO2");
5053		if (ret < 0) {
5054			dev_err(&i2c->dev, "Failed to request POW_LDO2 %d: %d\n",
5055				rt5677->pow_ldo2, ret);
5056			return ret;
5057		}
5058		/* Wait a while until I2C bus becomes available. The datasheet
5059		 * does not specify the exact we should wait but startup
5060		 * sequence mentiones at least a few milliseconds.
5061		 */
5062		msleep(10);
5063	}
5064
5065	rt5677->regmap_physical = devm_regmap_init_i2c(i2c,
5066					&rt5677_regmap_physical);
5067	if (IS_ERR(rt5677->regmap_physical)) {
5068		ret = PTR_ERR(rt5677->regmap_physical);
5069		dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5070			ret);
5071		return ret;
5072	}
5073
5074	rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap);
5075	if (IS_ERR(rt5677->regmap)) {
5076		ret = PTR_ERR(rt5677->regmap);
5077		dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5078			ret);
5079		return ret;
5080	}
5081
5082	regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
5083	if (val != RT5677_DEVICE_ID) {
5084		dev_err(&i2c->dev,
5085			"Device with ID register %x is not rt5677\n", val);
5086		return -ENODEV;
5087	}
5088
5089	regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
5090
5091	ret = regmap_register_patch(rt5677->regmap, init_list,
5092				    ARRAY_SIZE(init_list));
5093	if (ret != 0)
5094		dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
5095
5096	if (rt5677->pdata.in1_diff)
5097		regmap_update_bits(rt5677->regmap, RT5677_IN1,
5098					RT5677_IN_DF1, RT5677_IN_DF1);
5099
5100	if (rt5677->pdata.in2_diff)
5101		regmap_update_bits(rt5677->regmap, RT5677_IN1,
5102					RT5677_IN_DF2, RT5677_IN_DF2);
5103
5104	if (rt5677->pdata.lout1_diff)
5105		regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5106					RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF);
5107
5108	if (rt5677->pdata.lout2_diff)
5109		regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5110					RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF);
5111
5112	if (rt5677->pdata.lout3_diff)
5113		regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5114					RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF);
5115
5116	if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
5117		regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
5118					RT5677_GPIO5_FUNC_MASK,
5119					RT5677_GPIO5_FUNC_DMIC);
5120		regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
5121					RT5677_GPIO5_DIR_MASK,
5122					RT5677_GPIO5_DIR_OUT);
5123	}
5124
5125	if (rt5677->pdata.micbias1_vdd_3v3)
5126		regmap_update_bits(rt5677->regmap, RT5677_MICBIAS,
5127			RT5677_MICBIAS1_CTRL_VDD_MASK,
5128			RT5677_MICBIAS1_CTRL_VDD_3_3V);
5129
5130	rt5677_init_gpio(i2c);
5131	rt5677_init_irq(i2c);
5132
5133	return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
5134				      rt5677_dai, ARRAY_SIZE(rt5677_dai));
5135}
5136
5137static int rt5677_i2c_remove(struct i2c_client *i2c)
5138{
5139	snd_soc_unregister_codec(&i2c->dev);
5140	rt5677_free_irq(i2c);
5141	rt5677_free_gpio(i2c);
5142
5143	return 0;
5144}
5145
5146static struct i2c_driver rt5677_i2c_driver = {
5147	.driver = {
5148		.name = "rt5677",
5149		.owner = THIS_MODULE,
5150	},
5151	.probe = rt5677_i2c_probe,
5152	.remove   = rt5677_i2c_remove,
5153	.id_table = rt5677_i2c_id,
5154};
5155module_i2c_driver(rt5677_i2c_driver);
5156
5157MODULE_DESCRIPTION("ASoC RT5677 driver");
5158MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
5159MODULE_LICENSE("GPL v2");
5160