1/*
2 * wm8904.c  --  WM8904 ALSA SoC Audio driver
3 *
4 * Copyright 2009-12 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/clk.h>
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/init.h>
18#include <linux/delay.h>
19#include <linux/pm.h>
20#include <linux/i2c.h>
21#include <linux/regmap.h>
22#include <linux/regulator/consumer.h>
23#include <linux/slab.h>
24#include <sound/core.h>
25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/soc.h>
28#include <sound/initval.h>
29#include <sound/tlv.h>
30#include <sound/wm8904.h>
31
32#include "wm8904.h"
33
34enum wm8904_type {
35	WM8904,
36	WM8912,
37};
38
39#define WM8904_NUM_DCS_CHANNELS 4
40
41#define WM8904_NUM_SUPPLIES 5
42static const char *wm8904_supply_names[WM8904_NUM_SUPPLIES] = {
43	"DCVDD",
44	"DBVDD",
45	"AVDD",
46	"CPVDD",
47	"MICVDD",
48};
49
50/* codec private data */
51struct wm8904_priv {
52	struct regmap *regmap;
53	struct clk *mclk;
54
55	enum wm8904_type devtype;
56
57	struct regulator_bulk_data supplies[WM8904_NUM_SUPPLIES];
58
59	struct wm8904_pdata *pdata;
60
61	int deemph;
62
63	/* Platform provided DRC configuration */
64	const char **drc_texts;
65	int drc_cfg;
66	struct soc_enum drc_enum;
67
68	/* Platform provided ReTune mobile configuration */
69	int num_retune_mobile_texts;
70	const char **retune_mobile_texts;
71	int retune_mobile_cfg;
72	struct soc_enum retune_mobile_enum;
73
74	/* FLL setup */
75	int fll_src;
76	int fll_fref;
77	int fll_fout;
78
79	/* Clocking configuration */
80	unsigned int mclk_rate;
81	int sysclk_src;
82	unsigned int sysclk_rate;
83
84	int tdm_width;
85	int tdm_slots;
86	int bclk;
87	int fs;
88
89	/* DC servo configuration - cached offset values */
90	int dcs_state[WM8904_NUM_DCS_CHANNELS];
91};
92
93static const struct reg_default wm8904_reg_defaults[] = {
94	{ 4,   0x0018 },     /* R4   - Bias Control 0 */
95	{ 5,   0x0000 },     /* R5   - VMID Control 0 */
96	{ 6,   0x0000 },     /* R6   - Mic Bias Control 0 */
97	{ 7,   0x0000 },     /* R7   - Mic Bias Control 1 */
98	{ 8,   0x0001 },     /* R8   - Analogue DAC 0 */
99	{ 9,   0x9696 },     /* R9   - mic Filter Control */
100	{ 10,  0x0001 },     /* R10  - Analogue ADC 0 */
101	{ 12,  0x0000 },     /* R12  - Power Management 0 */
102	{ 14,  0x0000 },     /* R14  - Power Management 2 */
103	{ 15,  0x0000 },     /* R15  - Power Management 3 */
104	{ 18,  0x0000 },     /* R18  - Power Management 6 */
105	{ 20,  0x945E },     /* R20  - Clock Rates 0 */
106	{ 21,  0x0C05 },     /* R21  - Clock Rates 1 */
107	{ 22,  0x0006 },     /* R22  - Clock Rates 2 */
108	{ 24,  0x0050 },     /* R24  - Audio Interface 0 */
109	{ 25,  0x000A },     /* R25  - Audio Interface 1 */
110	{ 26,  0x00E4 },     /* R26  - Audio Interface 2 */
111	{ 27,  0x0040 },     /* R27  - Audio Interface 3 */
112	{ 30,  0x00C0 },     /* R30  - DAC Digital Volume Left */
113	{ 31,  0x00C0 },     /* R31  - DAC Digital Volume Right */
114	{ 32,  0x0000 },     /* R32  - DAC Digital 0 */
115	{ 33,  0x0008 },     /* R33  - DAC Digital 1 */
116	{ 36,  0x00C0 },     /* R36  - ADC Digital Volume Left */
117	{ 37,  0x00C0 },     /* R37  - ADC Digital Volume Right */
118	{ 38,  0x0010 },     /* R38  - ADC Digital 0 */
119	{ 39,  0x0000 },     /* R39  - Digital Microphone 0 */
120	{ 40,  0x01AF },     /* R40  - DRC 0 */
121	{ 41,  0x3248 },     /* R41  - DRC 1 */
122	{ 42,  0x0000 },     /* R42  - DRC 2 */
123	{ 43,  0x0000 },     /* R43  - DRC 3 */
124	{ 44,  0x0085 },     /* R44  - Analogue Left Input 0 */
125	{ 45,  0x0085 },     /* R45  - Analogue Right Input 0 */
126	{ 46,  0x0044 },     /* R46  - Analogue Left Input 1 */
127	{ 47,  0x0044 },     /* R47  - Analogue Right Input 1 */
128	{ 57,  0x002D },     /* R57  - Analogue OUT1 Left */
129	{ 58,  0x002D },     /* R58  - Analogue OUT1 Right */
130	{ 59,  0x0039 },     /* R59  - Analogue OUT2 Left */
131	{ 60,  0x0039 },     /* R60  - Analogue OUT2 Right */
132	{ 61,  0x0000 },     /* R61  - Analogue OUT12 ZC */
133	{ 67,  0x0000 },     /* R67  - DC Servo 0 */
134	{ 69,  0xAAAA },     /* R69  - DC Servo 2 */
135	{ 71,  0xAAAA },     /* R71  - DC Servo 4 */
136	{ 72,  0xAAAA },     /* R72  - DC Servo 5 */
137	{ 90,  0x0000 },     /* R90  - Analogue HP 0 */
138	{ 94,  0x0000 },     /* R94  - Analogue Lineout 0 */
139	{ 98,  0x0000 },     /* R98  - Charge Pump 0 */
140	{ 104, 0x0004 },     /* R104 - Class W 0 */
141	{ 108, 0x0000 },     /* R108 - Write Sequencer 0 */
142	{ 109, 0x0000 },     /* R109 - Write Sequencer 1 */
143	{ 110, 0x0000 },     /* R110 - Write Sequencer 2 */
144	{ 111, 0x0000 },     /* R111 - Write Sequencer 3 */
145	{ 112, 0x0000 },     /* R112 - Write Sequencer 4 */
146	{ 116, 0x0000 },     /* R116 - FLL Control 1 */
147	{ 117, 0x0007 },     /* R117 - FLL Control 2 */
148	{ 118, 0x0000 },     /* R118 - FLL Control 3 */
149	{ 119, 0x2EE0 },     /* R119 - FLL Control 4 */
150	{ 120, 0x0004 },     /* R120 - FLL Control 5 */
151	{ 121, 0x0014 },     /* R121 - GPIO Control 1 */
152	{ 122, 0x0010 },     /* R122 - GPIO Control 2 */
153	{ 123, 0x0010 },     /* R123 - GPIO Control 3 */
154	{ 124, 0x0000 },     /* R124 - GPIO Control 4 */
155	{ 126, 0x0000 },     /* R126 - Digital Pulls */
156	{ 128, 0xFFFF },     /* R128 - Interrupt Status Mask */
157	{ 129, 0x0000 },     /* R129 - Interrupt Polarity */
158	{ 130, 0x0000 },     /* R130 - Interrupt Debounce */
159	{ 134, 0x0000 },     /* R134 - EQ1 */
160	{ 135, 0x000C },     /* R135 - EQ2 */
161	{ 136, 0x000C },     /* R136 - EQ3 */
162	{ 137, 0x000C },     /* R137 - EQ4 */
163	{ 138, 0x000C },     /* R138 - EQ5 */
164	{ 139, 0x000C },     /* R139 - EQ6 */
165	{ 140, 0x0FCA },     /* R140 - EQ7 */
166	{ 141, 0x0400 },     /* R141 - EQ8 */
167	{ 142, 0x00D8 },     /* R142 - EQ9 */
168	{ 143, 0x1EB5 },     /* R143 - EQ10 */
169	{ 144, 0xF145 },     /* R144 - EQ11 */
170	{ 145, 0x0B75 },     /* R145 - EQ12 */
171	{ 146, 0x01C5 },     /* R146 - EQ13 */
172	{ 147, 0x1C58 },     /* R147 - EQ14 */
173	{ 148, 0xF373 },     /* R148 - EQ15 */
174	{ 149, 0x0A54 },     /* R149 - EQ16 */
175	{ 150, 0x0558 },     /* R150 - EQ17 */
176	{ 151, 0x168E },     /* R151 - EQ18 */
177	{ 152, 0xF829 },     /* R152 - EQ19 */
178	{ 153, 0x07AD },     /* R153 - EQ20 */
179	{ 154, 0x1103 },     /* R154 - EQ21 */
180	{ 155, 0x0564 },     /* R155 - EQ22 */
181	{ 156, 0x0559 },     /* R156 - EQ23 */
182	{ 157, 0x4000 },     /* R157 - EQ24 */
183	{ 161, 0x0000 },     /* R161 - Control Interface Test 1 */
184	{ 204, 0x0000 },     /* R204 - Analogue Output Bias 0 */
185	{ 247, 0x0000 },     /* R247 - FLL NCO Test 0 */
186	{ 248, 0x0019 },     /* R248 - FLL NCO Test 1 */
187};
188
189static bool wm8904_volatile_register(struct device *dev, unsigned int reg)
190{
191	switch (reg) {
192	case WM8904_SW_RESET_AND_ID:
193	case WM8904_REVISION:
194	case WM8904_DC_SERVO_1:
195	case WM8904_DC_SERVO_6:
196	case WM8904_DC_SERVO_7:
197	case WM8904_DC_SERVO_8:
198	case WM8904_DC_SERVO_9:
199	case WM8904_DC_SERVO_READBACK_0:
200	case WM8904_INTERRUPT_STATUS:
201		return true;
202	default:
203		return false;
204	}
205}
206
207static bool wm8904_readable_register(struct device *dev, unsigned int reg)
208{
209	switch (reg) {
210	case WM8904_SW_RESET_AND_ID:
211	case WM8904_REVISION:
212	case WM8904_BIAS_CONTROL_0:
213	case WM8904_VMID_CONTROL_0:
214	case WM8904_MIC_BIAS_CONTROL_0:
215	case WM8904_MIC_BIAS_CONTROL_1:
216	case WM8904_ANALOGUE_DAC_0:
217	case WM8904_MIC_FILTER_CONTROL:
218	case WM8904_ANALOGUE_ADC_0:
219	case WM8904_POWER_MANAGEMENT_0:
220	case WM8904_POWER_MANAGEMENT_2:
221	case WM8904_POWER_MANAGEMENT_3:
222	case WM8904_POWER_MANAGEMENT_6:
223	case WM8904_CLOCK_RATES_0:
224	case WM8904_CLOCK_RATES_1:
225	case WM8904_CLOCK_RATES_2:
226	case WM8904_AUDIO_INTERFACE_0:
227	case WM8904_AUDIO_INTERFACE_1:
228	case WM8904_AUDIO_INTERFACE_2:
229	case WM8904_AUDIO_INTERFACE_3:
230	case WM8904_DAC_DIGITAL_VOLUME_LEFT:
231	case WM8904_DAC_DIGITAL_VOLUME_RIGHT:
232	case WM8904_DAC_DIGITAL_0:
233	case WM8904_DAC_DIGITAL_1:
234	case WM8904_ADC_DIGITAL_VOLUME_LEFT:
235	case WM8904_ADC_DIGITAL_VOLUME_RIGHT:
236	case WM8904_ADC_DIGITAL_0:
237	case WM8904_DIGITAL_MICROPHONE_0:
238	case WM8904_DRC_0:
239	case WM8904_DRC_1:
240	case WM8904_DRC_2:
241	case WM8904_DRC_3:
242	case WM8904_ANALOGUE_LEFT_INPUT_0:
243	case WM8904_ANALOGUE_RIGHT_INPUT_0:
244	case WM8904_ANALOGUE_LEFT_INPUT_1:
245	case WM8904_ANALOGUE_RIGHT_INPUT_1:
246	case WM8904_ANALOGUE_OUT1_LEFT:
247	case WM8904_ANALOGUE_OUT1_RIGHT:
248	case WM8904_ANALOGUE_OUT2_LEFT:
249	case WM8904_ANALOGUE_OUT2_RIGHT:
250	case WM8904_ANALOGUE_OUT12_ZC:
251	case WM8904_DC_SERVO_0:
252	case WM8904_DC_SERVO_1:
253	case WM8904_DC_SERVO_2:
254	case WM8904_DC_SERVO_4:
255	case WM8904_DC_SERVO_5:
256	case WM8904_DC_SERVO_6:
257	case WM8904_DC_SERVO_7:
258	case WM8904_DC_SERVO_8:
259	case WM8904_DC_SERVO_9:
260	case WM8904_DC_SERVO_READBACK_0:
261	case WM8904_ANALOGUE_HP_0:
262	case WM8904_ANALOGUE_LINEOUT_0:
263	case WM8904_CHARGE_PUMP_0:
264	case WM8904_CLASS_W_0:
265	case WM8904_WRITE_SEQUENCER_0:
266	case WM8904_WRITE_SEQUENCER_1:
267	case WM8904_WRITE_SEQUENCER_2:
268	case WM8904_WRITE_SEQUENCER_3:
269	case WM8904_WRITE_SEQUENCER_4:
270	case WM8904_FLL_CONTROL_1:
271	case WM8904_FLL_CONTROL_2:
272	case WM8904_FLL_CONTROL_3:
273	case WM8904_FLL_CONTROL_4:
274	case WM8904_FLL_CONTROL_5:
275	case WM8904_GPIO_CONTROL_1:
276	case WM8904_GPIO_CONTROL_2:
277	case WM8904_GPIO_CONTROL_3:
278	case WM8904_GPIO_CONTROL_4:
279	case WM8904_DIGITAL_PULLS:
280	case WM8904_INTERRUPT_STATUS:
281	case WM8904_INTERRUPT_STATUS_MASK:
282	case WM8904_INTERRUPT_POLARITY:
283	case WM8904_INTERRUPT_DEBOUNCE:
284	case WM8904_EQ1:
285	case WM8904_EQ2:
286	case WM8904_EQ3:
287	case WM8904_EQ4:
288	case WM8904_EQ5:
289	case WM8904_EQ6:
290	case WM8904_EQ7:
291	case WM8904_EQ8:
292	case WM8904_EQ9:
293	case WM8904_EQ10:
294	case WM8904_EQ11:
295	case WM8904_EQ12:
296	case WM8904_EQ13:
297	case WM8904_EQ14:
298	case WM8904_EQ15:
299	case WM8904_EQ16:
300	case WM8904_EQ17:
301	case WM8904_EQ18:
302	case WM8904_EQ19:
303	case WM8904_EQ20:
304	case WM8904_EQ21:
305	case WM8904_EQ22:
306	case WM8904_EQ23:
307	case WM8904_EQ24:
308	case WM8904_CONTROL_INTERFACE_TEST_1:
309	case WM8904_ADC_TEST_0:
310	case WM8904_ANALOGUE_OUTPUT_BIAS_0:
311	case WM8904_FLL_NCO_TEST_0:
312	case WM8904_FLL_NCO_TEST_1:
313		return true;
314	default:
315		return true;
316	}
317}
318
319static int wm8904_configure_clocking(struct snd_soc_codec *codec)
320{
321	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
322	unsigned int clock0, clock2, rate;
323
324	/* Gate the clock while we're updating to avoid misclocking */
325	clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2);
326	snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
327			    WM8904_SYSCLK_SRC, 0);
328
329	/* This should be done on init() for bypass paths */
330	switch (wm8904->sysclk_src) {
331	case WM8904_CLK_MCLK:
332		dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8904->mclk_rate);
333
334		clock2 &= ~WM8904_SYSCLK_SRC;
335		rate = wm8904->mclk_rate;
336
337		/* Ensure the FLL is stopped */
338		snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
339				    WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
340		break;
341
342	case WM8904_CLK_FLL:
343		dev_dbg(codec->dev, "Using %dHz FLL clock\n",
344			wm8904->fll_fout);
345
346		clock2 |= WM8904_SYSCLK_SRC;
347		rate = wm8904->fll_fout;
348		break;
349
350	default:
351		dev_err(codec->dev, "System clock not configured\n");
352		return -EINVAL;
353	}
354
355	/* SYSCLK shouldn't be over 13.5MHz */
356	if (rate > 13500000) {
357		clock0 = WM8904_MCLK_DIV;
358		wm8904->sysclk_rate = rate / 2;
359	} else {
360		clock0 = 0;
361		wm8904->sysclk_rate = rate;
362	}
363
364	snd_soc_update_bits(codec, WM8904_CLOCK_RATES_0, WM8904_MCLK_DIV,
365			    clock0);
366
367	snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
368			    WM8904_CLK_SYS_ENA | WM8904_SYSCLK_SRC, clock2);
369
370	dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8904->sysclk_rate);
371
372	return 0;
373}
374
375static void wm8904_set_drc(struct snd_soc_codec *codec)
376{
377	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
378	struct wm8904_pdata *pdata = wm8904->pdata;
379	int save, i;
380
381	/* Save any enables; the configuration should clear them. */
382	save = snd_soc_read(codec, WM8904_DRC_0);
383
384	for (i = 0; i < WM8904_DRC_REGS; i++)
385		snd_soc_update_bits(codec, WM8904_DRC_0 + i, 0xffff,
386				    pdata->drc_cfgs[wm8904->drc_cfg].regs[i]);
387
388	/* Reenable the DRC */
389	snd_soc_update_bits(codec, WM8904_DRC_0,
390			    WM8904_DRC_ENA | WM8904_DRC_DAC_PATH, save);
391}
392
393static int wm8904_put_drc_enum(struct snd_kcontrol *kcontrol,
394			       struct snd_ctl_elem_value *ucontrol)
395{
396	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
397	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
398	struct wm8904_pdata *pdata = wm8904->pdata;
399	int value = ucontrol->value.integer.value[0];
400
401	if (value >= pdata->num_drc_cfgs)
402		return -EINVAL;
403
404	wm8904->drc_cfg = value;
405
406	wm8904_set_drc(codec);
407
408	return 0;
409}
410
411static int wm8904_get_drc_enum(struct snd_kcontrol *kcontrol,
412			       struct snd_ctl_elem_value *ucontrol)
413{
414	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
415	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
416
417	ucontrol->value.enumerated.item[0] = wm8904->drc_cfg;
418
419	return 0;
420}
421
422static void wm8904_set_retune_mobile(struct snd_soc_codec *codec)
423{
424	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
425	struct wm8904_pdata *pdata = wm8904->pdata;
426	int best, best_val, save, i, cfg;
427
428	if (!pdata || !wm8904->num_retune_mobile_texts)
429		return;
430
431	/* Find the version of the currently selected configuration
432	 * with the nearest sample rate. */
433	cfg = wm8904->retune_mobile_cfg;
434	best = 0;
435	best_val = INT_MAX;
436	for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
437		if (strcmp(pdata->retune_mobile_cfgs[i].name,
438			   wm8904->retune_mobile_texts[cfg]) == 0 &&
439		    abs(pdata->retune_mobile_cfgs[i].rate
440			- wm8904->fs) < best_val) {
441			best = i;
442			best_val = abs(pdata->retune_mobile_cfgs[i].rate
443				       - wm8904->fs);
444		}
445	}
446
447	dev_dbg(codec->dev, "ReTune Mobile %s/%dHz for %dHz sample rate\n",
448		pdata->retune_mobile_cfgs[best].name,
449		pdata->retune_mobile_cfgs[best].rate,
450		wm8904->fs);
451
452	/* The EQ will be disabled while reconfiguring it, remember the
453	 * current configuration.
454	 */
455	save = snd_soc_read(codec, WM8904_EQ1);
456
457	for (i = 0; i < WM8904_EQ_REGS; i++)
458		snd_soc_update_bits(codec, WM8904_EQ1 + i, 0xffff,
459				pdata->retune_mobile_cfgs[best].regs[i]);
460
461	snd_soc_update_bits(codec, WM8904_EQ1, WM8904_EQ_ENA, save);
462}
463
464static int wm8904_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
465					 struct snd_ctl_elem_value *ucontrol)
466{
467	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
468	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
469	struct wm8904_pdata *pdata = wm8904->pdata;
470	int value = ucontrol->value.integer.value[0];
471
472	if (value >= pdata->num_retune_mobile_cfgs)
473		return -EINVAL;
474
475	wm8904->retune_mobile_cfg = value;
476
477	wm8904_set_retune_mobile(codec);
478
479	return 0;
480}
481
482static int wm8904_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
483					 struct snd_ctl_elem_value *ucontrol)
484{
485	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
486	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
487
488	ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg;
489
490	return 0;
491}
492
493static int deemph_settings[] = { 0, 32000, 44100, 48000 };
494
495static int wm8904_set_deemph(struct snd_soc_codec *codec)
496{
497	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
498	int val, i, best;
499
500	/* If we're using deemphasis select the nearest available sample
501	 * rate.
502	 */
503	if (wm8904->deemph) {
504		best = 1;
505		for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
506			if (abs(deemph_settings[i] - wm8904->fs) <
507			    abs(deemph_settings[best] - wm8904->fs))
508				best = i;
509		}
510
511		val = best << WM8904_DEEMPH_SHIFT;
512	} else {
513		val = 0;
514	}
515
516	dev_dbg(codec->dev, "Set deemphasis %d\n", val);
517
518	return snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1,
519				   WM8904_DEEMPH_MASK, val);
520}
521
522static int wm8904_get_deemph(struct snd_kcontrol *kcontrol,
523			     struct snd_ctl_elem_value *ucontrol)
524{
525	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
526	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
527
528	ucontrol->value.integer.value[0] = wm8904->deemph;
529	return 0;
530}
531
532static int wm8904_put_deemph(struct snd_kcontrol *kcontrol,
533			      struct snd_ctl_elem_value *ucontrol)
534{
535	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
536	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
537	int deemph = ucontrol->value.integer.value[0];
538
539	if (deemph > 1)
540		return -EINVAL;
541
542	wm8904->deemph = deemph;
543
544	return wm8904_set_deemph(codec);
545}
546
547static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
548static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
549static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
550static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
551static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
552
553static const char *input_mode_text[] = {
554	"Single-Ended", "Differential Line", "Differential Mic"
555};
556
557static SOC_ENUM_SINGLE_DECL(lin_mode,
558			    WM8904_ANALOGUE_LEFT_INPUT_1, 0,
559			    input_mode_text);
560
561static SOC_ENUM_SINGLE_DECL(rin_mode,
562			    WM8904_ANALOGUE_RIGHT_INPUT_1, 0,
563			    input_mode_text);
564
565static const char *hpf_mode_text[] = {
566	"Hi-fi", "Voice 1", "Voice 2", "Voice 3"
567};
568
569static SOC_ENUM_SINGLE_DECL(hpf_mode, WM8904_ADC_DIGITAL_0, 5,
570			    hpf_mode_text);
571
572static int wm8904_adc_osr_put(struct snd_kcontrol *kcontrol,
573			      struct snd_ctl_elem_value *ucontrol)
574{
575	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
576	unsigned int val;
577	int ret;
578
579	ret = snd_soc_put_volsw(kcontrol, ucontrol);
580	if (ret < 0)
581		return ret;
582
583	if (ucontrol->value.integer.value[0])
584		val = 0;
585	else
586		val = WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5;
587
588	snd_soc_update_bits(codec, WM8904_ADC_TEST_0,
589			    WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5,
590			    val);
591
592	return ret;
593}
594
595static const struct snd_kcontrol_new wm8904_adc_snd_controls[] = {
596SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8904_ADC_DIGITAL_VOLUME_LEFT,
597		 WM8904_ADC_DIGITAL_VOLUME_RIGHT, 1, 119, 0, digital_tlv),
598
599SOC_ENUM("Left Caputure Mode", lin_mode),
600SOC_ENUM("Right Capture Mode", rin_mode),
601
602/* No TLV since it depends on mode */
603SOC_DOUBLE_R("Capture Volume", WM8904_ANALOGUE_LEFT_INPUT_0,
604	     WM8904_ANALOGUE_RIGHT_INPUT_0, 0, 31, 0),
605SOC_DOUBLE_R("Capture Switch", WM8904_ANALOGUE_LEFT_INPUT_0,
606	     WM8904_ANALOGUE_RIGHT_INPUT_0, 7, 1, 1),
607
608SOC_SINGLE("High Pass Filter Switch", WM8904_ADC_DIGITAL_0, 4, 1, 0),
609SOC_ENUM("High Pass Filter Mode", hpf_mode),
610SOC_SINGLE_EXT("ADC 128x OSR Switch", WM8904_ANALOGUE_ADC_0, 0, 1, 0,
611	snd_soc_get_volsw, wm8904_adc_osr_put),
612};
613
614static const char *drc_path_text[] = {
615	"ADC", "DAC"
616};
617
618static SOC_ENUM_SINGLE_DECL(drc_path, WM8904_DRC_0, 14, drc_path_text);
619
620static const struct snd_kcontrol_new wm8904_dac_snd_controls[] = {
621SOC_SINGLE_TLV("Digital Playback Boost Volume",
622	       WM8904_AUDIO_INTERFACE_0, 9, 3, 0, dac_boost_tlv),
623SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8904_DAC_DIGITAL_VOLUME_LEFT,
624		 WM8904_DAC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
625
626SOC_DOUBLE_R_TLV("Headphone Volume", WM8904_ANALOGUE_OUT1_LEFT,
627		 WM8904_ANALOGUE_OUT1_RIGHT, 0, 63, 0, out_tlv),
628SOC_DOUBLE_R("Headphone Switch", WM8904_ANALOGUE_OUT1_LEFT,
629	     WM8904_ANALOGUE_OUT1_RIGHT, 8, 1, 1),
630SOC_DOUBLE_R("Headphone ZC Switch", WM8904_ANALOGUE_OUT1_LEFT,
631	     WM8904_ANALOGUE_OUT1_RIGHT, 6, 1, 0),
632
633SOC_DOUBLE_R_TLV("Line Output Volume", WM8904_ANALOGUE_OUT2_LEFT,
634		 WM8904_ANALOGUE_OUT2_RIGHT, 0, 63, 0, out_tlv),
635SOC_DOUBLE_R("Line Output Switch", WM8904_ANALOGUE_OUT2_LEFT,
636	     WM8904_ANALOGUE_OUT2_RIGHT, 8, 1, 1),
637SOC_DOUBLE_R("Line Output ZC Switch", WM8904_ANALOGUE_OUT2_LEFT,
638	     WM8904_ANALOGUE_OUT2_RIGHT, 6, 1, 0),
639
640SOC_SINGLE("EQ Switch", WM8904_EQ1, 0, 1, 0),
641SOC_SINGLE("DRC Switch", WM8904_DRC_0, 15, 1, 0),
642SOC_ENUM("DRC Path", drc_path),
643SOC_SINGLE("DAC OSRx2 Switch", WM8904_DAC_DIGITAL_1, 6, 1, 0),
644SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
645		    wm8904_get_deemph, wm8904_put_deemph),
646};
647
648static const struct snd_kcontrol_new wm8904_snd_controls[] = {
649SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8904_DAC_DIGITAL_0, 4, 8, 15, 0,
650	       sidetone_tlv),
651};
652
653static const struct snd_kcontrol_new wm8904_eq_controls[] = {
654SOC_SINGLE_TLV("EQ1 Volume", WM8904_EQ2, 0, 24, 0, eq_tlv),
655SOC_SINGLE_TLV("EQ2 Volume", WM8904_EQ3, 0, 24, 0, eq_tlv),
656SOC_SINGLE_TLV("EQ3 Volume", WM8904_EQ4, 0, 24, 0, eq_tlv),
657SOC_SINGLE_TLV("EQ4 Volume", WM8904_EQ5, 0, 24, 0, eq_tlv),
658SOC_SINGLE_TLV("EQ5 Volume", WM8904_EQ6, 0, 24, 0, eq_tlv),
659};
660
661static int cp_event(struct snd_soc_dapm_widget *w,
662		    struct snd_kcontrol *kcontrol, int event)
663{
664	if (WARN_ON(event != SND_SOC_DAPM_POST_PMU))
665		return -EINVAL;
666
667	/* Maximum startup time */
668	udelay(500);
669
670	return 0;
671}
672
673static int sysclk_event(struct snd_soc_dapm_widget *w,
674			 struct snd_kcontrol *kcontrol, int event)
675{
676	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
677	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
678
679	switch (event) {
680	case SND_SOC_DAPM_PRE_PMU:
681		/* If we're using the FLL then we only start it when
682		 * required; we assume that the configuration has been
683		 * done previously and all we need to do is kick it
684		 * off.
685		 */
686		switch (wm8904->sysclk_src) {
687		case WM8904_CLK_FLL:
688			snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
689					    WM8904_FLL_OSC_ENA,
690					    WM8904_FLL_OSC_ENA);
691
692			snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
693					    WM8904_FLL_ENA,
694					    WM8904_FLL_ENA);
695			break;
696
697		default:
698			break;
699		}
700		break;
701
702	case SND_SOC_DAPM_POST_PMD:
703		snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
704				    WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
705		break;
706	}
707
708	return 0;
709}
710
711static int out_pga_event(struct snd_soc_dapm_widget *w,
712			 struct snd_kcontrol *kcontrol, int event)
713{
714	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
715	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
716	int reg, val;
717	int dcs_mask;
718	int dcs_l, dcs_r;
719	int dcs_l_reg, dcs_r_reg;
720	int timeout;
721	int pwr_reg;
722
723	/* This code is shared between HP and LINEOUT; we do all our
724	 * power management in stereo pairs to avoid latency issues so
725	 * we reuse shift to identify which rather than strcmp() the
726	 * name. */
727	reg = w->shift;
728
729	switch (reg) {
730	case WM8904_ANALOGUE_HP_0:
731		pwr_reg = WM8904_POWER_MANAGEMENT_2;
732		dcs_mask = WM8904_DCS_ENA_CHAN_0 | WM8904_DCS_ENA_CHAN_1;
733		dcs_r_reg = WM8904_DC_SERVO_8;
734		dcs_l_reg = WM8904_DC_SERVO_9;
735		dcs_l = 0;
736		dcs_r = 1;
737		break;
738	case WM8904_ANALOGUE_LINEOUT_0:
739		pwr_reg = WM8904_POWER_MANAGEMENT_3;
740		dcs_mask = WM8904_DCS_ENA_CHAN_2 | WM8904_DCS_ENA_CHAN_3;
741		dcs_r_reg = WM8904_DC_SERVO_6;
742		dcs_l_reg = WM8904_DC_SERVO_7;
743		dcs_l = 2;
744		dcs_r = 3;
745		break;
746	default:
747		WARN(1, "Invalid reg %d\n", reg);
748		return -EINVAL;
749	}
750
751	switch (event) {
752	case SND_SOC_DAPM_PRE_PMU:
753		/* Power on the PGAs */
754		snd_soc_update_bits(codec, pwr_reg,
755				    WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA,
756				    WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA);
757
758		/* Power on the amplifier */
759		snd_soc_update_bits(codec, reg,
760				    WM8904_HPL_ENA | WM8904_HPR_ENA,
761				    WM8904_HPL_ENA | WM8904_HPR_ENA);
762
763
764		/* Enable the first stage */
765		snd_soc_update_bits(codec, reg,
766				    WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY,
767				    WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY);
768
769		/* Power up the DC servo */
770		snd_soc_update_bits(codec, WM8904_DC_SERVO_0,
771				    dcs_mask, dcs_mask);
772
773		/* Either calibrate the DC servo or restore cached state
774		 * if we have that.
775		 */
776		if (wm8904->dcs_state[dcs_l] || wm8904->dcs_state[dcs_r]) {
777			dev_dbg(codec->dev, "Restoring DC servo state\n");
778
779			snd_soc_write(codec, dcs_l_reg,
780				      wm8904->dcs_state[dcs_l]);
781			snd_soc_write(codec, dcs_r_reg,
782				      wm8904->dcs_state[dcs_r]);
783
784			snd_soc_write(codec, WM8904_DC_SERVO_1, dcs_mask);
785
786			timeout = 20;
787		} else {
788			dev_dbg(codec->dev, "Calibrating DC servo\n");
789
790			snd_soc_write(codec, WM8904_DC_SERVO_1,
791				dcs_mask << WM8904_DCS_TRIG_STARTUP_0_SHIFT);
792
793			timeout = 500;
794		}
795
796		/* Wait for DC servo to complete */
797		dcs_mask <<= WM8904_DCS_CAL_COMPLETE_SHIFT;
798		do {
799			val = snd_soc_read(codec, WM8904_DC_SERVO_READBACK_0);
800			if ((val & dcs_mask) == dcs_mask)
801				break;
802
803			msleep(1);
804		} while (--timeout);
805
806		if ((val & dcs_mask) != dcs_mask)
807			dev_warn(codec->dev, "DC servo timed out\n");
808		else
809			dev_dbg(codec->dev, "DC servo ready\n");
810
811		/* Enable the output stage */
812		snd_soc_update_bits(codec, reg,
813				    WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
814				    WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP);
815		break;
816
817	case SND_SOC_DAPM_POST_PMU:
818		/* Unshort the output itself */
819		snd_soc_update_bits(codec, reg,
820				    WM8904_HPL_RMV_SHORT |
821				    WM8904_HPR_RMV_SHORT,
822				    WM8904_HPL_RMV_SHORT |
823				    WM8904_HPR_RMV_SHORT);
824
825		break;
826
827	case SND_SOC_DAPM_PRE_PMD:
828		/* Short the output */
829		snd_soc_update_bits(codec, reg,
830				    WM8904_HPL_RMV_SHORT |
831				    WM8904_HPR_RMV_SHORT, 0);
832		break;
833
834	case SND_SOC_DAPM_POST_PMD:
835		/* Cache the DC servo configuration; this will be
836		 * invalidated if we change the configuration. */
837		wm8904->dcs_state[dcs_l] = snd_soc_read(codec, dcs_l_reg);
838		wm8904->dcs_state[dcs_r] = snd_soc_read(codec, dcs_r_reg);
839
840		snd_soc_update_bits(codec, WM8904_DC_SERVO_0,
841				    dcs_mask, 0);
842
843		/* Disable the amplifier input and output stages */
844		snd_soc_update_bits(codec, reg,
845				    WM8904_HPL_ENA | WM8904_HPR_ENA |
846				    WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY |
847				    WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
848				    0);
849
850		/* PGAs too */
851		snd_soc_update_bits(codec, pwr_reg,
852				    WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA,
853				    0);
854		break;
855	}
856
857	return 0;
858}
859
860static const char *lin_text[] = {
861	"IN1L", "IN2L", "IN3L"
862};
863
864static SOC_ENUM_SINGLE_DECL(lin_enum, WM8904_ANALOGUE_LEFT_INPUT_1, 2,
865			    lin_text);
866
867static const struct snd_kcontrol_new lin_mux =
868	SOC_DAPM_ENUM("Left Capture Mux", lin_enum);
869
870static SOC_ENUM_SINGLE_DECL(lin_inv_enum, WM8904_ANALOGUE_LEFT_INPUT_1, 4,
871			    lin_text);
872
873static const struct snd_kcontrol_new lin_inv_mux =
874	SOC_DAPM_ENUM("Left Capture Inveting Mux", lin_inv_enum);
875
876static const char *rin_text[] = {
877	"IN1R", "IN2R", "IN3R"
878};
879
880static SOC_ENUM_SINGLE_DECL(rin_enum, WM8904_ANALOGUE_RIGHT_INPUT_1, 2,
881			    rin_text);
882
883static const struct snd_kcontrol_new rin_mux =
884	SOC_DAPM_ENUM("Right Capture Mux", rin_enum);
885
886static SOC_ENUM_SINGLE_DECL(rin_inv_enum, WM8904_ANALOGUE_RIGHT_INPUT_1, 4,
887			    rin_text);
888
889static const struct snd_kcontrol_new rin_inv_mux =
890	SOC_DAPM_ENUM("Right Capture Inveting Mux", rin_inv_enum);
891
892static const char *aif_text[] = {
893	"Left", "Right"
894};
895
896static SOC_ENUM_SINGLE_DECL(aifoutl_enum, WM8904_AUDIO_INTERFACE_0, 7,
897			    aif_text);
898
899static const struct snd_kcontrol_new aifoutl_mux =
900	SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum);
901
902static SOC_ENUM_SINGLE_DECL(aifoutr_enum, WM8904_AUDIO_INTERFACE_0, 6,
903			    aif_text);
904
905static const struct snd_kcontrol_new aifoutr_mux =
906	SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum);
907
908static SOC_ENUM_SINGLE_DECL(aifinl_enum, WM8904_AUDIO_INTERFACE_0, 5,
909			    aif_text);
910
911static const struct snd_kcontrol_new aifinl_mux =
912	SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum);
913
914static SOC_ENUM_SINGLE_DECL(aifinr_enum, WM8904_AUDIO_INTERFACE_0, 4,
915			    aif_text);
916
917static const struct snd_kcontrol_new aifinr_mux =
918	SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum);
919
920static const struct snd_soc_dapm_widget wm8904_core_dapm_widgets[] = {
921SND_SOC_DAPM_SUPPLY("SYSCLK", WM8904_CLOCK_RATES_2, 2, 0, sysclk_event,
922		    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
923SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8904_CLOCK_RATES_2, 1, 0, NULL, 0),
924SND_SOC_DAPM_SUPPLY("TOCLK", WM8904_CLOCK_RATES_2, 0, 0, NULL, 0),
925};
926
927static const struct snd_soc_dapm_widget wm8904_adc_dapm_widgets[] = {
928SND_SOC_DAPM_INPUT("IN1L"),
929SND_SOC_DAPM_INPUT("IN1R"),
930SND_SOC_DAPM_INPUT("IN2L"),
931SND_SOC_DAPM_INPUT("IN2R"),
932SND_SOC_DAPM_INPUT("IN3L"),
933SND_SOC_DAPM_INPUT("IN3R"),
934
935SND_SOC_DAPM_SUPPLY("MICBIAS", WM8904_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0),
936
937SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lin_mux),
938SND_SOC_DAPM_MUX("Left Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
939		 &lin_inv_mux),
940SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rin_mux),
941SND_SOC_DAPM_MUX("Right Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
942		 &rin_inv_mux),
943
944SND_SOC_DAPM_PGA("Left Capture PGA", WM8904_POWER_MANAGEMENT_0, 1, 0,
945		 NULL, 0),
946SND_SOC_DAPM_PGA("Right Capture PGA", WM8904_POWER_MANAGEMENT_0, 0, 0,
947		 NULL, 0),
948
949SND_SOC_DAPM_ADC("ADCL", NULL, WM8904_POWER_MANAGEMENT_6, 1, 0),
950SND_SOC_DAPM_ADC("ADCR", NULL, WM8904_POWER_MANAGEMENT_6, 0, 0),
951
952SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux),
953SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux),
954
955SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
956SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
957};
958
959static const struct snd_soc_dapm_widget wm8904_dac_dapm_widgets[] = {
960SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
961SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
962
963SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux),
964SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux),
965
966SND_SOC_DAPM_DAC("DACL", NULL, WM8904_POWER_MANAGEMENT_6, 3, 0),
967SND_SOC_DAPM_DAC("DACR", NULL, WM8904_POWER_MANAGEMENT_6, 2, 0),
968
969SND_SOC_DAPM_SUPPLY("Charge pump", WM8904_CHARGE_PUMP_0, 0, 0, cp_event,
970		    SND_SOC_DAPM_POST_PMU),
971
972SND_SOC_DAPM_PGA("HPL PGA", SND_SOC_NOPM, 1, 0, NULL, 0),
973SND_SOC_DAPM_PGA("HPR PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
974
975SND_SOC_DAPM_PGA("LINEL PGA", SND_SOC_NOPM, 1, 0, NULL, 0),
976SND_SOC_DAPM_PGA("LINER PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
977
978SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM, WM8904_ANALOGUE_HP_0,
979		   0, NULL, 0, out_pga_event,
980		   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
981		   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
982SND_SOC_DAPM_PGA_E("Line Output", SND_SOC_NOPM, WM8904_ANALOGUE_LINEOUT_0,
983		   0, NULL, 0, out_pga_event,
984		   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
985		   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
986
987SND_SOC_DAPM_OUTPUT("HPOUTL"),
988SND_SOC_DAPM_OUTPUT("HPOUTR"),
989SND_SOC_DAPM_OUTPUT("LINEOUTL"),
990SND_SOC_DAPM_OUTPUT("LINEOUTR"),
991};
992
993static const char *out_mux_text[] = {
994	"DAC", "Bypass"
995};
996
997static SOC_ENUM_SINGLE_DECL(hpl_enum, WM8904_ANALOGUE_OUT12_ZC, 3,
998			    out_mux_text);
999
1000static const struct snd_kcontrol_new hpl_mux =
1001	SOC_DAPM_ENUM("HPL Mux", hpl_enum);
1002
1003static SOC_ENUM_SINGLE_DECL(hpr_enum, WM8904_ANALOGUE_OUT12_ZC, 2,
1004			    out_mux_text);
1005
1006static const struct snd_kcontrol_new hpr_mux =
1007	SOC_DAPM_ENUM("HPR Mux", hpr_enum);
1008
1009static SOC_ENUM_SINGLE_DECL(linel_enum, WM8904_ANALOGUE_OUT12_ZC, 1,
1010			    out_mux_text);
1011
1012static const struct snd_kcontrol_new linel_mux =
1013	SOC_DAPM_ENUM("LINEL Mux", linel_enum);
1014
1015static SOC_ENUM_SINGLE_DECL(liner_enum, WM8904_ANALOGUE_OUT12_ZC, 0,
1016			    out_mux_text);
1017
1018static const struct snd_kcontrol_new liner_mux =
1019	SOC_DAPM_ENUM("LINER Mux", liner_enum);
1020
1021static const char *sidetone_text[] = {
1022	"None", "Left", "Right"
1023};
1024
1025static SOC_ENUM_SINGLE_DECL(dacl_sidetone_enum, WM8904_DAC_DIGITAL_0, 2,
1026			    sidetone_text);
1027
1028static const struct snd_kcontrol_new dacl_sidetone_mux =
1029	SOC_DAPM_ENUM("Left Sidetone Mux", dacl_sidetone_enum);
1030
1031static SOC_ENUM_SINGLE_DECL(dacr_sidetone_enum, WM8904_DAC_DIGITAL_0, 0,
1032			    sidetone_text);
1033
1034static const struct snd_kcontrol_new dacr_sidetone_mux =
1035	SOC_DAPM_ENUM("Right Sidetone Mux", dacr_sidetone_enum);
1036
1037static const struct snd_soc_dapm_widget wm8904_dapm_widgets[] = {
1038SND_SOC_DAPM_SUPPLY("Class G", WM8904_CLASS_W_0, 0, 1, NULL, 0),
1039SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
1040SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
1041
1042SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &dacl_sidetone_mux),
1043SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &dacr_sidetone_mux),
1044
1045SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1046SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1047SND_SOC_DAPM_MUX("LINEL Mux", SND_SOC_NOPM, 0, 0, &linel_mux),
1048SND_SOC_DAPM_MUX("LINER Mux", SND_SOC_NOPM, 0, 0, &liner_mux),
1049};
1050
1051static const struct snd_soc_dapm_route core_intercon[] = {
1052	{ "CLK_DSP", NULL, "SYSCLK" },
1053	{ "TOCLK", NULL, "SYSCLK" },
1054};
1055
1056static const struct snd_soc_dapm_route adc_intercon[] = {
1057	{ "Left Capture Mux", "IN1L", "IN1L" },
1058	{ "Left Capture Mux", "IN2L", "IN2L" },
1059	{ "Left Capture Mux", "IN3L", "IN3L" },
1060
1061	{ "Left Capture Inverting Mux", "IN1L", "IN1L" },
1062	{ "Left Capture Inverting Mux", "IN2L", "IN2L" },
1063	{ "Left Capture Inverting Mux", "IN3L", "IN3L" },
1064
1065	{ "Right Capture Mux", "IN1R", "IN1R" },
1066	{ "Right Capture Mux", "IN2R", "IN2R" },
1067	{ "Right Capture Mux", "IN3R", "IN3R" },
1068
1069	{ "Right Capture Inverting Mux", "IN1R", "IN1R" },
1070	{ "Right Capture Inverting Mux", "IN2R", "IN2R" },
1071	{ "Right Capture Inverting Mux", "IN3R", "IN3R" },
1072
1073	{ "Left Capture PGA", NULL, "Left Capture Mux" },
1074	{ "Left Capture PGA", NULL, "Left Capture Inverting Mux" },
1075
1076	{ "Right Capture PGA", NULL, "Right Capture Mux" },
1077	{ "Right Capture PGA", NULL, "Right Capture Inverting Mux" },
1078
1079	{ "AIFOUTL Mux", "Left", "ADCL" },
1080	{ "AIFOUTL Mux", "Right", "ADCR" },
1081	{ "AIFOUTR Mux", "Left", "ADCL" },
1082	{ "AIFOUTR Mux", "Right", "ADCR" },
1083
1084	{ "AIFOUTL", NULL, "AIFOUTL Mux" },
1085	{ "AIFOUTR", NULL, "AIFOUTR Mux" },
1086
1087	{ "ADCL", NULL, "CLK_DSP" },
1088	{ "ADCL", NULL, "Left Capture PGA" },
1089
1090	{ "ADCR", NULL, "CLK_DSP" },
1091	{ "ADCR", NULL, "Right Capture PGA" },
1092};
1093
1094static const struct snd_soc_dapm_route dac_intercon[] = {
1095	{ "DACL Mux", "Left", "AIFINL" },
1096	{ "DACL Mux", "Right", "AIFINR" },
1097
1098	{ "DACR Mux", "Left", "AIFINL" },
1099	{ "DACR Mux", "Right", "AIFINR" },
1100
1101	{ "DACL", NULL, "DACL Mux" },
1102	{ "DACL", NULL, "CLK_DSP" },
1103
1104	{ "DACR", NULL, "DACR Mux" },
1105	{ "DACR", NULL, "CLK_DSP" },
1106
1107	{ "Charge pump", NULL, "SYSCLK" },
1108
1109	{ "Headphone Output", NULL, "HPL PGA" },
1110	{ "Headphone Output", NULL, "HPR PGA" },
1111	{ "Headphone Output", NULL, "Charge pump" },
1112	{ "Headphone Output", NULL, "TOCLK" },
1113
1114	{ "Line Output", NULL, "LINEL PGA" },
1115	{ "Line Output", NULL, "LINER PGA" },
1116	{ "Line Output", NULL, "Charge pump" },
1117	{ "Line Output", NULL, "TOCLK" },
1118
1119	{ "HPOUTL", NULL, "Headphone Output" },
1120	{ "HPOUTR", NULL, "Headphone Output" },
1121
1122	{ "LINEOUTL", NULL, "Line Output" },
1123	{ "LINEOUTR", NULL, "Line Output" },
1124};
1125
1126static const struct snd_soc_dapm_route wm8904_intercon[] = {
1127	{ "Left Sidetone", "Left", "ADCL" },
1128	{ "Left Sidetone", "Right", "ADCR" },
1129	{ "DACL", NULL, "Left Sidetone" },
1130
1131	{ "Right Sidetone", "Left", "ADCL" },
1132	{ "Right Sidetone", "Right", "ADCR" },
1133	{ "DACR", NULL, "Right Sidetone" },
1134
1135	{ "Left Bypass", NULL, "Class G" },
1136	{ "Left Bypass", NULL, "Left Capture PGA" },
1137
1138	{ "Right Bypass", NULL, "Class G" },
1139	{ "Right Bypass", NULL, "Right Capture PGA" },
1140
1141	{ "HPL Mux", "DAC", "DACL" },
1142	{ "HPL Mux", "Bypass", "Left Bypass" },
1143
1144	{ "HPR Mux", "DAC", "DACR" },
1145	{ "HPR Mux", "Bypass", "Right Bypass" },
1146
1147	{ "LINEL Mux", "DAC", "DACL" },
1148	{ "LINEL Mux", "Bypass", "Left Bypass" },
1149
1150	{ "LINER Mux", "DAC", "DACR" },
1151	{ "LINER Mux", "Bypass", "Right Bypass" },
1152
1153	{ "HPL PGA", NULL, "HPL Mux" },
1154	{ "HPR PGA", NULL, "HPR Mux" },
1155
1156	{ "LINEL PGA", NULL, "LINEL Mux" },
1157	{ "LINER PGA", NULL, "LINER Mux" },
1158};
1159
1160static const struct snd_soc_dapm_route wm8912_intercon[] = {
1161	{ "HPL PGA", NULL, "DACL" },
1162	{ "HPR PGA", NULL, "DACR" },
1163
1164	{ "LINEL PGA", NULL, "DACL" },
1165	{ "LINER PGA", NULL, "DACR" },
1166};
1167
1168static int wm8904_add_widgets(struct snd_soc_codec *codec)
1169{
1170	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
1171	struct snd_soc_dapm_context *dapm = &codec->dapm;
1172
1173	snd_soc_dapm_new_controls(dapm, wm8904_core_dapm_widgets,
1174				  ARRAY_SIZE(wm8904_core_dapm_widgets));
1175	snd_soc_dapm_add_routes(dapm, core_intercon,
1176				ARRAY_SIZE(core_intercon));
1177
1178	switch (wm8904->devtype) {
1179	case WM8904:
1180		snd_soc_add_codec_controls(codec, wm8904_adc_snd_controls,
1181				     ARRAY_SIZE(wm8904_adc_snd_controls));
1182		snd_soc_add_codec_controls(codec, wm8904_dac_snd_controls,
1183				     ARRAY_SIZE(wm8904_dac_snd_controls));
1184		snd_soc_add_codec_controls(codec, wm8904_snd_controls,
1185				     ARRAY_SIZE(wm8904_snd_controls));
1186
1187		snd_soc_dapm_new_controls(dapm, wm8904_adc_dapm_widgets,
1188					  ARRAY_SIZE(wm8904_adc_dapm_widgets));
1189		snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets,
1190					  ARRAY_SIZE(wm8904_dac_dapm_widgets));
1191		snd_soc_dapm_new_controls(dapm, wm8904_dapm_widgets,
1192					  ARRAY_SIZE(wm8904_dapm_widgets));
1193
1194		snd_soc_dapm_add_routes(dapm, adc_intercon,
1195					ARRAY_SIZE(adc_intercon));
1196		snd_soc_dapm_add_routes(dapm, dac_intercon,
1197					ARRAY_SIZE(dac_intercon));
1198		snd_soc_dapm_add_routes(dapm, wm8904_intercon,
1199					ARRAY_SIZE(wm8904_intercon));
1200		break;
1201
1202	case WM8912:
1203		snd_soc_add_codec_controls(codec, wm8904_dac_snd_controls,
1204				     ARRAY_SIZE(wm8904_dac_snd_controls));
1205
1206		snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets,
1207					  ARRAY_SIZE(wm8904_dac_dapm_widgets));
1208
1209		snd_soc_dapm_add_routes(dapm, dac_intercon,
1210					ARRAY_SIZE(dac_intercon));
1211		snd_soc_dapm_add_routes(dapm, wm8912_intercon,
1212					ARRAY_SIZE(wm8912_intercon));
1213		break;
1214	}
1215
1216	return 0;
1217}
1218
1219static struct {
1220	int ratio;
1221	unsigned int clk_sys_rate;
1222} clk_sys_rates[] = {
1223	{   64,  0 },
1224	{  128,  1 },
1225	{  192,  2 },
1226	{  256,  3 },
1227	{  384,  4 },
1228	{  512,  5 },
1229	{  786,  6 },
1230	{ 1024,  7 },
1231	{ 1408,  8 },
1232	{ 1536,  9 },
1233};
1234
1235static struct {
1236	int rate;
1237	int sample_rate;
1238} sample_rates[] = {
1239	{ 8000,  0  },
1240	{ 11025, 1  },
1241	{ 12000, 1  },
1242	{ 16000, 2  },
1243	{ 22050, 3  },
1244	{ 24000, 3  },
1245	{ 32000, 4  },
1246	{ 44100, 5  },
1247	{ 48000, 5  },
1248};
1249
1250static struct {
1251	int div; /* *10 due to .5s */
1252	int bclk_div;
1253} bclk_divs[] = {
1254	{ 10,  0  },
1255	{ 15,  1  },
1256	{ 20,  2  },
1257	{ 30,  3  },
1258	{ 40,  4  },
1259	{ 50,  5  },
1260	{ 55,  6  },
1261	{ 60,  7  },
1262	{ 80,  8  },
1263	{ 100, 9  },
1264	{ 110, 10 },
1265	{ 120, 11 },
1266	{ 160, 12 },
1267	{ 200, 13 },
1268	{ 220, 14 },
1269	{ 240, 16 },
1270	{ 200, 17 },
1271	{ 320, 18 },
1272	{ 440, 19 },
1273	{ 480, 20 },
1274};
1275
1276
1277static int wm8904_hw_params(struct snd_pcm_substream *substream,
1278			    struct snd_pcm_hw_params *params,
1279			    struct snd_soc_dai *dai)
1280{
1281	struct snd_soc_codec *codec = dai->codec;
1282	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
1283	int ret, i, best, best_val, cur_val;
1284	unsigned int aif1 = 0;
1285	unsigned int aif2 = 0;
1286	unsigned int aif3 = 0;
1287	unsigned int clock1 = 0;
1288	unsigned int dac_digital1 = 0;
1289
1290	/* What BCLK do we need? */
1291	wm8904->fs = params_rate(params);
1292	if (wm8904->tdm_slots) {
1293		dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n",
1294			wm8904->tdm_slots, wm8904->tdm_width);
1295		wm8904->bclk = snd_soc_calc_bclk(wm8904->fs,
1296						 wm8904->tdm_width, 2,
1297						 wm8904->tdm_slots);
1298	} else {
1299		wm8904->bclk = snd_soc_params_to_bclk(params);
1300	}
1301
1302	switch (params_width(params)) {
1303	case 16:
1304		break;
1305	case 20:
1306		aif1 |= 0x40;
1307		break;
1308	case 24:
1309		aif1 |= 0x80;
1310		break;
1311	case 32:
1312		aif1 |= 0xc0;
1313		break;
1314	default:
1315		return -EINVAL;
1316	}
1317
1318
1319	dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8904->bclk);
1320
1321	ret = wm8904_configure_clocking(codec);
1322	if (ret != 0)
1323		return ret;
1324
1325	/* Select nearest CLK_SYS_RATE */
1326	best = 0;
1327	best_val = abs((wm8904->sysclk_rate / clk_sys_rates[0].ratio)
1328		       - wm8904->fs);
1329	for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1330		cur_val = abs((wm8904->sysclk_rate /
1331			       clk_sys_rates[i].ratio) - wm8904->fs);
1332		if (cur_val < best_val) {
1333			best = i;
1334			best_val = cur_val;
1335		}
1336	}
1337	dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1338		clk_sys_rates[best].ratio);
1339	clock1 |= (clk_sys_rates[best].clk_sys_rate
1340		   << WM8904_CLK_SYS_RATE_SHIFT);
1341
1342	/* SAMPLE_RATE */
1343	best = 0;
1344	best_val = abs(wm8904->fs - sample_rates[0].rate);
1345	for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1346		/* Closest match */
1347		cur_val = abs(wm8904->fs - sample_rates[i].rate);
1348		if (cur_val < best_val) {
1349			best = i;
1350			best_val = cur_val;
1351		}
1352	}
1353	dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1354		sample_rates[best].rate);
1355	clock1 |= (sample_rates[best].sample_rate
1356		   << WM8904_SAMPLE_RATE_SHIFT);
1357
1358	/* Enable sloping stopband filter for low sample rates */
1359	if (wm8904->fs <= 24000)
1360		dac_digital1 |= WM8904_DAC_SB_FILT;
1361
1362	/* BCLK_DIV */
1363	best = 0;
1364	best_val = INT_MAX;
1365	for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1366		cur_val = ((wm8904->sysclk_rate * 10) / bclk_divs[i].div)
1367			- wm8904->bclk;
1368		if (cur_val < 0) /* Table is sorted */
1369			break;
1370		if (cur_val < best_val) {
1371			best = i;
1372			best_val = cur_val;
1373		}
1374	}
1375	wm8904->bclk = (wm8904->sysclk_rate * 10) / bclk_divs[best].div;
1376	dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1377		bclk_divs[best].div, wm8904->bclk);
1378	aif2 |= bclk_divs[best].bclk_div;
1379
1380	/* LRCLK is a simple fraction of BCLK */
1381	dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8904->bclk / wm8904->fs);
1382	aif3 |= wm8904->bclk / wm8904->fs;
1383
1384	/* Apply the settings */
1385	snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1,
1386			    WM8904_DAC_SB_FILT, dac_digital1);
1387	snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
1388			    WM8904_AIF_WL_MASK, aif1);
1389	snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_2,
1390			    WM8904_BCLK_DIV_MASK, aif2);
1391	snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3,
1392			    WM8904_LRCLK_RATE_MASK, aif3);
1393	snd_soc_update_bits(codec, WM8904_CLOCK_RATES_1,
1394			    WM8904_SAMPLE_RATE_MASK |
1395			    WM8904_CLK_SYS_RATE_MASK, clock1);
1396
1397	/* Update filters for the new settings */
1398	wm8904_set_retune_mobile(codec);
1399	wm8904_set_deemph(codec);
1400
1401	return 0;
1402}
1403
1404
1405static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id,
1406			     unsigned int freq, int dir)
1407{
1408	struct snd_soc_codec *codec = dai->codec;
1409	struct wm8904_priv *priv = snd_soc_codec_get_drvdata(codec);
1410
1411	switch (clk_id) {
1412	case WM8904_CLK_MCLK:
1413		priv->sysclk_src = clk_id;
1414		priv->mclk_rate = freq;
1415		break;
1416
1417	case WM8904_CLK_FLL:
1418		priv->sysclk_src = clk_id;
1419		break;
1420
1421	default:
1422		return -EINVAL;
1423	}
1424
1425	dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
1426
1427	wm8904_configure_clocking(codec);
1428
1429	return 0;
1430}
1431
1432static int wm8904_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1433{
1434	struct snd_soc_codec *codec = dai->codec;
1435	unsigned int aif1 = 0;
1436	unsigned int aif3 = 0;
1437
1438	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1439	case SND_SOC_DAIFMT_CBS_CFS:
1440		break;
1441	case SND_SOC_DAIFMT_CBS_CFM:
1442		aif3 |= WM8904_LRCLK_DIR;
1443		break;
1444	case SND_SOC_DAIFMT_CBM_CFS:
1445		aif1 |= WM8904_BCLK_DIR;
1446		break;
1447	case SND_SOC_DAIFMT_CBM_CFM:
1448		aif1 |= WM8904_BCLK_DIR;
1449		aif3 |= WM8904_LRCLK_DIR;
1450		break;
1451	default:
1452		return -EINVAL;
1453	}
1454
1455	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1456	case SND_SOC_DAIFMT_DSP_B:
1457		aif1 |= 0x3 | WM8904_AIF_LRCLK_INV;
1458	case SND_SOC_DAIFMT_DSP_A:
1459		aif1 |= 0x3;
1460		break;
1461	case SND_SOC_DAIFMT_I2S:
1462		aif1 |= 0x2;
1463		break;
1464	case SND_SOC_DAIFMT_RIGHT_J:
1465		break;
1466	case SND_SOC_DAIFMT_LEFT_J:
1467		aif1 |= 0x1;
1468		break;
1469	default:
1470		return -EINVAL;
1471	}
1472
1473	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1474	case SND_SOC_DAIFMT_DSP_A:
1475	case SND_SOC_DAIFMT_DSP_B:
1476		/* frame inversion not valid for DSP modes */
1477		switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1478		case SND_SOC_DAIFMT_NB_NF:
1479			break;
1480		case SND_SOC_DAIFMT_IB_NF:
1481			aif1 |= WM8904_AIF_BCLK_INV;
1482			break;
1483		default:
1484			return -EINVAL;
1485		}
1486		break;
1487
1488	case SND_SOC_DAIFMT_I2S:
1489	case SND_SOC_DAIFMT_RIGHT_J:
1490	case SND_SOC_DAIFMT_LEFT_J:
1491		switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1492		case SND_SOC_DAIFMT_NB_NF:
1493			break;
1494		case SND_SOC_DAIFMT_IB_IF:
1495			aif1 |= WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV;
1496			break;
1497		case SND_SOC_DAIFMT_IB_NF:
1498			aif1 |= WM8904_AIF_BCLK_INV;
1499			break;
1500		case SND_SOC_DAIFMT_NB_IF:
1501			aif1 |= WM8904_AIF_LRCLK_INV;
1502			break;
1503		default:
1504			return -EINVAL;
1505		}
1506		break;
1507	default:
1508		return -EINVAL;
1509	}
1510
1511	snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
1512			    WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV |
1513			    WM8904_AIF_FMT_MASK | WM8904_BCLK_DIR, aif1);
1514	snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3,
1515			    WM8904_LRCLK_DIR, aif3);
1516
1517	return 0;
1518}
1519
1520
1521static int wm8904_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1522			       unsigned int rx_mask, int slots, int slot_width)
1523{
1524	struct snd_soc_codec *codec = dai->codec;
1525	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
1526	int aif1 = 0;
1527
1528	/* Don't need to validate anything if we're turning off TDM */
1529	if (slots == 0)
1530		goto out;
1531
1532	/* Note that we allow configurations we can't handle ourselves -
1533	 * for example, we can generate clocks for slots 2 and up even if
1534	 * we can't use those slots ourselves.
1535	 */
1536	aif1 |= WM8904_AIFADC_TDM | WM8904_AIFDAC_TDM;
1537
1538	switch (rx_mask) {
1539	case 3:
1540		break;
1541	case 0xc:
1542		aif1 |= WM8904_AIFADC_TDM_CHAN;
1543		break;
1544	default:
1545		return -EINVAL;
1546	}
1547
1548
1549	switch (tx_mask) {
1550	case 3:
1551		break;
1552	case 0xc:
1553		aif1 |= WM8904_AIFDAC_TDM_CHAN;
1554		break;
1555	default:
1556		return -EINVAL;
1557	}
1558
1559out:
1560	wm8904->tdm_width = slot_width;
1561	wm8904->tdm_slots = slots / 2;
1562
1563	snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
1564			    WM8904_AIFADC_TDM | WM8904_AIFADC_TDM_CHAN |
1565			    WM8904_AIFDAC_TDM | WM8904_AIFDAC_TDM_CHAN, aif1);
1566
1567	return 0;
1568}
1569
1570struct _fll_div {
1571	u16 fll_fratio;
1572	u16 fll_outdiv;
1573	u16 fll_clk_ref_div;
1574	u16 n;
1575	u16 k;
1576};
1577
1578/* The size in bits of the FLL divide multiplied by 10
1579 * to allow rounding later */
1580#define FIXED_FLL_SIZE ((1 << 16) * 10)
1581
1582static struct {
1583	unsigned int min;
1584	unsigned int max;
1585	u16 fll_fratio;
1586	int ratio;
1587} fll_fratios[] = {
1588	{       0,    64000, 4, 16 },
1589	{   64000,   128000, 3,  8 },
1590	{  128000,   256000, 2,  4 },
1591	{  256000,  1000000, 1,  2 },
1592	{ 1000000, 13500000, 0,  1 },
1593};
1594
1595static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1596		       unsigned int Fout)
1597{
1598	u64 Kpart;
1599	unsigned int K, Ndiv, Nmod, target;
1600	unsigned int div;
1601	int i;
1602
1603	/* Fref must be <=13.5MHz */
1604	div = 1;
1605	fll_div->fll_clk_ref_div = 0;
1606	while ((Fref / div) > 13500000) {
1607		div *= 2;
1608		fll_div->fll_clk_ref_div++;
1609
1610		if (div > 8) {
1611			pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1612			       Fref);
1613			return -EINVAL;
1614		}
1615	}
1616
1617	pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
1618
1619	/* Apply the division for our remaining calculations */
1620	Fref /= div;
1621
1622	/* Fvco should be 90-100MHz; don't check the upper bound */
1623	div = 4;
1624	while (Fout * div < 90000000) {
1625		div++;
1626		if (div > 64) {
1627			pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1628			       Fout);
1629			return -EINVAL;
1630		}
1631	}
1632	target = Fout * div;
1633	fll_div->fll_outdiv = div - 1;
1634
1635	pr_debug("Fvco=%dHz\n", target);
1636
1637	/* Find an appropriate FLL_FRATIO and factor it out of the target */
1638	for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1639		if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1640			fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1641			target /= fll_fratios[i].ratio;
1642			break;
1643		}
1644	}
1645	if (i == ARRAY_SIZE(fll_fratios)) {
1646		pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1647		return -EINVAL;
1648	}
1649
1650	/* Now, calculate N.K */
1651	Ndiv = target / Fref;
1652
1653	fll_div->n = Ndiv;
1654	Nmod = target % Fref;
1655	pr_debug("Nmod=%d\n", Nmod);
1656
1657	/* Calculate fractional part - scale up so we can round. */
1658	Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1659
1660	do_div(Kpart, Fref);
1661
1662	K = Kpart & 0xFFFFFFFF;
1663
1664	if ((K % 10) >= 5)
1665		K += 5;
1666
1667	/* Move down to proper range now rounding is done */
1668	fll_div->k = K / 10;
1669
1670	pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
1671		 fll_div->n, fll_div->k,
1672		 fll_div->fll_fratio, fll_div->fll_outdiv,
1673		 fll_div->fll_clk_ref_div);
1674
1675	return 0;
1676}
1677
1678static int wm8904_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
1679			  unsigned int Fref, unsigned int Fout)
1680{
1681	struct snd_soc_codec *codec = dai->codec;
1682	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
1683	struct _fll_div fll_div;
1684	int ret, val;
1685	int clock2, fll1;
1686
1687	/* Any change? */
1688	if (source == wm8904->fll_src && Fref == wm8904->fll_fref &&
1689	    Fout == wm8904->fll_fout)
1690		return 0;
1691
1692	clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2);
1693
1694	if (Fout == 0) {
1695		dev_dbg(codec->dev, "FLL disabled\n");
1696
1697		wm8904->fll_fref = 0;
1698		wm8904->fll_fout = 0;
1699
1700		/* Gate SYSCLK to avoid glitches */
1701		snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
1702				    WM8904_CLK_SYS_ENA, 0);
1703
1704		snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1705				    WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
1706
1707		goto out;
1708	}
1709
1710	/* Validate the FLL ID */
1711	switch (source) {
1712	case WM8904_FLL_MCLK:
1713	case WM8904_FLL_LRCLK:
1714	case WM8904_FLL_BCLK:
1715		ret = fll_factors(&fll_div, Fref, Fout);
1716		if (ret != 0)
1717			return ret;
1718		break;
1719
1720	case WM8904_FLL_FREE_RUNNING:
1721		dev_dbg(codec->dev, "Using free running FLL\n");
1722		/* Force 12MHz and output/4 for now */
1723		Fout = 12000000;
1724		Fref = 12000000;
1725
1726		memset(&fll_div, 0, sizeof(fll_div));
1727		fll_div.fll_outdiv = 3;
1728		break;
1729
1730	default:
1731		dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
1732		return -EINVAL;
1733	}
1734
1735	/* Save current state then disable the FLL and SYSCLK to avoid
1736	 * misclocking */
1737	fll1 = snd_soc_read(codec, WM8904_FLL_CONTROL_1);
1738	snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
1739			    WM8904_CLK_SYS_ENA, 0);
1740	snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1741			    WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
1742
1743	/* Unlock forced oscilator control to switch it on/off */
1744	snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1,
1745			    WM8904_USER_KEY, WM8904_USER_KEY);
1746
1747	if (fll_id == WM8904_FLL_FREE_RUNNING) {
1748		val = WM8904_FLL_FRC_NCO;
1749	} else {
1750		val = 0;
1751	}
1752
1753	snd_soc_update_bits(codec, WM8904_FLL_NCO_TEST_1, WM8904_FLL_FRC_NCO,
1754			    val);
1755	snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1,
1756			    WM8904_USER_KEY, 0);
1757
1758	switch (fll_id) {
1759	case WM8904_FLL_MCLK:
1760		snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
1761				    WM8904_FLL_CLK_REF_SRC_MASK, 0);
1762		break;
1763
1764	case WM8904_FLL_LRCLK:
1765		snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
1766				    WM8904_FLL_CLK_REF_SRC_MASK, 1);
1767		break;
1768
1769	case WM8904_FLL_BCLK:
1770		snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
1771				    WM8904_FLL_CLK_REF_SRC_MASK, 2);
1772		break;
1773	}
1774
1775	if (fll_div.k)
1776		val = WM8904_FLL_FRACN_ENA;
1777	else
1778		val = 0;
1779	snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1780			    WM8904_FLL_FRACN_ENA, val);
1781
1782	snd_soc_update_bits(codec, WM8904_FLL_CONTROL_2,
1783			    WM8904_FLL_OUTDIV_MASK | WM8904_FLL_FRATIO_MASK,
1784			    (fll_div.fll_outdiv << WM8904_FLL_OUTDIV_SHIFT) |
1785			    (fll_div.fll_fratio << WM8904_FLL_FRATIO_SHIFT));
1786
1787	snd_soc_write(codec, WM8904_FLL_CONTROL_3, fll_div.k);
1788
1789	snd_soc_update_bits(codec, WM8904_FLL_CONTROL_4, WM8904_FLL_N_MASK,
1790			    fll_div.n << WM8904_FLL_N_SHIFT);
1791
1792	snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
1793			    WM8904_FLL_CLK_REF_DIV_MASK,
1794			    fll_div.fll_clk_ref_div
1795			    << WM8904_FLL_CLK_REF_DIV_SHIFT);
1796
1797	dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
1798
1799	wm8904->fll_fref = Fref;
1800	wm8904->fll_fout = Fout;
1801	wm8904->fll_src = source;
1802
1803	/* Enable the FLL if it was previously active */
1804	snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1805			    WM8904_FLL_OSC_ENA, fll1);
1806	snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1807			    WM8904_FLL_ENA, fll1);
1808
1809out:
1810	/* Reenable SYSCLK if it was previously active */
1811	snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
1812			    WM8904_CLK_SYS_ENA, clock2);
1813
1814	return 0;
1815}
1816
1817static int wm8904_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1818{
1819	struct snd_soc_codec *codec = codec_dai->codec;
1820	int val;
1821
1822	if (mute)
1823		val = WM8904_DAC_MUTE;
1824	else
1825		val = 0;
1826
1827	snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, WM8904_DAC_MUTE, val);
1828
1829	return 0;
1830}
1831
1832static int wm8904_set_bias_level(struct snd_soc_codec *codec,
1833				 enum snd_soc_bias_level level)
1834{
1835	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
1836	int ret;
1837
1838	switch (level) {
1839	case SND_SOC_BIAS_ON:
1840		clk_prepare_enable(wm8904->mclk);
1841		break;
1842
1843	case SND_SOC_BIAS_PREPARE:
1844		/* VMID resistance 2*50k */
1845		snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
1846				    WM8904_VMID_RES_MASK,
1847				    0x1 << WM8904_VMID_RES_SHIFT);
1848
1849		/* Normal bias current */
1850		snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
1851				    WM8904_ISEL_MASK, 2 << WM8904_ISEL_SHIFT);
1852		break;
1853
1854	case SND_SOC_BIAS_STANDBY:
1855		if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1856			ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
1857						    wm8904->supplies);
1858			if (ret != 0) {
1859				dev_err(codec->dev,
1860					"Failed to enable supplies: %d\n",
1861					ret);
1862				return ret;
1863			}
1864
1865			regcache_cache_only(wm8904->regmap, false);
1866			regcache_sync(wm8904->regmap);
1867
1868			/* Enable bias */
1869			snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
1870					    WM8904_BIAS_ENA, WM8904_BIAS_ENA);
1871
1872			/* Enable VMID, VMID buffering, 2*5k resistance */
1873			snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
1874					    WM8904_VMID_ENA |
1875					    WM8904_VMID_RES_MASK,
1876					    WM8904_VMID_ENA |
1877					    0x3 << WM8904_VMID_RES_SHIFT);
1878
1879			/* Let VMID ramp */
1880			msleep(1);
1881		}
1882
1883		/* Maintain VMID with 2*250k */
1884		snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
1885				    WM8904_VMID_RES_MASK,
1886				    0x2 << WM8904_VMID_RES_SHIFT);
1887
1888		/* Bias current *0.5 */
1889		snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
1890				    WM8904_ISEL_MASK, 0);
1891		break;
1892
1893	case SND_SOC_BIAS_OFF:
1894		/* Turn off VMID */
1895		snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
1896				    WM8904_VMID_RES_MASK | WM8904_VMID_ENA, 0);
1897
1898		/* Stop bias generation */
1899		snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
1900				    WM8904_BIAS_ENA, 0);
1901
1902		regcache_cache_only(wm8904->regmap, true);
1903		regcache_mark_dirty(wm8904->regmap);
1904
1905		regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies),
1906				       wm8904->supplies);
1907		clk_disable_unprepare(wm8904->mclk);
1908		break;
1909	}
1910	codec->dapm.bias_level = level;
1911	return 0;
1912}
1913
1914#define WM8904_RATES SNDRV_PCM_RATE_8000_96000
1915
1916#define WM8904_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1917			SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1918
1919static const struct snd_soc_dai_ops wm8904_dai_ops = {
1920	.set_sysclk = wm8904_set_sysclk,
1921	.set_fmt = wm8904_set_fmt,
1922	.set_tdm_slot = wm8904_set_tdm_slot,
1923	.set_pll = wm8904_set_fll,
1924	.hw_params = wm8904_hw_params,
1925	.digital_mute = wm8904_digital_mute,
1926};
1927
1928static struct snd_soc_dai_driver wm8904_dai = {
1929	.name = "wm8904-hifi",
1930	.playback = {
1931		.stream_name = "Playback",
1932		.channels_min = 2,
1933		.channels_max = 2,
1934		.rates = WM8904_RATES,
1935		.formats = WM8904_FORMATS,
1936	},
1937	.capture = {
1938		.stream_name = "Capture",
1939		.channels_min = 2,
1940		.channels_max = 2,
1941		.rates = WM8904_RATES,
1942		.formats = WM8904_FORMATS,
1943	},
1944	.ops = &wm8904_dai_ops,
1945	.symmetric_rates = 1,
1946};
1947
1948static void wm8904_handle_retune_mobile_pdata(struct snd_soc_codec *codec)
1949{
1950	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
1951	struct wm8904_pdata *pdata = wm8904->pdata;
1952	struct snd_kcontrol_new control =
1953		SOC_ENUM_EXT("EQ Mode",
1954			     wm8904->retune_mobile_enum,
1955			     wm8904_get_retune_mobile_enum,
1956			     wm8904_put_retune_mobile_enum);
1957	int ret, i, j;
1958	const char **t;
1959
1960	/* We need an array of texts for the enum API but the number
1961	 * of texts is likely to be less than the number of
1962	 * configurations due to the sample rate dependency of the
1963	 * configurations. */
1964	wm8904->num_retune_mobile_texts = 0;
1965	wm8904->retune_mobile_texts = NULL;
1966	for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
1967		for (j = 0; j < wm8904->num_retune_mobile_texts; j++) {
1968			if (strcmp(pdata->retune_mobile_cfgs[i].name,
1969				   wm8904->retune_mobile_texts[j]) == 0)
1970				break;
1971		}
1972
1973		if (j != wm8904->num_retune_mobile_texts)
1974			continue;
1975
1976		/* Expand the array... */
1977		t = krealloc(wm8904->retune_mobile_texts,
1978			     sizeof(char *) *
1979			     (wm8904->num_retune_mobile_texts + 1),
1980			     GFP_KERNEL);
1981		if (t == NULL)
1982			continue;
1983
1984		/* ...store the new entry... */
1985		t[wm8904->num_retune_mobile_texts] =
1986			pdata->retune_mobile_cfgs[i].name;
1987
1988		/* ...and remember the new version. */
1989		wm8904->num_retune_mobile_texts++;
1990		wm8904->retune_mobile_texts = t;
1991	}
1992
1993	dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
1994		wm8904->num_retune_mobile_texts);
1995
1996	wm8904->retune_mobile_enum.items = wm8904->num_retune_mobile_texts;
1997	wm8904->retune_mobile_enum.texts = wm8904->retune_mobile_texts;
1998
1999	ret = snd_soc_add_codec_controls(codec, &control, 1);
2000	if (ret != 0)
2001		dev_err(codec->dev,
2002			"Failed to add ReTune Mobile control: %d\n", ret);
2003}
2004
2005static void wm8904_handle_pdata(struct snd_soc_codec *codec)
2006{
2007	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
2008	struct wm8904_pdata *pdata = wm8904->pdata;
2009	int ret, i;
2010
2011	if (!pdata) {
2012		snd_soc_add_codec_controls(codec, wm8904_eq_controls,
2013				     ARRAY_SIZE(wm8904_eq_controls));
2014		return;
2015	}
2016
2017	dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2018
2019	if (pdata->num_drc_cfgs) {
2020		struct snd_kcontrol_new control =
2021			SOC_ENUM_EXT("DRC Mode", wm8904->drc_enum,
2022				     wm8904_get_drc_enum, wm8904_put_drc_enum);
2023
2024		/* We need an array of texts for the enum API */
2025		wm8904->drc_texts = kmalloc(sizeof(char *)
2026					    * pdata->num_drc_cfgs, GFP_KERNEL);
2027		if (!wm8904->drc_texts)
2028			return;
2029
2030		for (i = 0; i < pdata->num_drc_cfgs; i++)
2031			wm8904->drc_texts[i] = pdata->drc_cfgs[i].name;
2032
2033		wm8904->drc_enum.items = pdata->num_drc_cfgs;
2034		wm8904->drc_enum.texts = wm8904->drc_texts;
2035
2036		ret = snd_soc_add_codec_controls(codec, &control, 1);
2037		if (ret != 0)
2038			dev_err(codec->dev,
2039				"Failed to add DRC mode control: %d\n", ret);
2040
2041		wm8904_set_drc(codec);
2042	}
2043
2044	dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2045		pdata->num_retune_mobile_cfgs);
2046
2047	if (pdata->num_retune_mobile_cfgs)
2048		wm8904_handle_retune_mobile_pdata(codec);
2049	else
2050		snd_soc_add_codec_controls(codec, wm8904_eq_controls,
2051				     ARRAY_SIZE(wm8904_eq_controls));
2052}
2053
2054
2055static int wm8904_probe(struct snd_soc_codec *codec)
2056{
2057	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
2058
2059	switch (wm8904->devtype) {
2060	case WM8904:
2061		break;
2062	case WM8912:
2063		memset(&wm8904_dai.capture, 0, sizeof(wm8904_dai.capture));
2064		break;
2065	default:
2066		dev_err(codec->dev, "Unknown device type %d\n",
2067			wm8904->devtype);
2068		return -EINVAL;
2069	}
2070
2071	wm8904_handle_pdata(codec);
2072
2073	wm8904_add_widgets(codec);
2074
2075	return 0;
2076}
2077
2078static int wm8904_remove(struct snd_soc_codec *codec)
2079{
2080	struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
2081
2082	kfree(wm8904->retune_mobile_texts);
2083	kfree(wm8904->drc_texts);
2084
2085	return 0;
2086}
2087
2088static struct snd_soc_codec_driver soc_codec_dev_wm8904 = {
2089	.probe =	wm8904_probe,
2090	.remove =	wm8904_remove,
2091	.set_bias_level = wm8904_set_bias_level,
2092	.idle_bias_off = true,
2093};
2094
2095static const struct regmap_config wm8904_regmap = {
2096	.reg_bits = 8,
2097	.val_bits = 16,
2098
2099	.max_register = WM8904_MAX_REGISTER,
2100	.volatile_reg = wm8904_volatile_register,
2101	.readable_reg = wm8904_readable_register,
2102
2103	.cache_type = REGCACHE_RBTREE,
2104	.reg_defaults = wm8904_reg_defaults,
2105	.num_reg_defaults = ARRAY_SIZE(wm8904_reg_defaults),
2106};
2107
2108#ifdef CONFIG_OF
2109static enum wm8904_type wm8904_data = WM8904;
2110static enum wm8904_type wm8912_data = WM8912;
2111
2112static const struct of_device_id wm8904_of_match[] = {
2113	{
2114		.compatible = "wlf,wm8904",
2115		.data = &wm8904_data,
2116	}, {
2117		.compatible = "wlf,wm8912",
2118		.data = &wm8912_data,
2119	}, {
2120		/* sentinel */
2121	}
2122};
2123MODULE_DEVICE_TABLE(of, wm8904_of_match);
2124#endif
2125
2126static int wm8904_i2c_probe(struct i2c_client *i2c,
2127			    const struct i2c_device_id *id)
2128{
2129	struct wm8904_priv *wm8904;
2130	unsigned int val;
2131	int ret, i;
2132
2133	wm8904 = devm_kzalloc(&i2c->dev, sizeof(struct wm8904_priv),
2134			      GFP_KERNEL);
2135	if (wm8904 == NULL)
2136		return -ENOMEM;
2137
2138	wm8904->mclk = devm_clk_get(&i2c->dev, "mclk");
2139	if (IS_ERR(wm8904->mclk)) {
2140		ret = PTR_ERR(wm8904->mclk);
2141		dev_err(&i2c->dev, "Failed to get MCLK\n");
2142		return ret;
2143	}
2144
2145	wm8904->regmap = devm_regmap_init_i2c(i2c, &wm8904_regmap);
2146	if (IS_ERR(wm8904->regmap)) {
2147		ret = PTR_ERR(wm8904->regmap);
2148		dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2149			ret);
2150		return ret;
2151	}
2152
2153	if (i2c->dev.of_node) {
2154		const struct of_device_id *match;
2155
2156		match = of_match_node(wm8904_of_match, i2c->dev.of_node);
2157		if (match == NULL)
2158			return -EINVAL;
2159		wm8904->devtype = *((enum wm8904_type *)match->data);
2160	} else {
2161		wm8904->devtype = id->driver_data;
2162	}
2163
2164	i2c_set_clientdata(i2c, wm8904);
2165	wm8904->pdata = i2c->dev.platform_data;
2166
2167	for (i = 0; i < ARRAY_SIZE(wm8904->supplies); i++)
2168		wm8904->supplies[i].supply = wm8904_supply_names[i];
2169
2170	ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8904->supplies),
2171				      wm8904->supplies);
2172	if (ret != 0) {
2173		dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
2174		return ret;
2175	}
2176
2177	ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
2178				    wm8904->supplies);
2179	if (ret != 0) {
2180		dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
2181		return ret;
2182	}
2183
2184	ret = regmap_read(wm8904->regmap, WM8904_SW_RESET_AND_ID, &val);
2185	if (ret < 0) {
2186		dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
2187		goto err_enable;
2188	}
2189	if (val != 0x8904) {
2190		dev_err(&i2c->dev, "Device is not a WM8904, ID is %x\n", val);
2191		ret = -EINVAL;
2192		goto err_enable;
2193	}
2194
2195	ret = regmap_read(wm8904->regmap, WM8904_REVISION, &val);
2196	if (ret < 0) {
2197		dev_err(&i2c->dev, "Failed to read device revision: %d\n",
2198			ret);
2199		goto err_enable;
2200	}
2201	dev_info(&i2c->dev, "revision %c\n", val + 'A');
2202
2203	ret = regmap_write(wm8904->regmap, WM8904_SW_RESET_AND_ID, 0);
2204	if (ret < 0) {
2205		dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
2206		goto err_enable;
2207	}
2208
2209	/* Change some default settings - latch VU and enable ZC */
2210	regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_LEFT,
2211			   WM8904_ADC_VU, WM8904_ADC_VU);
2212	regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_RIGHT,
2213			   WM8904_ADC_VU, WM8904_ADC_VU);
2214	regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_LEFT,
2215			   WM8904_DAC_VU, WM8904_DAC_VU);
2216	regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_RIGHT,
2217			   WM8904_DAC_VU, WM8904_DAC_VU);
2218	regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_LEFT,
2219			   WM8904_HPOUT_VU | WM8904_HPOUTLZC,
2220			   WM8904_HPOUT_VU | WM8904_HPOUTLZC);
2221	regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_RIGHT,
2222			   WM8904_HPOUT_VU | WM8904_HPOUTRZC,
2223			   WM8904_HPOUT_VU | WM8904_HPOUTRZC);
2224	regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_LEFT,
2225			   WM8904_LINEOUT_VU | WM8904_LINEOUTLZC,
2226			   WM8904_LINEOUT_VU | WM8904_LINEOUTLZC);
2227	regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_RIGHT,
2228			   WM8904_LINEOUT_VU | WM8904_LINEOUTRZC,
2229			   WM8904_LINEOUT_VU | WM8904_LINEOUTRZC);
2230	regmap_update_bits(wm8904->regmap, WM8904_CLOCK_RATES_0,
2231			   WM8904_SR_MODE, 0);
2232
2233	/* Apply configuration from the platform data. */
2234	if (wm8904->pdata) {
2235		for (i = 0; i < WM8904_GPIO_REGS; i++) {
2236			if (!wm8904->pdata->gpio_cfg[i])
2237				continue;
2238
2239			regmap_update_bits(wm8904->regmap,
2240					   WM8904_GPIO_CONTROL_1 + i,
2241					   0xffff,
2242					   wm8904->pdata->gpio_cfg[i]);
2243		}
2244
2245		/* Zero is the default value for these anyway */
2246		for (i = 0; i < WM8904_MIC_REGS; i++)
2247			regmap_update_bits(wm8904->regmap,
2248					   WM8904_MIC_BIAS_CONTROL_0 + i,
2249					   0xffff,
2250					   wm8904->pdata->mic_cfg[i]);
2251	}
2252
2253	/* Set Class W by default - this will be managed by the Class
2254	 * G widget at runtime where bypass paths are available.
2255	 */
2256	regmap_update_bits(wm8904->regmap, WM8904_CLASS_W_0,
2257			    WM8904_CP_DYN_PWR, WM8904_CP_DYN_PWR);
2258
2259	/* Use normal bias source */
2260	regmap_update_bits(wm8904->regmap, WM8904_BIAS_CONTROL_0,
2261			    WM8904_POBCTRL, 0);
2262
2263	/* Can leave the device powered off until we need it */
2264	regcache_cache_only(wm8904->regmap, true);
2265	regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
2266
2267	ret = snd_soc_register_codec(&i2c->dev,
2268			&soc_codec_dev_wm8904, &wm8904_dai, 1);
2269	if (ret != 0)
2270		return ret;
2271
2272	return 0;
2273
2274err_enable:
2275	regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
2276	return ret;
2277}
2278
2279static int wm8904_i2c_remove(struct i2c_client *client)
2280{
2281	snd_soc_unregister_codec(&client->dev);
2282	return 0;
2283}
2284
2285static const struct i2c_device_id wm8904_i2c_id[] = {
2286	{ "wm8904", WM8904 },
2287	{ "wm8912", WM8912 },
2288	{ "wm8918", WM8904 },   /* Actually a subset, updates to follow */
2289	{ }
2290};
2291MODULE_DEVICE_TABLE(i2c, wm8904_i2c_id);
2292
2293static struct i2c_driver wm8904_i2c_driver = {
2294	.driver = {
2295		.name = "wm8904",
2296		.owner = THIS_MODULE,
2297		.of_match_table = of_match_ptr(wm8904_of_match),
2298	},
2299	.probe =    wm8904_i2c_probe,
2300	.remove =   wm8904_i2c_remove,
2301	.id_table = wm8904_i2c_id,
2302};
2303
2304module_i2c_driver(wm8904_i2c_driver);
2305
2306MODULE_DESCRIPTION("ASoC WM8904 driver");
2307MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2308MODULE_LICENSE("GPL");
2309