1/* 2 * wm8995.c -- WM8995 ALSA SoC Audio driver 3 * 4 * Copyright 2010 Wolfson Microelectronics plc 5 * 6 * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> 7 * 8 * Based on wm8994.c and wm_hubs.c by Mark Brown 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15#include <linux/module.h> 16#include <linux/moduleparam.h> 17#include <linux/init.h> 18#include <linux/delay.h> 19#include <linux/pm.h> 20#include <linux/i2c.h> 21#include <linux/regmap.h> 22#include <linux/spi/spi.h> 23#include <linux/regulator/consumer.h> 24#include <linux/slab.h> 25#include <sound/core.h> 26#include <sound/pcm.h> 27#include <sound/pcm_params.h> 28#include <sound/soc.h> 29#include <sound/soc-dapm.h> 30#include <sound/initval.h> 31#include <sound/tlv.h> 32 33#include "wm8995.h" 34 35#define WM8995_NUM_SUPPLIES 8 36static const char *wm8995_supply_names[WM8995_NUM_SUPPLIES] = { 37 "DCVDD", 38 "DBVDD1", 39 "DBVDD2", 40 "DBVDD3", 41 "AVDD1", 42 "AVDD2", 43 "CPVDD", 44 "MICVDD" 45}; 46 47static const struct reg_default wm8995_reg_defaults[] = { 48 { 0, 0x8995 }, 49 { 5, 0x0100 }, 50 { 16, 0x000b }, 51 { 17, 0x000b }, 52 { 24, 0x02c0 }, 53 { 25, 0x02c0 }, 54 { 26, 0x02c0 }, 55 { 27, 0x02c0 }, 56 { 28, 0x000f }, 57 { 32, 0x0005 }, 58 { 33, 0x0005 }, 59 { 40, 0x0003 }, 60 { 41, 0x0013 }, 61 { 48, 0x0004 }, 62 { 56, 0x09f8 }, 63 { 64, 0x1f25 }, 64 { 69, 0x0004 }, 65 { 82, 0xaaaa }, 66 { 84, 0x2a2a }, 67 { 146, 0x0060 }, 68 { 256, 0x0002 }, 69 { 257, 0x8004 }, 70 { 520, 0x0010 }, 71 { 528, 0x0083 }, 72 { 529, 0x0083 }, 73 { 548, 0x0c80 }, 74 { 580, 0x0c80 }, 75 { 768, 0x4050 }, 76 { 769, 0x4000 }, 77 { 771, 0x0040 }, 78 { 772, 0x0040 }, 79 { 773, 0x0040 }, 80 { 774, 0x0004 }, 81 { 775, 0x0100 }, 82 { 784, 0x4050 }, 83 { 785, 0x4000 }, 84 { 787, 0x0040 }, 85 { 788, 0x0040 }, 86 { 789, 0x0040 }, 87 { 1024, 0x00c0 }, 88 { 1025, 0x00c0 }, 89 { 1026, 0x00c0 }, 90 { 1027, 0x00c0 }, 91 { 1028, 0x00c0 }, 92 { 1029, 0x00c0 }, 93 { 1030, 0x00c0 }, 94 { 1031, 0x00c0 }, 95 { 1056, 0x0200 }, 96 { 1057, 0x0010 }, 97 { 1058, 0x0200 }, 98 { 1059, 0x0010 }, 99 { 1088, 0x0098 }, 100 { 1089, 0x0845 }, 101 { 1104, 0x0098 }, 102 { 1105, 0x0845 }, 103 { 1152, 0x6318 }, 104 { 1153, 0x6300 }, 105 { 1154, 0x0fca }, 106 { 1155, 0x0400 }, 107 { 1156, 0x00d8 }, 108 { 1157, 0x1eb5 }, 109 { 1158, 0xf145 }, 110 { 1159, 0x0b75 }, 111 { 1160, 0x01c5 }, 112 { 1161, 0x1c58 }, 113 { 1162, 0xf373 }, 114 { 1163, 0x0a54 }, 115 { 1164, 0x0558 }, 116 { 1165, 0x168e }, 117 { 1166, 0xf829 }, 118 { 1167, 0x07ad }, 119 { 1168, 0x1103 }, 120 { 1169, 0x0564 }, 121 { 1170, 0x0559 }, 122 { 1171, 0x4000 }, 123 { 1184, 0x6318 }, 124 { 1185, 0x6300 }, 125 { 1186, 0x0fca }, 126 { 1187, 0x0400 }, 127 { 1188, 0x00d8 }, 128 { 1189, 0x1eb5 }, 129 { 1190, 0xf145 }, 130 { 1191, 0x0b75 }, 131 { 1192, 0x01c5 }, 132 { 1193, 0x1c58 }, 133 { 1194, 0xf373 }, 134 { 1195, 0x0a54 }, 135 { 1196, 0x0558 }, 136 { 1197, 0x168e }, 137 { 1198, 0xf829 }, 138 { 1199, 0x07ad }, 139 { 1200, 0x1103 }, 140 { 1201, 0x0564 }, 141 { 1202, 0x0559 }, 142 { 1203, 0x4000 }, 143 { 1280, 0x00c0 }, 144 { 1281, 0x00c0 }, 145 { 1282, 0x00c0 }, 146 { 1283, 0x00c0 }, 147 { 1312, 0x0200 }, 148 { 1313, 0x0010 }, 149 { 1344, 0x0098 }, 150 { 1345, 0x0845 }, 151 { 1408, 0x6318 }, 152 { 1409, 0x6300 }, 153 { 1410, 0x0fca }, 154 { 1411, 0x0400 }, 155 { 1412, 0x00d8 }, 156 { 1413, 0x1eb5 }, 157 { 1414, 0xf145 }, 158 { 1415, 0x0b75 }, 159 { 1416, 0x01c5 }, 160 { 1417, 0x1c58 }, 161 { 1418, 0xf373 }, 162 { 1419, 0x0a54 }, 163 { 1420, 0x0558 }, 164 { 1421, 0x168e }, 165 { 1422, 0xf829 }, 166 { 1423, 0x07ad }, 167 { 1424, 0x1103 }, 168 { 1425, 0x0564 }, 169 { 1426, 0x0559 }, 170 { 1427, 0x4000 }, 171 { 1568, 0x0002 }, 172 { 1792, 0xa100 }, 173 { 1793, 0xa101 }, 174 { 1794, 0xa101 }, 175 { 1795, 0xa101 }, 176 { 1796, 0xa101 }, 177 { 1797, 0xa101 }, 178 { 1798, 0xa101 }, 179 { 1799, 0xa101 }, 180 { 1800, 0xa101 }, 181 { 1801, 0xa101 }, 182 { 1802, 0xa101 }, 183 { 1803, 0xa101 }, 184 { 1804, 0xa101 }, 185 { 1805, 0xa101 }, 186 { 1825, 0x0055 }, 187 { 1848, 0x3fff }, 188 { 1849, 0x1fff }, 189 { 2049, 0x0001 }, 190 { 2050, 0x0069 }, 191 { 2056, 0x0002 }, 192 { 2057, 0x0003 }, 193 { 2058, 0x0069 }, 194 { 12288, 0x0001 }, 195 { 12289, 0x0001 }, 196 { 12291, 0x0006 }, 197 { 12292, 0x0040 }, 198 { 12293, 0x0001 }, 199 { 12294, 0x000f }, 200 { 12295, 0x0006 }, 201 { 12296, 0x0001 }, 202 { 12297, 0x0003 }, 203 { 12298, 0x0104 }, 204 { 12300, 0x0060 }, 205 { 12301, 0x0011 }, 206 { 12302, 0x0401 }, 207 { 12304, 0x0050 }, 208 { 12305, 0x0003 }, 209 { 12306, 0x0100 }, 210 { 12308, 0x0051 }, 211 { 12309, 0x0003 }, 212 { 12310, 0x0104 }, 213 { 12311, 0x000a }, 214 { 12312, 0x0060 }, 215 { 12313, 0x003b }, 216 { 12314, 0x0502 }, 217 { 12315, 0x0100 }, 218 { 12316, 0x2fff }, 219 { 12320, 0x2fff }, 220 { 12324, 0x2fff }, 221 { 12328, 0x2fff }, 222 { 12332, 0x2fff }, 223 { 12336, 0x2fff }, 224 { 12340, 0x2fff }, 225 { 12344, 0x2fff }, 226 { 12348, 0x2fff }, 227 { 12352, 0x0001 }, 228 { 12353, 0x0001 }, 229 { 12355, 0x0006 }, 230 { 12356, 0x0040 }, 231 { 12357, 0x0001 }, 232 { 12358, 0x000f }, 233 { 12359, 0x0006 }, 234 { 12360, 0x0001 }, 235 { 12361, 0x0003 }, 236 { 12362, 0x0104 }, 237 { 12364, 0x0060 }, 238 { 12365, 0x0011 }, 239 { 12366, 0x0401 }, 240 { 12368, 0x0050 }, 241 { 12369, 0x0003 }, 242 { 12370, 0x0100 }, 243 { 12372, 0x0060 }, 244 { 12373, 0x003b }, 245 { 12374, 0x0502 }, 246 { 12375, 0x0100 }, 247 { 12376, 0x2fff }, 248 { 12380, 0x2fff }, 249 { 12384, 0x2fff }, 250 { 12388, 0x2fff }, 251 { 12392, 0x2fff }, 252 { 12396, 0x2fff }, 253 { 12400, 0x2fff }, 254 { 12404, 0x2fff }, 255 { 12408, 0x2fff }, 256 { 12412, 0x2fff }, 257 { 12416, 0x0001 }, 258 { 12417, 0x0001 }, 259 { 12419, 0x0006 }, 260 { 12420, 0x0040 }, 261 { 12421, 0x0001 }, 262 { 12422, 0x000f }, 263 { 12423, 0x0006 }, 264 { 12424, 0x0001 }, 265 { 12425, 0x0003 }, 266 { 12426, 0x0106 }, 267 { 12428, 0x0061 }, 268 { 12429, 0x0011 }, 269 { 12430, 0x0401 }, 270 { 12432, 0x0050 }, 271 { 12433, 0x0003 }, 272 { 12434, 0x0102 }, 273 { 12436, 0x0051 }, 274 { 12437, 0x0003 }, 275 { 12438, 0x0106 }, 276 { 12439, 0x000a }, 277 { 12440, 0x0061 }, 278 { 12441, 0x003b }, 279 { 12442, 0x0502 }, 280 { 12443, 0x0100 }, 281 { 12444, 0x2fff }, 282 { 12448, 0x2fff }, 283 { 12452, 0x2fff }, 284 { 12456, 0x2fff }, 285 { 12460, 0x2fff }, 286 { 12464, 0x2fff }, 287 { 12468, 0x2fff }, 288 { 12472, 0x2fff }, 289 { 12476, 0x2fff }, 290 { 12480, 0x0001 }, 291 { 12481, 0x0001 }, 292 { 12483, 0x0006 }, 293 { 12484, 0x0040 }, 294 { 12485, 0x0001 }, 295 { 12486, 0x000f }, 296 { 12487, 0x0006 }, 297 { 12488, 0x0001 }, 298 { 12489, 0x0003 }, 299 { 12490, 0x0106 }, 300 { 12492, 0x0061 }, 301 { 12493, 0x0011 }, 302 { 12494, 0x0401 }, 303 { 12496, 0x0050 }, 304 { 12497, 0x0003 }, 305 { 12498, 0x0102 }, 306 { 12500, 0x0061 }, 307 { 12501, 0x003b }, 308 { 12502, 0x0502 }, 309 { 12503, 0x0100 }, 310 { 12504, 0x2fff }, 311 { 12508, 0x2fff }, 312 { 12512, 0x2fff }, 313 { 12516, 0x2fff }, 314 { 12520, 0x2fff }, 315 { 12524, 0x2fff }, 316 { 12528, 0x2fff }, 317 { 12532, 0x2fff }, 318 { 12536, 0x2fff }, 319 { 12540, 0x2fff }, 320 { 12544, 0x0060 }, 321 { 12546, 0x0601 }, 322 { 12548, 0x0050 }, 323 { 12550, 0x0100 }, 324 { 12552, 0x0001 }, 325 { 12554, 0x0104 }, 326 { 12555, 0x0100 }, 327 { 12556, 0x2fff }, 328 { 12560, 0x2fff }, 329 { 12564, 0x2fff }, 330 { 12568, 0x2fff }, 331 { 12572, 0x2fff }, 332 { 12576, 0x2fff }, 333 { 12580, 0x2fff }, 334 { 12584, 0x2fff }, 335 { 12588, 0x2fff }, 336 { 12592, 0x2fff }, 337 { 12596, 0x2fff }, 338 { 12600, 0x2fff }, 339 { 12604, 0x2fff }, 340 { 12608, 0x0061 }, 341 { 12610, 0x0601 }, 342 { 12612, 0x0050 }, 343 { 12614, 0x0102 }, 344 { 12616, 0x0001 }, 345 { 12618, 0x0106 }, 346 { 12619, 0x0100 }, 347 { 12620, 0x2fff }, 348 { 12624, 0x2fff }, 349 { 12628, 0x2fff }, 350 { 12632, 0x2fff }, 351 { 12636, 0x2fff }, 352 { 12640, 0x2fff }, 353 { 12644, 0x2fff }, 354 { 12648, 0x2fff }, 355 { 12652, 0x2fff }, 356 { 12656, 0x2fff }, 357 { 12660, 0x2fff }, 358 { 12664, 0x2fff }, 359 { 12668, 0x2fff }, 360 { 12672, 0x0060 }, 361 { 12674, 0x0601 }, 362 { 12676, 0x0061 }, 363 { 12678, 0x0601 }, 364 { 12680, 0x0050 }, 365 { 12682, 0x0300 }, 366 { 12684, 0x0001 }, 367 { 12686, 0x0304 }, 368 { 12688, 0x0040 }, 369 { 12690, 0x000f }, 370 { 12692, 0x0001 }, 371 { 12695, 0x0100 }, 372}; 373 374struct fll_config { 375 int src; 376 int in; 377 int out; 378}; 379 380struct wm8995_priv { 381 struct regmap *regmap; 382 int sysclk[2]; 383 int mclk[2]; 384 int aifclk[2]; 385 struct fll_config fll[2], fll_suspend[2]; 386 struct regulator_bulk_data supplies[WM8995_NUM_SUPPLIES]; 387 struct notifier_block disable_nb[WM8995_NUM_SUPPLIES]; 388 struct snd_soc_codec *codec; 389}; 390 391/* 392 * We can't use the same notifier block for more than one supply and 393 * there's no way I can see to get from a callback to the caller 394 * except container_of(). 395 */ 396#define WM8995_REGULATOR_EVENT(n) \ 397static int wm8995_regulator_event_##n(struct notifier_block *nb, \ 398 unsigned long event, void *data) \ 399{ \ 400 struct wm8995_priv *wm8995 = container_of(nb, struct wm8995_priv, \ 401 disable_nb[n]); \ 402 if (event & REGULATOR_EVENT_DISABLE) { \ 403 regcache_mark_dirty(wm8995->regmap); \ 404 } \ 405 return 0; \ 406} 407 408WM8995_REGULATOR_EVENT(0) 409WM8995_REGULATOR_EVENT(1) 410WM8995_REGULATOR_EVENT(2) 411WM8995_REGULATOR_EVENT(3) 412WM8995_REGULATOR_EVENT(4) 413WM8995_REGULATOR_EVENT(5) 414WM8995_REGULATOR_EVENT(6) 415WM8995_REGULATOR_EVENT(7) 416 417static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 418static const DECLARE_TLV_DB_SCALE(in1lr_pga_tlv, -1650, 150, 0); 419static const DECLARE_TLV_DB_SCALE(in1l_boost_tlv, 0, 600, 0); 420static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0); 421 422static const char *in1l_text[] = { 423 "Differential", "Single-ended IN1LN", "Single-ended IN1LP" 424}; 425 426static SOC_ENUM_SINGLE_DECL(in1l_enum, WM8995_LEFT_LINE_INPUT_CONTROL, 427 2, in1l_text); 428 429static const char *in1r_text[] = { 430 "Differential", "Single-ended IN1RN", "Single-ended IN1RP" 431}; 432 433static SOC_ENUM_SINGLE_DECL(in1r_enum, WM8995_LEFT_LINE_INPUT_CONTROL, 434 0, in1r_text); 435 436static const char *dmic_src_text[] = { 437 "DMICDAT1", "DMICDAT2", "DMICDAT3" 438}; 439 440static SOC_ENUM_SINGLE_DECL(dmic_src1_enum, WM8995_POWER_MANAGEMENT_5, 441 8, dmic_src_text); 442static SOC_ENUM_SINGLE_DECL(dmic_src2_enum, WM8995_POWER_MANAGEMENT_5, 443 6, dmic_src_text); 444 445static const struct snd_kcontrol_new wm8995_snd_controls[] = { 446 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8995_DAC1_LEFT_VOLUME, 447 WM8995_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv), 448 SOC_DOUBLE_R("DAC1 Switch", WM8995_DAC1_LEFT_VOLUME, 449 WM8995_DAC1_RIGHT_VOLUME, 9, 1, 1), 450 451 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8995_DAC2_LEFT_VOLUME, 452 WM8995_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv), 453 SOC_DOUBLE_R("DAC2 Switch", WM8995_DAC2_LEFT_VOLUME, 454 WM8995_DAC2_RIGHT_VOLUME, 9, 1, 1), 455 456 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8995_AIF1_DAC1_LEFT_VOLUME, 457 WM8995_AIF1_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv), 458 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8995_AIF1_DAC2_LEFT_VOLUME, 459 WM8995_AIF1_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv), 460 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8995_AIF2_DAC_LEFT_VOLUME, 461 WM8995_AIF2_DAC_RIGHT_VOLUME, 0, 96, 0, digital_tlv), 462 463 SOC_DOUBLE_R_TLV("IN1LR Volume", WM8995_LEFT_LINE_INPUT_1_VOLUME, 464 WM8995_RIGHT_LINE_INPUT_1_VOLUME, 0, 31, 0, in1lr_pga_tlv), 465 466 SOC_SINGLE_TLV("IN1L Boost", WM8995_LEFT_LINE_INPUT_CONTROL, 467 4, 3, 0, in1l_boost_tlv), 468 469 SOC_ENUM("IN1L Mode", in1l_enum), 470 SOC_ENUM("IN1R Mode", in1r_enum), 471 472 SOC_ENUM("DMIC1 SRC", dmic_src1_enum), 473 SOC_ENUM("DMIC2 SRC", dmic_src2_enum), 474 475 SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8995_DAC1_MIXER_VOLUMES, 0, 5, 476 24, 0, sidetone_tlv), 477 SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8995_DAC2_MIXER_VOLUMES, 0, 5, 478 24, 0, sidetone_tlv), 479 480 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8995_AIF1_ADC1_LEFT_VOLUME, 481 WM8995_AIF1_ADC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv), 482 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8995_AIF1_ADC2_LEFT_VOLUME, 483 WM8995_AIF1_ADC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv), 484 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8995_AIF2_ADC_LEFT_VOLUME, 485 WM8995_AIF2_ADC_RIGHT_VOLUME, 0, 96, 0, digital_tlv) 486}; 487 488static void wm8995_update_class_w(struct snd_soc_codec *codec) 489{ 490 int enable = 1; 491 int source = 0; /* GCC flow analysis can't track enable */ 492 int reg, reg_r; 493 494 /* We also need the same setting for L/R and only one path */ 495 reg = snd_soc_read(codec, WM8995_DAC1_LEFT_MIXER_ROUTING); 496 switch (reg) { 497 case WM8995_AIF2DACL_TO_DAC1L: 498 dev_dbg(codec->dev, "Class W source AIF2DAC\n"); 499 source = 2 << WM8995_CP_DYN_SRC_SEL_SHIFT; 500 break; 501 case WM8995_AIF1DAC2L_TO_DAC1L: 502 dev_dbg(codec->dev, "Class W source AIF1DAC2\n"); 503 source = 1 << WM8995_CP_DYN_SRC_SEL_SHIFT; 504 break; 505 case WM8995_AIF1DAC1L_TO_DAC1L: 506 dev_dbg(codec->dev, "Class W source AIF1DAC1\n"); 507 source = 0 << WM8995_CP_DYN_SRC_SEL_SHIFT; 508 break; 509 default: 510 dev_dbg(codec->dev, "DAC mixer setting: %x\n", reg); 511 enable = 0; 512 break; 513 } 514 515 reg_r = snd_soc_read(codec, WM8995_DAC1_RIGHT_MIXER_ROUTING); 516 if (reg_r != reg) { 517 dev_dbg(codec->dev, "Left and right DAC mixers different\n"); 518 enable = 0; 519 } 520 521 if (enable) { 522 dev_dbg(codec->dev, "Class W enabled\n"); 523 snd_soc_update_bits(codec, WM8995_CLASS_W_1, 524 WM8995_CP_DYN_PWR_MASK | 525 WM8995_CP_DYN_SRC_SEL_MASK, 526 source | WM8995_CP_DYN_PWR); 527 } else { 528 dev_dbg(codec->dev, "Class W disabled\n"); 529 snd_soc_update_bits(codec, WM8995_CLASS_W_1, 530 WM8995_CP_DYN_PWR_MASK, 0); 531 } 532} 533 534static int check_clk_sys(struct snd_soc_dapm_widget *source, 535 struct snd_soc_dapm_widget *sink) 536{ 537 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm); 538 unsigned int reg; 539 const char *clk; 540 541 reg = snd_soc_read(codec, WM8995_CLOCKING_1); 542 /* Check what we're currently using for CLK_SYS */ 543 if (reg & WM8995_SYSCLK_SRC) 544 clk = "AIF2CLK"; 545 else 546 clk = "AIF1CLK"; 547 return !strcmp(source->name, clk); 548} 549 550static int wm8995_put_class_w(struct snd_kcontrol *kcontrol, 551 struct snd_ctl_elem_value *ucontrol) 552{ 553 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol); 554 int ret; 555 556 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); 557 wm8995_update_class_w(codec); 558 return ret; 559} 560 561static int hp_supply_event(struct snd_soc_dapm_widget *w, 562 struct snd_kcontrol *kcontrol, int event) 563{ 564 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 565 566 switch (event) { 567 case SND_SOC_DAPM_PRE_PMU: 568 /* Enable the headphone amp */ 569 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, 570 WM8995_HPOUT1L_ENA_MASK | 571 WM8995_HPOUT1R_ENA_MASK, 572 WM8995_HPOUT1L_ENA | 573 WM8995_HPOUT1R_ENA); 574 575 /* Enable the second stage */ 576 snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1, 577 WM8995_HPOUT1L_DLY_MASK | 578 WM8995_HPOUT1R_DLY_MASK, 579 WM8995_HPOUT1L_DLY | 580 WM8995_HPOUT1R_DLY); 581 break; 582 case SND_SOC_DAPM_PRE_PMD: 583 snd_soc_update_bits(codec, WM8995_CHARGE_PUMP_1, 584 WM8995_CP_ENA_MASK, 0); 585 break; 586 } 587 588 return 0; 589} 590 591static void dc_servo_cmd(struct snd_soc_codec *codec, 592 unsigned int reg, unsigned int val, unsigned int mask) 593{ 594 int timeout = 10; 595 596 dev_dbg(codec->dev, "%s: reg = %#x, val = %#x, mask = %#x\n", 597 __func__, reg, val, mask); 598 599 snd_soc_write(codec, reg, val); 600 while (timeout--) { 601 msleep(10); 602 val = snd_soc_read(codec, WM8995_DC_SERVO_READBACK_0); 603 if ((val & mask) == mask) 604 return; 605 } 606 607 dev_err(codec->dev, "Timed out waiting for DC Servo\n"); 608} 609 610static int hp_event(struct snd_soc_dapm_widget *w, 611 struct snd_kcontrol *kcontrol, int event) 612{ 613 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 614 unsigned int reg; 615 616 reg = snd_soc_read(codec, WM8995_ANALOGUE_HP_1); 617 618 switch (event) { 619 case SND_SOC_DAPM_POST_PMU: 620 snd_soc_update_bits(codec, WM8995_CHARGE_PUMP_1, 621 WM8995_CP_ENA_MASK, WM8995_CP_ENA); 622 623 msleep(5); 624 625 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, 626 WM8995_HPOUT1L_ENA_MASK | 627 WM8995_HPOUT1R_ENA_MASK, 628 WM8995_HPOUT1L_ENA | WM8995_HPOUT1R_ENA); 629 630 udelay(20); 631 632 reg |= WM8995_HPOUT1L_DLY | WM8995_HPOUT1R_DLY; 633 snd_soc_write(codec, WM8995_ANALOGUE_HP_1, reg); 634 635 snd_soc_write(codec, WM8995_DC_SERVO_1, WM8995_DCS_ENA_CHAN_0 | 636 WM8995_DCS_ENA_CHAN_1); 637 638 dc_servo_cmd(codec, WM8995_DC_SERVO_2, 639 WM8995_DCS_TRIG_STARTUP_0 | 640 WM8995_DCS_TRIG_STARTUP_1, 641 WM8995_DCS_TRIG_DAC_WR_0 | 642 WM8995_DCS_TRIG_DAC_WR_1); 643 644 reg |= WM8995_HPOUT1R_OUTP | WM8995_HPOUT1R_RMV_SHORT | 645 WM8995_HPOUT1L_OUTP | WM8995_HPOUT1L_RMV_SHORT; 646 snd_soc_write(codec, WM8995_ANALOGUE_HP_1, reg); 647 648 break; 649 case SND_SOC_DAPM_PRE_PMD: 650 snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1, 651 WM8995_HPOUT1L_OUTP_MASK | 652 WM8995_HPOUT1R_OUTP_MASK | 653 WM8995_HPOUT1L_RMV_SHORT_MASK | 654 WM8995_HPOUT1R_RMV_SHORT_MASK, 0); 655 656 snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1, 657 WM8995_HPOUT1L_DLY_MASK | 658 WM8995_HPOUT1R_DLY_MASK, 0); 659 660 snd_soc_write(codec, WM8995_DC_SERVO_1, 0); 661 662 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, 663 WM8995_HPOUT1L_ENA_MASK | 664 WM8995_HPOUT1R_ENA_MASK, 665 0); 666 break; 667 } 668 669 return 0; 670} 671 672static int configure_aif_clock(struct snd_soc_codec *codec, int aif) 673{ 674 struct wm8995_priv *wm8995; 675 int rate; 676 int reg1 = 0; 677 int offset; 678 679 wm8995 = snd_soc_codec_get_drvdata(codec); 680 681 if (aif) 682 offset = 4; 683 else 684 offset = 0; 685 686 switch (wm8995->sysclk[aif]) { 687 case WM8995_SYSCLK_MCLK1: 688 rate = wm8995->mclk[0]; 689 break; 690 case WM8995_SYSCLK_MCLK2: 691 reg1 |= 0x8; 692 rate = wm8995->mclk[1]; 693 break; 694 case WM8995_SYSCLK_FLL1: 695 reg1 |= 0x10; 696 rate = wm8995->fll[0].out; 697 break; 698 case WM8995_SYSCLK_FLL2: 699 reg1 |= 0x18; 700 rate = wm8995->fll[1].out; 701 break; 702 default: 703 return -EINVAL; 704 } 705 706 if (rate >= 13500000) { 707 rate /= 2; 708 reg1 |= WM8995_AIF1CLK_DIV; 709 710 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n", 711 aif + 1, rate); 712 } 713 714 wm8995->aifclk[aif] = rate; 715 716 snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1 + offset, 717 WM8995_AIF1CLK_SRC_MASK | WM8995_AIF1CLK_DIV_MASK, 718 reg1); 719 return 0; 720} 721 722static int configure_clock(struct snd_soc_codec *codec) 723{ 724 struct wm8995_priv *wm8995; 725 int change, new; 726 727 wm8995 = snd_soc_codec_get_drvdata(codec); 728 729 /* Bring up the AIF clocks first */ 730 configure_aif_clock(codec, 0); 731 configure_aif_clock(codec, 1); 732 733 /* 734 * Then switch CLK_SYS over to the higher of them; a change 735 * can only happen as a result of a clocking change which can 736 * only be made outside of DAPM so we can safely redo the 737 * clocking. 738 */ 739 740 /* If they're equal it doesn't matter which is used */ 741 if (wm8995->aifclk[0] == wm8995->aifclk[1]) 742 return 0; 743 744 if (wm8995->aifclk[0] < wm8995->aifclk[1]) 745 new = WM8995_SYSCLK_SRC; 746 else 747 new = 0; 748 749 change = snd_soc_update_bits(codec, WM8995_CLOCKING_1, 750 WM8995_SYSCLK_SRC_MASK, new); 751 if (!change) 752 return 0; 753 754 snd_soc_dapm_sync(&codec->dapm); 755 756 return 0; 757} 758 759static int clk_sys_event(struct snd_soc_dapm_widget *w, 760 struct snd_kcontrol *kcontrol, int event) 761{ 762 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 763 764 switch (event) { 765 case SND_SOC_DAPM_PRE_PMU: 766 return configure_clock(codec); 767 768 case SND_SOC_DAPM_POST_PMD: 769 configure_clock(codec); 770 break; 771 } 772 773 return 0; 774} 775 776static const char *sidetone_text[] = { 777 "ADC/DMIC1", "DMIC2", 778}; 779 780static SOC_ENUM_SINGLE_DECL(sidetone1_enum, WM8995_SIDETONE, 0, sidetone_text); 781 782static const struct snd_kcontrol_new sidetone1_mux = 783 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum); 784 785static SOC_ENUM_SINGLE_DECL(sidetone2_enum, WM8995_SIDETONE, 1, sidetone_text); 786 787static const struct snd_kcontrol_new sidetone2_mux = 788 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum); 789 790static const struct snd_kcontrol_new aif1adc1l_mix[] = { 791 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING, 792 1, 1, 0), 793 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING, 794 0, 1, 0), 795}; 796 797static const struct snd_kcontrol_new aif1adc1r_mix[] = { 798 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING, 799 1, 1, 0), 800 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING, 801 0, 1, 0), 802}; 803 804static const struct snd_kcontrol_new aif1adc2l_mix[] = { 805 SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING, 806 1, 1, 0), 807 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING, 808 0, 1, 0), 809}; 810 811static const struct snd_kcontrol_new aif1adc2r_mix[] = { 812 SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING, 813 1, 1, 0), 814 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING, 815 0, 1, 0), 816}; 817 818static const struct snd_kcontrol_new dac1l_mix[] = { 819 WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, 820 5, 1, 0), 821 WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, 822 4, 1, 0), 823 WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, 824 2, 1, 0), 825 WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, 826 1, 1, 0), 827 WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, 828 0, 1, 0), 829}; 830 831static const struct snd_kcontrol_new dac1r_mix[] = { 832 WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, 833 5, 1, 0), 834 WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, 835 4, 1, 0), 836 WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, 837 2, 1, 0), 838 WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, 839 1, 1, 0), 840 WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, 841 0, 1, 0), 842}; 843 844static const struct snd_kcontrol_new aif2dac2l_mix[] = { 845 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, 846 5, 1, 0), 847 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, 848 4, 1, 0), 849 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, 850 2, 1, 0), 851 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, 852 1, 1, 0), 853 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, 854 0, 1, 0), 855}; 856 857static const struct snd_kcontrol_new aif2dac2r_mix[] = { 858 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, 859 5, 1, 0), 860 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, 861 4, 1, 0), 862 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, 863 2, 1, 0), 864 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, 865 1, 1, 0), 866 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, 867 0, 1, 0), 868}; 869 870static const struct snd_kcontrol_new in1l_pga = 871 SOC_DAPM_SINGLE("IN1L Switch", WM8995_POWER_MANAGEMENT_2, 5, 1, 0); 872 873static const struct snd_kcontrol_new in1r_pga = 874 SOC_DAPM_SINGLE("IN1R Switch", WM8995_POWER_MANAGEMENT_2, 4, 1, 0); 875 876static const char *adc_mux_text[] = { 877 "ADC", 878 "DMIC", 879}; 880 881static SOC_ENUM_SINGLE_VIRT_DECL(adc_enum, adc_mux_text); 882 883static const struct snd_kcontrol_new adcl_mux = 884 SOC_DAPM_ENUM("ADCL Mux", adc_enum); 885 886static const struct snd_kcontrol_new adcr_mux = 887 SOC_DAPM_ENUM("ADCR Mux", adc_enum); 888 889static const char *spk_src_text[] = { 890 "DAC1L", "DAC1R", "DAC2L", "DAC2R" 891}; 892 893static SOC_ENUM_SINGLE_DECL(spk1l_src_enum, WM8995_LEFT_PDM_SPEAKER_1, 894 0, spk_src_text); 895static SOC_ENUM_SINGLE_DECL(spk1r_src_enum, WM8995_RIGHT_PDM_SPEAKER_1, 896 0, spk_src_text); 897static SOC_ENUM_SINGLE_DECL(spk2l_src_enum, WM8995_LEFT_PDM_SPEAKER_2, 898 0, spk_src_text); 899static SOC_ENUM_SINGLE_DECL(spk2r_src_enum, WM8995_RIGHT_PDM_SPEAKER_2, 900 0, spk_src_text); 901 902static const struct snd_kcontrol_new spk1l_mux = 903 SOC_DAPM_ENUM("SPK1L SRC", spk1l_src_enum); 904static const struct snd_kcontrol_new spk1r_mux = 905 SOC_DAPM_ENUM("SPK1R SRC", spk1r_src_enum); 906static const struct snd_kcontrol_new spk2l_mux = 907 SOC_DAPM_ENUM("SPK2L SRC", spk2l_src_enum); 908static const struct snd_kcontrol_new spk2r_mux = 909 SOC_DAPM_ENUM("SPK2R SRC", spk2r_src_enum); 910 911static const struct snd_soc_dapm_widget wm8995_dapm_widgets[] = { 912 SND_SOC_DAPM_INPUT("DMIC1DAT"), 913 SND_SOC_DAPM_INPUT("DMIC2DAT"), 914 915 SND_SOC_DAPM_INPUT("IN1L"), 916 SND_SOC_DAPM_INPUT("IN1R"), 917 918 SND_SOC_DAPM_MIXER("IN1L PGA", SND_SOC_NOPM, 0, 0, 919 &in1l_pga, 1), 920 SND_SOC_DAPM_MIXER("IN1R PGA", SND_SOC_NOPM, 0, 0, 921 &in1r_pga, 1), 922 923 SND_SOC_DAPM_SUPPLY("MICBIAS1", WM8995_POWER_MANAGEMENT_1, 8, 0, 924 NULL, 0), 925 SND_SOC_DAPM_SUPPLY("MICBIAS2", WM8995_POWER_MANAGEMENT_1, 9, 0, 926 NULL, 0), 927 928 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8995_AIF1_CLOCKING_1, 0, 0, NULL, 0), 929 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8995_AIF2_CLOCKING_1, 0, 0, NULL, 0), 930 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8995_CLOCKING_1, 3, 0, NULL, 0), 931 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8995_CLOCKING_1, 2, 0, NULL, 0), 932 SND_SOC_DAPM_SUPPLY("SYSDSPCLK", WM8995_CLOCKING_1, 1, 0, NULL, 0), 933 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event, 934 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 935 936 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture", 0, 937 WM8995_POWER_MANAGEMENT_3, 9, 0), 938 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture", 0, 939 WM8995_POWER_MANAGEMENT_3, 8, 0), 940 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, 941 SND_SOC_NOPM, 0, 0), 942 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture", 943 0, WM8995_POWER_MANAGEMENT_3, 11, 0), 944 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture", 945 0, WM8995_POWER_MANAGEMENT_3, 10, 0), 946 947 SND_SOC_DAPM_MUX("ADCL Mux", SND_SOC_NOPM, 1, 0, &adcl_mux), 948 SND_SOC_DAPM_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0, &adcr_mux), 949 950 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8995_POWER_MANAGEMENT_3, 5, 0), 951 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8995_POWER_MANAGEMENT_3, 4, 0), 952 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8995_POWER_MANAGEMENT_3, 3, 0), 953 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8995_POWER_MANAGEMENT_3, 2, 0), 954 955 SND_SOC_DAPM_ADC("ADCL", NULL, WM8995_POWER_MANAGEMENT_3, 1, 0), 956 SND_SOC_DAPM_ADC("ADCR", NULL, WM8995_POWER_MANAGEMENT_3, 0, 0), 957 958 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0, 959 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)), 960 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0, 961 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)), 962 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0, 963 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)), 964 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0, 965 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)), 966 967 SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0, WM8995_POWER_MANAGEMENT_4, 968 9, 0), 969 SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0, WM8995_POWER_MANAGEMENT_4, 970 8, 0), 971 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 972 0, 0), 973 974 SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0, WM8995_POWER_MANAGEMENT_4, 975 11, 0), 976 SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0, WM8995_POWER_MANAGEMENT_4, 977 10, 0), 978 979 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0, 980 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)), 981 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0, 982 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)), 983 984 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8995_POWER_MANAGEMENT_4, 3, 0), 985 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8995_POWER_MANAGEMENT_4, 2, 0), 986 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8995_POWER_MANAGEMENT_4, 1, 0), 987 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8995_POWER_MANAGEMENT_4, 0, 0), 988 989 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, dac1l_mix, 990 ARRAY_SIZE(dac1l_mix)), 991 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, dac1r_mix, 992 ARRAY_SIZE(dac1r_mix)), 993 994 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux), 995 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux), 996 997 SND_SOC_DAPM_PGA_E("Headphone PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 998 hp_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 999 1000 SND_SOC_DAPM_SUPPLY("Headphone Supply", SND_SOC_NOPM, 0, 0, 1001 hp_supply_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 1002 1003 SND_SOC_DAPM_MUX("SPK1L Driver", WM8995_LEFT_PDM_SPEAKER_1, 1004 4, 0, &spk1l_mux), 1005 SND_SOC_DAPM_MUX("SPK1R Driver", WM8995_RIGHT_PDM_SPEAKER_1, 1006 4, 0, &spk1r_mux), 1007 SND_SOC_DAPM_MUX("SPK2L Driver", WM8995_LEFT_PDM_SPEAKER_2, 1008 4, 0, &spk2l_mux), 1009 SND_SOC_DAPM_MUX("SPK2R Driver", WM8995_RIGHT_PDM_SPEAKER_2, 1010 4, 0, &spk2r_mux), 1011 1012 SND_SOC_DAPM_SUPPLY("LDO2", WM8995_POWER_MANAGEMENT_2, 1, 0, NULL, 0), 1013 1014 SND_SOC_DAPM_OUTPUT("HP1L"), 1015 SND_SOC_DAPM_OUTPUT("HP1R"), 1016 SND_SOC_DAPM_OUTPUT("SPK1L"), 1017 SND_SOC_DAPM_OUTPUT("SPK1R"), 1018 SND_SOC_DAPM_OUTPUT("SPK2L"), 1019 SND_SOC_DAPM_OUTPUT("SPK2R") 1020}; 1021 1022static const struct snd_soc_dapm_route wm8995_intercon[] = { 1023 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys }, 1024 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys }, 1025 1026 { "DSP1CLK", NULL, "CLK_SYS" }, 1027 { "DSP2CLK", NULL, "CLK_SYS" }, 1028 { "SYSDSPCLK", NULL, "CLK_SYS" }, 1029 1030 { "AIF1ADC1L", NULL, "AIF1CLK" }, 1031 { "AIF1ADC1L", NULL, "DSP1CLK" }, 1032 { "AIF1ADC1R", NULL, "AIF1CLK" }, 1033 { "AIF1ADC1R", NULL, "DSP1CLK" }, 1034 { "AIF1ADC1R", NULL, "SYSDSPCLK" }, 1035 1036 { "AIF1ADC2L", NULL, "AIF1CLK" }, 1037 { "AIF1ADC2L", NULL, "DSP1CLK" }, 1038 { "AIF1ADC2R", NULL, "AIF1CLK" }, 1039 { "AIF1ADC2R", NULL, "DSP1CLK" }, 1040 { "AIF1ADC2R", NULL, "SYSDSPCLK" }, 1041 1042 { "DMIC1L", NULL, "DMIC1DAT" }, 1043 { "DMIC1L", NULL, "CLK_SYS" }, 1044 { "DMIC1R", NULL, "DMIC1DAT" }, 1045 { "DMIC1R", NULL, "CLK_SYS" }, 1046 { "DMIC2L", NULL, "DMIC2DAT" }, 1047 { "DMIC2L", NULL, "CLK_SYS" }, 1048 { "DMIC2R", NULL, "DMIC2DAT" }, 1049 { "DMIC2R", NULL, "CLK_SYS" }, 1050 1051 { "ADCL", NULL, "AIF1CLK" }, 1052 { "ADCL", NULL, "DSP1CLK" }, 1053 { "ADCL", NULL, "SYSDSPCLK" }, 1054 1055 { "ADCR", NULL, "AIF1CLK" }, 1056 { "ADCR", NULL, "DSP1CLK" }, 1057 { "ADCR", NULL, "SYSDSPCLK" }, 1058 1059 { "IN1L PGA", "IN1L Switch", "IN1L" }, 1060 { "IN1R PGA", "IN1R Switch", "IN1R" }, 1061 { "IN1L PGA", NULL, "LDO2" }, 1062 { "IN1R PGA", NULL, "LDO2" }, 1063 1064 { "ADCL", NULL, "IN1L PGA" }, 1065 { "ADCR", NULL, "IN1R PGA" }, 1066 1067 { "ADCL Mux", "ADC", "ADCL" }, 1068 { "ADCL Mux", "DMIC", "DMIC1L" }, 1069 { "ADCR Mux", "ADC", "ADCR" }, 1070 { "ADCR Mux", "DMIC", "DMIC1R" }, 1071 1072 /* AIF1 outputs */ 1073 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" }, 1074 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" }, 1075 1076 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" }, 1077 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" }, 1078 1079 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" }, 1080 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" }, 1081 1082 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" }, 1083 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" }, 1084 1085 /* Sidetone */ 1086 { "Left Sidetone", "ADC/DMIC1", "AIF1ADC1L" }, 1087 { "Left Sidetone", "DMIC2", "AIF1ADC2L" }, 1088 { "Right Sidetone", "ADC/DMIC1", "AIF1ADC1R" }, 1089 { "Right Sidetone", "DMIC2", "AIF1ADC2R" }, 1090 1091 { "AIF1DAC1L", NULL, "AIF1CLK" }, 1092 { "AIF1DAC1L", NULL, "DSP1CLK" }, 1093 { "AIF1DAC1R", NULL, "AIF1CLK" }, 1094 { "AIF1DAC1R", NULL, "DSP1CLK" }, 1095 { "AIF1DAC1R", NULL, "SYSDSPCLK" }, 1096 1097 { "AIF1DAC2L", NULL, "AIF1CLK" }, 1098 { "AIF1DAC2L", NULL, "DSP1CLK" }, 1099 { "AIF1DAC2R", NULL, "AIF1CLK" }, 1100 { "AIF1DAC2R", NULL, "DSP1CLK" }, 1101 { "AIF1DAC2R", NULL, "SYSDSPCLK" }, 1102 1103 { "DAC1L", NULL, "AIF1CLK" }, 1104 { "DAC1L", NULL, "DSP1CLK" }, 1105 { "DAC1L", NULL, "SYSDSPCLK" }, 1106 1107 { "DAC1R", NULL, "AIF1CLK" }, 1108 { "DAC1R", NULL, "DSP1CLK" }, 1109 { "DAC1R", NULL, "SYSDSPCLK" }, 1110 1111 { "AIF1DAC1L", NULL, "AIF1DACDAT" }, 1112 { "AIF1DAC1R", NULL, "AIF1DACDAT" }, 1113 { "AIF1DAC2L", NULL, "AIF1DACDAT" }, 1114 { "AIF1DAC2R", NULL, "AIF1DACDAT" }, 1115 1116 /* DAC1 inputs */ 1117 { "DAC1L", NULL, "DAC1L Mixer" }, 1118 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, 1119 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, 1120 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1121 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1122 1123 { "DAC1R", NULL, "DAC1R Mixer" }, 1124 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, 1125 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, 1126 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1127 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1128 1129 /* DAC2/AIF2 outputs */ 1130 { "DAC2L", NULL, "AIF2DAC2L Mixer" }, 1131 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, 1132 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, 1133 1134 { "DAC2R", NULL, "AIF2DAC2R Mixer" }, 1135 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, 1136 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, 1137 1138 /* Output stages */ 1139 { "Headphone PGA", NULL, "DAC1L" }, 1140 { "Headphone PGA", NULL, "DAC1R" }, 1141 1142 { "Headphone PGA", NULL, "DAC2L" }, 1143 { "Headphone PGA", NULL, "DAC2R" }, 1144 1145 { "Headphone PGA", NULL, "Headphone Supply" }, 1146 { "Headphone PGA", NULL, "CLK_SYS" }, 1147 { "Headphone PGA", NULL, "LDO2" }, 1148 1149 { "HP1L", NULL, "Headphone PGA" }, 1150 { "HP1R", NULL, "Headphone PGA" }, 1151 1152 { "SPK1L Driver", "DAC1L", "DAC1L" }, 1153 { "SPK1L Driver", "DAC1R", "DAC1R" }, 1154 { "SPK1L Driver", "DAC2L", "DAC2L" }, 1155 { "SPK1L Driver", "DAC2R", "DAC2R" }, 1156 { "SPK1L Driver", NULL, "CLK_SYS" }, 1157 1158 { "SPK1R Driver", "DAC1L", "DAC1L" }, 1159 { "SPK1R Driver", "DAC1R", "DAC1R" }, 1160 { "SPK1R Driver", "DAC2L", "DAC2L" }, 1161 { "SPK1R Driver", "DAC2R", "DAC2R" }, 1162 { "SPK1R Driver", NULL, "CLK_SYS" }, 1163 1164 { "SPK2L Driver", "DAC1L", "DAC1L" }, 1165 { "SPK2L Driver", "DAC1R", "DAC1R" }, 1166 { "SPK2L Driver", "DAC2L", "DAC2L" }, 1167 { "SPK2L Driver", "DAC2R", "DAC2R" }, 1168 { "SPK2L Driver", NULL, "CLK_SYS" }, 1169 1170 { "SPK2R Driver", "DAC1L", "DAC1L" }, 1171 { "SPK2R Driver", "DAC1R", "DAC1R" }, 1172 { "SPK2R Driver", "DAC2L", "DAC2L" }, 1173 { "SPK2R Driver", "DAC2R", "DAC2R" }, 1174 { "SPK2R Driver", NULL, "CLK_SYS" }, 1175 1176 { "SPK1L", NULL, "SPK1L Driver" }, 1177 { "SPK1R", NULL, "SPK1R Driver" }, 1178 { "SPK2L", NULL, "SPK2L Driver" }, 1179 { "SPK2R", NULL, "SPK2R Driver" } 1180}; 1181 1182static bool wm8995_readable(struct device *dev, unsigned int reg) 1183{ 1184 switch (reg) { 1185 case WM8995_SOFTWARE_RESET: 1186 case WM8995_POWER_MANAGEMENT_1: 1187 case WM8995_POWER_MANAGEMENT_2: 1188 case WM8995_POWER_MANAGEMENT_3: 1189 case WM8995_POWER_MANAGEMENT_4: 1190 case WM8995_POWER_MANAGEMENT_5: 1191 case WM8995_LEFT_LINE_INPUT_1_VOLUME: 1192 case WM8995_RIGHT_LINE_INPUT_1_VOLUME: 1193 case WM8995_LEFT_LINE_INPUT_CONTROL: 1194 case WM8995_DAC1_LEFT_VOLUME: 1195 case WM8995_DAC1_RIGHT_VOLUME: 1196 case WM8995_DAC2_LEFT_VOLUME: 1197 case WM8995_DAC2_RIGHT_VOLUME: 1198 case WM8995_OUTPUT_VOLUME_ZC_1: 1199 case WM8995_MICBIAS_1: 1200 case WM8995_MICBIAS_2: 1201 case WM8995_LDO_1: 1202 case WM8995_LDO_2: 1203 case WM8995_ACCESSORY_DETECT_MODE1: 1204 case WM8995_ACCESSORY_DETECT_MODE2: 1205 case WM8995_HEADPHONE_DETECT1: 1206 case WM8995_HEADPHONE_DETECT2: 1207 case WM8995_MIC_DETECT_1: 1208 case WM8995_MIC_DETECT_2: 1209 case WM8995_CHARGE_PUMP_1: 1210 case WM8995_CLASS_W_1: 1211 case WM8995_DC_SERVO_1: 1212 case WM8995_DC_SERVO_2: 1213 case WM8995_DC_SERVO_3: 1214 case WM8995_DC_SERVO_5: 1215 case WM8995_DC_SERVO_6: 1216 case WM8995_DC_SERVO_7: 1217 case WM8995_DC_SERVO_READBACK_0: 1218 case WM8995_ANALOGUE_HP_1: 1219 case WM8995_ANALOGUE_HP_2: 1220 case WM8995_CHIP_REVISION: 1221 case WM8995_CONTROL_INTERFACE_1: 1222 case WM8995_CONTROL_INTERFACE_2: 1223 case WM8995_WRITE_SEQUENCER_CTRL_1: 1224 case WM8995_WRITE_SEQUENCER_CTRL_2: 1225 case WM8995_AIF1_CLOCKING_1: 1226 case WM8995_AIF1_CLOCKING_2: 1227 case WM8995_AIF2_CLOCKING_1: 1228 case WM8995_AIF2_CLOCKING_2: 1229 case WM8995_CLOCKING_1: 1230 case WM8995_CLOCKING_2: 1231 case WM8995_AIF1_RATE: 1232 case WM8995_AIF2_RATE: 1233 case WM8995_RATE_STATUS: 1234 case WM8995_FLL1_CONTROL_1: 1235 case WM8995_FLL1_CONTROL_2: 1236 case WM8995_FLL1_CONTROL_3: 1237 case WM8995_FLL1_CONTROL_4: 1238 case WM8995_FLL1_CONTROL_5: 1239 case WM8995_FLL2_CONTROL_1: 1240 case WM8995_FLL2_CONTROL_2: 1241 case WM8995_FLL2_CONTROL_3: 1242 case WM8995_FLL2_CONTROL_4: 1243 case WM8995_FLL2_CONTROL_5: 1244 case WM8995_AIF1_CONTROL_1: 1245 case WM8995_AIF1_CONTROL_2: 1246 case WM8995_AIF1_MASTER_SLAVE: 1247 case WM8995_AIF1_BCLK: 1248 case WM8995_AIF1ADC_LRCLK: 1249 case WM8995_AIF1DAC_LRCLK: 1250 case WM8995_AIF1DAC_DATA: 1251 case WM8995_AIF1ADC_DATA: 1252 case WM8995_AIF2_CONTROL_1: 1253 case WM8995_AIF2_CONTROL_2: 1254 case WM8995_AIF2_MASTER_SLAVE: 1255 case WM8995_AIF2_BCLK: 1256 case WM8995_AIF2ADC_LRCLK: 1257 case WM8995_AIF2DAC_LRCLK: 1258 case WM8995_AIF2DAC_DATA: 1259 case WM8995_AIF2ADC_DATA: 1260 case WM8995_AIF1_ADC1_LEFT_VOLUME: 1261 case WM8995_AIF1_ADC1_RIGHT_VOLUME: 1262 case WM8995_AIF1_DAC1_LEFT_VOLUME: 1263 case WM8995_AIF1_DAC1_RIGHT_VOLUME: 1264 case WM8995_AIF1_ADC2_LEFT_VOLUME: 1265 case WM8995_AIF1_ADC2_RIGHT_VOLUME: 1266 case WM8995_AIF1_DAC2_LEFT_VOLUME: 1267 case WM8995_AIF1_DAC2_RIGHT_VOLUME: 1268 case WM8995_AIF1_ADC1_FILTERS: 1269 case WM8995_AIF1_ADC2_FILTERS: 1270 case WM8995_AIF1_DAC1_FILTERS_1: 1271 case WM8995_AIF1_DAC1_FILTERS_2: 1272 case WM8995_AIF1_DAC2_FILTERS_1: 1273 case WM8995_AIF1_DAC2_FILTERS_2: 1274 case WM8995_AIF1_DRC1_1: 1275 case WM8995_AIF1_DRC1_2: 1276 case WM8995_AIF1_DRC1_3: 1277 case WM8995_AIF1_DRC1_4: 1278 case WM8995_AIF1_DRC1_5: 1279 case WM8995_AIF1_DRC2_1: 1280 case WM8995_AIF1_DRC2_2: 1281 case WM8995_AIF1_DRC2_3: 1282 case WM8995_AIF1_DRC2_4: 1283 case WM8995_AIF1_DRC2_5: 1284 case WM8995_AIF1_DAC1_EQ_GAINS_1: 1285 case WM8995_AIF1_DAC1_EQ_GAINS_2: 1286 case WM8995_AIF1_DAC1_EQ_BAND_1_A: 1287 case WM8995_AIF1_DAC1_EQ_BAND_1_B: 1288 case WM8995_AIF1_DAC1_EQ_BAND_1_PG: 1289 case WM8995_AIF1_DAC1_EQ_BAND_2_A: 1290 case WM8995_AIF1_DAC1_EQ_BAND_2_B: 1291 case WM8995_AIF1_DAC1_EQ_BAND_2_C: 1292 case WM8995_AIF1_DAC1_EQ_BAND_2_PG: 1293 case WM8995_AIF1_DAC1_EQ_BAND_3_A: 1294 case WM8995_AIF1_DAC1_EQ_BAND_3_B: 1295 case WM8995_AIF1_DAC1_EQ_BAND_3_C: 1296 case WM8995_AIF1_DAC1_EQ_BAND_3_PG: 1297 case WM8995_AIF1_DAC1_EQ_BAND_4_A: 1298 case WM8995_AIF1_DAC1_EQ_BAND_4_B: 1299 case WM8995_AIF1_DAC1_EQ_BAND_4_C: 1300 case WM8995_AIF1_DAC1_EQ_BAND_4_PG: 1301 case WM8995_AIF1_DAC1_EQ_BAND_5_A: 1302 case WM8995_AIF1_DAC1_EQ_BAND_5_B: 1303 case WM8995_AIF1_DAC1_EQ_BAND_5_PG: 1304 case WM8995_AIF1_DAC2_EQ_GAINS_1: 1305 case WM8995_AIF1_DAC2_EQ_GAINS_2: 1306 case WM8995_AIF1_DAC2_EQ_BAND_1_A: 1307 case WM8995_AIF1_DAC2_EQ_BAND_1_B: 1308 case WM8995_AIF1_DAC2_EQ_BAND_1_PG: 1309 case WM8995_AIF1_DAC2_EQ_BAND_2_A: 1310 case WM8995_AIF1_DAC2_EQ_BAND_2_B: 1311 case WM8995_AIF1_DAC2_EQ_BAND_2_C: 1312 case WM8995_AIF1_DAC2_EQ_BAND_2_PG: 1313 case WM8995_AIF1_DAC2_EQ_BAND_3_A: 1314 case WM8995_AIF1_DAC2_EQ_BAND_3_B: 1315 case WM8995_AIF1_DAC2_EQ_BAND_3_C: 1316 case WM8995_AIF1_DAC2_EQ_BAND_3_PG: 1317 case WM8995_AIF1_DAC2_EQ_BAND_4_A: 1318 case WM8995_AIF1_DAC2_EQ_BAND_4_B: 1319 case WM8995_AIF1_DAC2_EQ_BAND_4_C: 1320 case WM8995_AIF1_DAC2_EQ_BAND_4_PG: 1321 case WM8995_AIF1_DAC2_EQ_BAND_5_A: 1322 case WM8995_AIF1_DAC2_EQ_BAND_5_B: 1323 case WM8995_AIF1_DAC2_EQ_BAND_5_PG: 1324 case WM8995_AIF2_ADC_LEFT_VOLUME: 1325 case WM8995_AIF2_ADC_RIGHT_VOLUME: 1326 case WM8995_AIF2_DAC_LEFT_VOLUME: 1327 case WM8995_AIF2_DAC_RIGHT_VOLUME: 1328 case WM8995_AIF2_ADC_FILTERS: 1329 case WM8995_AIF2_DAC_FILTERS_1: 1330 case WM8995_AIF2_DAC_FILTERS_2: 1331 case WM8995_AIF2_DRC_1: 1332 case WM8995_AIF2_DRC_2: 1333 case WM8995_AIF2_DRC_3: 1334 case WM8995_AIF2_DRC_4: 1335 case WM8995_AIF2_DRC_5: 1336 case WM8995_AIF2_EQ_GAINS_1: 1337 case WM8995_AIF2_EQ_GAINS_2: 1338 case WM8995_AIF2_EQ_BAND_1_A: 1339 case WM8995_AIF2_EQ_BAND_1_B: 1340 case WM8995_AIF2_EQ_BAND_1_PG: 1341 case WM8995_AIF2_EQ_BAND_2_A: 1342 case WM8995_AIF2_EQ_BAND_2_B: 1343 case WM8995_AIF2_EQ_BAND_2_C: 1344 case WM8995_AIF2_EQ_BAND_2_PG: 1345 case WM8995_AIF2_EQ_BAND_3_A: 1346 case WM8995_AIF2_EQ_BAND_3_B: 1347 case WM8995_AIF2_EQ_BAND_3_C: 1348 case WM8995_AIF2_EQ_BAND_3_PG: 1349 case WM8995_AIF2_EQ_BAND_4_A: 1350 case WM8995_AIF2_EQ_BAND_4_B: 1351 case WM8995_AIF2_EQ_BAND_4_C: 1352 case WM8995_AIF2_EQ_BAND_4_PG: 1353 case WM8995_AIF2_EQ_BAND_5_A: 1354 case WM8995_AIF2_EQ_BAND_5_B: 1355 case WM8995_AIF2_EQ_BAND_5_PG: 1356 case WM8995_DAC1_MIXER_VOLUMES: 1357 case WM8995_DAC1_LEFT_MIXER_ROUTING: 1358 case WM8995_DAC1_RIGHT_MIXER_ROUTING: 1359 case WM8995_DAC2_MIXER_VOLUMES: 1360 case WM8995_DAC2_LEFT_MIXER_ROUTING: 1361 case WM8995_DAC2_RIGHT_MIXER_ROUTING: 1362 case WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING: 1363 case WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING: 1364 case WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING: 1365 case WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING: 1366 case WM8995_DAC_SOFTMUTE: 1367 case WM8995_OVERSAMPLING: 1368 case WM8995_SIDETONE: 1369 case WM8995_GPIO_1: 1370 case WM8995_GPIO_2: 1371 case WM8995_GPIO_3: 1372 case WM8995_GPIO_4: 1373 case WM8995_GPIO_5: 1374 case WM8995_GPIO_6: 1375 case WM8995_GPIO_7: 1376 case WM8995_GPIO_8: 1377 case WM8995_GPIO_9: 1378 case WM8995_GPIO_10: 1379 case WM8995_GPIO_11: 1380 case WM8995_GPIO_12: 1381 case WM8995_GPIO_13: 1382 case WM8995_GPIO_14: 1383 case WM8995_PULL_CONTROL_1: 1384 case WM8995_PULL_CONTROL_2: 1385 case WM8995_INTERRUPT_STATUS_1: 1386 case WM8995_INTERRUPT_STATUS_2: 1387 case WM8995_INTERRUPT_RAW_STATUS_2: 1388 case WM8995_INTERRUPT_STATUS_1_MASK: 1389 case WM8995_INTERRUPT_STATUS_2_MASK: 1390 case WM8995_INTERRUPT_CONTROL: 1391 case WM8995_LEFT_PDM_SPEAKER_1: 1392 case WM8995_RIGHT_PDM_SPEAKER_1: 1393 case WM8995_PDM_SPEAKER_1_MUTE_SEQUENCE: 1394 case WM8995_LEFT_PDM_SPEAKER_2: 1395 case WM8995_RIGHT_PDM_SPEAKER_2: 1396 case WM8995_PDM_SPEAKER_2_MUTE_SEQUENCE: 1397 return true; 1398 default: 1399 return false; 1400 } 1401} 1402 1403static bool wm8995_volatile(struct device *dev, unsigned int reg) 1404{ 1405 switch (reg) { 1406 case WM8995_SOFTWARE_RESET: 1407 case WM8995_DC_SERVO_READBACK_0: 1408 case WM8995_INTERRUPT_STATUS_1: 1409 case WM8995_INTERRUPT_STATUS_2: 1410 case WM8995_INTERRUPT_CONTROL: 1411 case WM8995_ACCESSORY_DETECT_MODE1: 1412 case WM8995_ACCESSORY_DETECT_MODE2: 1413 case WM8995_HEADPHONE_DETECT1: 1414 case WM8995_HEADPHONE_DETECT2: 1415 case WM8995_RATE_STATUS: 1416 return true; 1417 default: 1418 return false; 1419 } 1420} 1421 1422static int wm8995_aif_mute(struct snd_soc_dai *dai, int mute) 1423{ 1424 struct snd_soc_codec *codec = dai->codec; 1425 int mute_reg; 1426 1427 switch (dai->id) { 1428 case 0: 1429 mute_reg = WM8995_AIF1_DAC1_FILTERS_1; 1430 break; 1431 case 1: 1432 mute_reg = WM8995_AIF2_DAC_FILTERS_1; 1433 break; 1434 default: 1435 return -EINVAL; 1436 } 1437 1438 snd_soc_update_bits(codec, mute_reg, WM8995_AIF1DAC1_MUTE_MASK, 1439 !!mute << WM8995_AIF1DAC1_MUTE_SHIFT); 1440 return 0; 1441} 1442 1443static int wm8995_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1444{ 1445 struct snd_soc_codec *codec; 1446 int master; 1447 int aif; 1448 1449 codec = dai->codec; 1450 1451 master = 0; 1452 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1453 case SND_SOC_DAIFMT_CBS_CFS: 1454 break; 1455 case SND_SOC_DAIFMT_CBM_CFM: 1456 master = WM8995_AIF1_MSTR; 1457 break; 1458 default: 1459 dev_err(dai->dev, "Unknown master/slave configuration\n"); 1460 return -EINVAL; 1461 } 1462 1463 aif = 0; 1464 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1465 case SND_SOC_DAIFMT_DSP_B: 1466 aif |= WM8995_AIF1_LRCLK_INV; 1467 case SND_SOC_DAIFMT_DSP_A: 1468 aif |= (0x3 << WM8995_AIF1_FMT_SHIFT); 1469 break; 1470 case SND_SOC_DAIFMT_I2S: 1471 aif |= (0x2 << WM8995_AIF1_FMT_SHIFT); 1472 break; 1473 case SND_SOC_DAIFMT_RIGHT_J: 1474 break; 1475 case SND_SOC_DAIFMT_LEFT_J: 1476 aif |= (0x1 << WM8995_AIF1_FMT_SHIFT); 1477 break; 1478 default: 1479 dev_err(dai->dev, "Unknown dai format\n"); 1480 return -EINVAL; 1481 } 1482 1483 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1484 case SND_SOC_DAIFMT_DSP_A: 1485 case SND_SOC_DAIFMT_DSP_B: 1486 /* frame inversion not valid for DSP modes */ 1487 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1488 case SND_SOC_DAIFMT_NB_NF: 1489 break; 1490 case SND_SOC_DAIFMT_IB_NF: 1491 aif |= WM8995_AIF1_BCLK_INV; 1492 break; 1493 default: 1494 return -EINVAL; 1495 } 1496 break; 1497 1498 case SND_SOC_DAIFMT_I2S: 1499 case SND_SOC_DAIFMT_RIGHT_J: 1500 case SND_SOC_DAIFMT_LEFT_J: 1501 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1502 case SND_SOC_DAIFMT_NB_NF: 1503 break; 1504 case SND_SOC_DAIFMT_IB_IF: 1505 aif |= WM8995_AIF1_BCLK_INV | WM8995_AIF1_LRCLK_INV; 1506 break; 1507 case SND_SOC_DAIFMT_IB_NF: 1508 aif |= WM8995_AIF1_BCLK_INV; 1509 break; 1510 case SND_SOC_DAIFMT_NB_IF: 1511 aif |= WM8995_AIF1_LRCLK_INV; 1512 break; 1513 default: 1514 return -EINVAL; 1515 } 1516 break; 1517 default: 1518 return -EINVAL; 1519 } 1520 1521 snd_soc_update_bits(codec, WM8995_AIF1_CONTROL_1, 1522 WM8995_AIF1_BCLK_INV_MASK | 1523 WM8995_AIF1_LRCLK_INV_MASK | 1524 WM8995_AIF1_FMT_MASK, aif); 1525 snd_soc_update_bits(codec, WM8995_AIF1_MASTER_SLAVE, 1526 WM8995_AIF1_MSTR_MASK, master); 1527 return 0; 1528} 1529 1530static const int srs[] = { 1531 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 1532 48000, 88200, 96000 1533}; 1534 1535static const int fs_ratios[] = { 1536 -1 /* reserved */, 1537 128, 192, 256, 384, 512, 768, 1024, 1408, 1536 1538}; 1539 1540static const int bclk_divs[] = { 1541 10, 15, 20, 30, 40, 55, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480 1542}; 1543 1544static int wm8995_hw_params(struct snd_pcm_substream *substream, 1545 struct snd_pcm_hw_params *params, 1546 struct snd_soc_dai *dai) 1547{ 1548 struct snd_soc_codec *codec; 1549 struct wm8995_priv *wm8995; 1550 int aif1_reg; 1551 int bclk_reg; 1552 int lrclk_reg; 1553 int rate_reg; 1554 int bclk_rate; 1555 int aif1; 1556 int lrclk, bclk; 1557 int i, rate_val, best, best_val, cur_val; 1558 1559 codec = dai->codec; 1560 wm8995 = snd_soc_codec_get_drvdata(codec); 1561 1562 switch (dai->id) { 1563 case 0: 1564 aif1_reg = WM8995_AIF1_CONTROL_1; 1565 bclk_reg = WM8995_AIF1_BCLK; 1566 rate_reg = WM8995_AIF1_RATE; 1567 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* || 1568 wm8995->lrclk_shared[0] */) { 1569 lrclk_reg = WM8995_AIF1DAC_LRCLK; 1570 } else { 1571 lrclk_reg = WM8995_AIF1ADC_LRCLK; 1572 dev_dbg(codec->dev, "AIF1 using split LRCLK\n"); 1573 } 1574 break; 1575 case 1: 1576 aif1_reg = WM8995_AIF2_CONTROL_1; 1577 bclk_reg = WM8995_AIF2_BCLK; 1578 rate_reg = WM8995_AIF2_RATE; 1579 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* || 1580 wm8995->lrclk_shared[1] */) { 1581 lrclk_reg = WM8995_AIF2DAC_LRCLK; 1582 } else { 1583 lrclk_reg = WM8995_AIF2ADC_LRCLK; 1584 dev_dbg(codec->dev, "AIF2 using split LRCLK\n"); 1585 } 1586 break; 1587 default: 1588 return -EINVAL; 1589 } 1590 1591 bclk_rate = snd_soc_params_to_bclk(params); 1592 if (bclk_rate < 0) 1593 return bclk_rate; 1594 1595 aif1 = 0; 1596 switch (params_width(params)) { 1597 case 16: 1598 break; 1599 case 20: 1600 aif1 |= (0x1 << WM8995_AIF1_WL_SHIFT); 1601 break; 1602 case 24: 1603 aif1 |= (0x2 << WM8995_AIF1_WL_SHIFT); 1604 break; 1605 case 32: 1606 aif1 |= (0x3 << WM8995_AIF1_WL_SHIFT); 1607 break; 1608 default: 1609 dev_err(dai->dev, "Unsupported word length %u\n", 1610 params_width(params)); 1611 return -EINVAL; 1612 } 1613 1614 /* try to find a suitable sample rate */ 1615 for (i = 0; i < ARRAY_SIZE(srs); ++i) 1616 if (srs[i] == params_rate(params)) 1617 break; 1618 if (i == ARRAY_SIZE(srs)) { 1619 dev_err(dai->dev, "Sample rate %d is not supported\n", 1620 params_rate(params)); 1621 return -EINVAL; 1622 } 1623 rate_val = i << WM8995_AIF1_SR_SHIFT; 1624 1625 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i]); 1626 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n", 1627 dai->id + 1, wm8995->aifclk[dai->id], bclk_rate); 1628 1629 /* AIFCLK/fs ratio; look for a close match in either direction */ 1630 best = 1; 1631 best_val = abs((fs_ratios[1] * params_rate(params)) 1632 - wm8995->aifclk[dai->id]); 1633 for (i = 2; i < ARRAY_SIZE(fs_ratios); i++) { 1634 cur_val = abs((fs_ratios[i] * params_rate(params)) 1635 - wm8995->aifclk[dai->id]); 1636 if (cur_val >= best_val) 1637 continue; 1638 best = i; 1639 best_val = cur_val; 1640 } 1641 rate_val |= best; 1642 1643 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n", 1644 dai->id + 1, fs_ratios[best]); 1645 1646 /* 1647 * We may not get quite the right frequency if using 1648 * approximate clocks so look for the closest match that is 1649 * higher than the target (we need to ensure that there enough 1650 * BCLKs to clock out the samples). 1651 */ 1652 best = 0; 1653 bclk = 0; 1654 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 1655 cur_val = (wm8995->aifclk[dai->id] * 10 / bclk_divs[i]) - bclk_rate; 1656 if (cur_val < 0) /* BCLK table is sorted */ 1657 break; 1658 best = i; 1659 } 1660 bclk |= best << WM8995_AIF1_BCLK_DIV_SHIFT; 1661 1662 bclk_rate = wm8995->aifclk[dai->id] * 10 / bclk_divs[best]; 1663 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", 1664 bclk_divs[best], bclk_rate); 1665 1666 lrclk = bclk_rate / params_rate(params); 1667 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", 1668 lrclk, bclk_rate / lrclk); 1669 1670 snd_soc_update_bits(codec, aif1_reg, 1671 WM8995_AIF1_WL_MASK, aif1); 1672 snd_soc_update_bits(codec, bclk_reg, 1673 WM8995_AIF1_BCLK_DIV_MASK, bclk); 1674 snd_soc_update_bits(codec, lrclk_reg, 1675 WM8995_AIF1DAC_RATE_MASK, lrclk); 1676 snd_soc_update_bits(codec, rate_reg, 1677 WM8995_AIF1_SR_MASK | 1678 WM8995_AIF1CLK_RATE_MASK, rate_val); 1679 return 0; 1680} 1681 1682static int wm8995_set_tristate(struct snd_soc_dai *codec_dai, int tristate) 1683{ 1684 struct snd_soc_codec *codec = codec_dai->codec; 1685 int reg, val, mask; 1686 1687 switch (codec_dai->id) { 1688 case 0: 1689 reg = WM8995_AIF1_MASTER_SLAVE; 1690 mask = WM8995_AIF1_TRI; 1691 break; 1692 case 1: 1693 reg = WM8995_AIF2_MASTER_SLAVE; 1694 mask = WM8995_AIF2_TRI; 1695 break; 1696 case 2: 1697 reg = WM8995_POWER_MANAGEMENT_5; 1698 mask = WM8995_AIF3_TRI; 1699 break; 1700 default: 1701 return -EINVAL; 1702 } 1703 1704 if (tristate) 1705 val = mask; 1706 else 1707 val = 0; 1708 1709 return snd_soc_update_bits(codec, reg, mask, val); 1710} 1711 1712/* The size in bits of the FLL divide multiplied by 10 1713 * to allow rounding later */ 1714#define FIXED_FLL_SIZE ((1 << 16) * 10) 1715 1716struct fll_div { 1717 u16 outdiv; 1718 u16 n; 1719 u16 k; 1720 u16 clk_ref_div; 1721 u16 fll_fratio; 1722}; 1723 1724static int wm8995_get_fll_config(struct fll_div *fll, 1725 int freq_in, int freq_out) 1726{ 1727 u64 Kpart; 1728 unsigned int K, Ndiv, Nmod; 1729 1730 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out); 1731 1732 /* Scale the input frequency down to <= 13.5MHz */ 1733 fll->clk_ref_div = 0; 1734 while (freq_in > 13500000) { 1735 fll->clk_ref_div++; 1736 freq_in /= 2; 1737 1738 if (fll->clk_ref_div > 3) 1739 return -EINVAL; 1740 } 1741 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in); 1742 1743 /* Scale the output to give 90MHz<=Fvco<=100MHz */ 1744 fll->outdiv = 3; 1745 while (freq_out * (fll->outdiv + 1) < 90000000) { 1746 fll->outdiv++; 1747 if (fll->outdiv > 63) 1748 return -EINVAL; 1749 } 1750 freq_out *= fll->outdiv + 1; 1751 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out); 1752 1753 if (freq_in > 1000000) { 1754 fll->fll_fratio = 0; 1755 } else if (freq_in > 256000) { 1756 fll->fll_fratio = 1; 1757 freq_in *= 2; 1758 } else if (freq_in > 128000) { 1759 fll->fll_fratio = 2; 1760 freq_in *= 4; 1761 } else if (freq_in > 64000) { 1762 fll->fll_fratio = 3; 1763 freq_in *= 8; 1764 } else { 1765 fll->fll_fratio = 4; 1766 freq_in *= 16; 1767 } 1768 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in); 1769 1770 /* Now, calculate N.K */ 1771 Ndiv = freq_out / freq_in; 1772 1773 fll->n = Ndiv; 1774 Nmod = freq_out % freq_in; 1775 pr_debug("Nmod=%d\n", Nmod); 1776 1777 /* Calculate fractional part - scale up so we can round. */ 1778 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 1779 1780 do_div(Kpart, freq_in); 1781 1782 K = Kpart & 0xFFFFFFFF; 1783 1784 if ((K % 10) >= 5) 1785 K += 5; 1786 1787 /* Move down to proper range now rounding is done */ 1788 fll->k = K / 10; 1789 1790 pr_debug("N=%x K=%x\n", fll->n, fll->k); 1791 1792 return 0; 1793} 1794 1795static int wm8995_set_fll(struct snd_soc_dai *dai, int id, 1796 int src, unsigned int freq_in, 1797 unsigned int freq_out) 1798{ 1799 struct snd_soc_codec *codec; 1800 struct wm8995_priv *wm8995; 1801 int reg_offset, ret; 1802 struct fll_div fll; 1803 u16 reg, aif1, aif2; 1804 1805 codec = dai->codec; 1806 wm8995 = snd_soc_codec_get_drvdata(codec); 1807 1808 aif1 = snd_soc_read(codec, WM8995_AIF1_CLOCKING_1) 1809 & WM8995_AIF1CLK_ENA; 1810 1811 aif2 = snd_soc_read(codec, WM8995_AIF2_CLOCKING_1) 1812 & WM8995_AIF2CLK_ENA; 1813 1814 switch (id) { 1815 case WM8995_FLL1: 1816 reg_offset = 0; 1817 id = 0; 1818 break; 1819 case WM8995_FLL2: 1820 reg_offset = 0x20; 1821 id = 1; 1822 break; 1823 default: 1824 return -EINVAL; 1825 } 1826 1827 switch (src) { 1828 case 0: 1829 /* Allow no source specification when stopping */ 1830 if (freq_out) 1831 return -EINVAL; 1832 break; 1833 case WM8995_FLL_SRC_MCLK1: 1834 case WM8995_FLL_SRC_MCLK2: 1835 case WM8995_FLL_SRC_LRCLK: 1836 case WM8995_FLL_SRC_BCLK: 1837 break; 1838 default: 1839 return -EINVAL; 1840 } 1841 1842 /* Are we changing anything? */ 1843 if (wm8995->fll[id].src == src && 1844 wm8995->fll[id].in == freq_in && wm8995->fll[id].out == freq_out) 1845 return 0; 1846 1847 /* If we're stopping the FLL redo the old config - no 1848 * registers will actually be written but we avoid GCC flow 1849 * analysis bugs spewing warnings. 1850 */ 1851 if (freq_out) 1852 ret = wm8995_get_fll_config(&fll, freq_in, freq_out); 1853 else 1854 ret = wm8995_get_fll_config(&fll, wm8995->fll[id].in, 1855 wm8995->fll[id].out); 1856 if (ret < 0) 1857 return ret; 1858 1859 /* Gate the AIF clocks while we reclock */ 1860 snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1, 1861 WM8995_AIF1CLK_ENA_MASK, 0); 1862 snd_soc_update_bits(codec, WM8995_AIF2_CLOCKING_1, 1863 WM8995_AIF2CLK_ENA_MASK, 0); 1864 1865 /* We always need to disable the FLL while reconfiguring */ 1866 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_1 + reg_offset, 1867 WM8995_FLL1_ENA_MASK, 0); 1868 1869 reg = (fll.outdiv << WM8995_FLL1_OUTDIV_SHIFT) | 1870 (fll.fll_fratio << WM8995_FLL1_FRATIO_SHIFT); 1871 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_2 + reg_offset, 1872 WM8995_FLL1_OUTDIV_MASK | 1873 WM8995_FLL1_FRATIO_MASK, reg); 1874 1875 snd_soc_write(codec, WM8995_FLL1_CONTROL_3 + reg_offset, fll.k); 1876 1877 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_4 + reg_offset, 1878 WM8995_FLL1_N_MASK, 1879 fll.n << WM8995_FLL1_N_SHIFT); 1880 1881 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_5 + reg_offset, 1882 WM8995_FLL1_REFCLK_DIV_MASK | 1883 WM8995_FLL1_REFCLK_SRC_MASK, 1884 (fll.clk_ref_div << WM8995_FLL1_REFCLK_DIV_SHIFT) | 1885 (src - 1)); 1886 1887 if (freq_out) 1888 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_1 + reg_offset, 1889 WM8995_FLL1_ENA_MASK, WM8995_FLL1_ENA); 1890 1891 wm8995->fll[id].in = freq_in; 1892 wm8995->fll[id].out = freq_out; 1893 wm8995->fll[id].src = src; 1894 1895 /* Enable any gated AIF clocks */ 1896 snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1, 1897 WM8995_AIF1CLK_ENA_MASK, aif1); 1898 snd_soc_update_bits(codec, WM8995_AIF2_CLOCKING_1, 1899 WM8995_AIF2CLK_ENA_MASK, aif2); 1900 1901 configure_clock(codec); 1902 1903 return 0; 1904} 1905 1906static int wm8995_set_dai_sysclk(struct snd_soc_dai *dai, 1907 int clk_id, unsigned int freq, int dir) 1908{ 1909 struct snd_soc_codec *codec; 1910 struct wm8995_priv *wm8995; 1911 1912 codec = dai->codec; 1913 wm8995 = snd_soc_codec_get_drvdata(codec); 1914 1915 switch (dai->id) { 1916 case 0: 1917 case 1: 1918 break; 1919 default: 1920 /* AIF3 shares clocking with AIF1/2 */ 1921 return -EINVAL; 1922 } 1923 1924 switch (clk_id) { 1925 case WM8995_SYSCLK_MCLK1: 1926 wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1; 1927 wm8995->mclk[0] = freq; 1928 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n", 1929 dai->id + 1, freq); 1930 break; 1931 case WM8995_SYSCLK_MCLK2: 1932 wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1; 1933 wm8995->mclk[1] = freq; 1934 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n", 1935 dai->id + 1, freq); 1936 break; 1937 case WM8995_SYSCLK_FLL1: 1938 wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL1; 1939 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id + 1); 1940 break; 1941 case WM8995_SYSCLK_FLL2: 1942 wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL2; 1943 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id + 1); 1944 break; 1945 case WM8995_SYSCLK_OPCLK: 1946 default: 1947 dev_err(dai->dev, "Unknown clock source %d\n", clk_id); 1948 return -EINVAL; 1949 } 1950 1951 configure_clock(codec); 1952 1953 return 0; 1954} 1955 1956static int wm8995_set_bias_level(struct snd_soc_codec *codec, 1957 enum snd_soc_bias_level level) 1958{ 1959 struct wm8995_priv *wm8995; 1960 int ret; 1961 1962 wm8995 = snd_soc_codec_get_drvdata(codec); 1963 switch (level) { 1964 case SND_SOC_BIAS_ON: 1965 case SND_SOC_BIAS_PREPARE: 1966 break; 1967 case SND_SOC_BIAS_STANDBY: 1968 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1969 ret = regulator_bulk_enable(ARRAY_SIZE(wm8995->supplies), 1970 wm8995->supplies); 1971 if (ret) 1972 return ret; 1973 1974 ret = regcache_sync(wm8995->regmap); 1975 if (ret) { 1976 dev_err(codec->dev, 1977 "Failed to sync cache: %d\n", ret); 1978 return ret; 1979 } 1980 1981 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, 1982 WM8995_BG_ENA_MASK, WM8995_BG_ENA); 1983 } 1984 break; 1985 case SND_SOC_BIAS_OFF: 1986 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, 1987 WM8995_BG_ENA_MASK, 0); 1988 regulator_bulk_disable(ARRAY_SIZE(wm8995->supplies), 1989 wm8995->supplies); 1990 break; 1991 } 1992 1993 codec->dapm.bias_level = level; 1994 return 0; 1995} 1996 1997static int wm8995_remove(struct snd_soc_codec *codec) 1998{ 1999 struct wm8995_priv *wm8995; 2000 int i; 2001 2002 wm8995 = snd_soc_codec_get_drvdata(codec); 2003 2004 for (i = 0; i < ARRAY_SIZE(wm8995->supplies); ++i) 2005 regulator_unregister_notifier(wm8995->supplies[i].consumer, 2006 &wm8995->disable_nb[i]); 2007 2008 regulator_bulk_free(ARRAY_SIZE(wm8995->supplies), wm8995->supplies); 2009 return 0; 2010} 2011 2012static int wm8995_probe(struct snd_soc_codec *codec) 2013{ 2014 struct wm8995_priv *wm8995; 2015 int i; 2016 int ret; 2017 2018 wm8995 = snd_soc_codec_get_drvdata(codec); 2019 wm8995->codec = codec; 2020 2021 for (i = 0; i < ARRAY_SIZE(wm8995->supplies); i++) 2022 wm8995->supplies[i].supply = wm8995_supply_names[i]; 2023 2024 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8995->supplies), 2025 wm8995->supplies); 2026 if (ret) { 2027 dev_err(codec->dev, "Failed to request supplies: %d\n", ret); 2028 return ret; 2029 } 2030 2031 wm8995->disable_nb[0].notifier_call = wm8995_regulator_event_0; 2032 wm8995->disable_nb[1].notifier_call = wm8995_regulator_event_1; 2033 wm8995->disable_nb[2].notifier_call = wm8995_regulator_event_2; 2034 wm8995->disable_nb[3].notifier_call = wm8995_regulator_event_3; 2035 wm8995->disable_nb[4].notifier_call = wm8995_regulator_event_4; 2036 wm8995->disable_nb[5].notifier_call = wm8995_regulator_event_5; 2037 wm8995->disable_nb[6].notifier_call = wm8995_regulator_event_6; 2038 wm8995->disable_nb[7].notifier_call = wm8995_regulator_event_7; 2039 2040 /* This should really be moved into the regulator core */ 2041 for (i = 0; i < ARRAY_SIZE(wm8995->supplies); i++) { 2042 ret = regulator_register_notifier(wm8995->supplies[i].consumer, 2043 &wm8995->disable_nb[i]); 2044 if (ret) { 2045 dev_err(codec->dev, 2046 "Failed to register regulator notifier: %d\n", 2047 ret); 2048 } 2049 } 2050 2051 ret = regulator_bulk_enable(ARRAY_SIZE(wm8995->supplies), 2052 wm8995->supplies); 2053 if (ret) { 2054 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); 2055 goto err_reg_get; 2056 } 2057 2058 ret = snd_soc_read(codec, WM8995_SOFTWARE_RESET); 2059 if (ret < 0) { 2060 dev_err(codec->dev, "Failed to read device ID: %d\n", ret); 2061 goto err_reg_enable; 2062 } 2063 2064 if (ret != 0x8995) { 2065 dev_err(codec->dev, "Invalid device ID: %#x\n", ret); 2066 ret = -EINVAL; 2067 goto err_reg_enable; 2068 } 2069 2070 ret = snd_soc_write(codec, WM8995_SOFTWARE_RESET, 0); 2071 if (ret < 0) { 2072 dev_err(codec->dev, "Failed to issue reset: %d\n", ret); 2073 goto err_reg_enable; 2074 } 2075 2076 /* Latch volume updates (right only; we always do left then right). */ 2077 snd_soc_update_bits(codec, WM8995_AIF1_DAC1_RIGHT_VOLUME, 2078 WM8995_AIF1DAC1_VU_MASK, WM8995_AIF1DAC1_VU); 2079 snd_soc_update_bits(codec, WM8995_AIF1_DAC2_RIGHT_VOLUME, 2080 WM8995_AIF1DAC2_VU_MASK, WM8995_AIF1DAC2_VU); 2081 snd_soc_update_bits(codec, WM8995_AIF2_DAC_RIGHT_VOLUME, 2082 WM8995_AIF2DAC_VU_MASK, WM8995_AIF2DAC_VU); 2083 snd_soc_update_bits(codec, WM8995_AIF1_ADC1_RIGHT_VOLUME, 2084 WM8995_AIF1ADC1_VU_MASK, WM8995_AIF1ADC1_VU); 2085 snd_soc_update_bits(codec, WM8995_AIF1_ADC2_RIGHT_VOLUME, 2086 WM8995_AIF1ADC2_VU_MASK, WM8995_AIF1ADC2_VU); 2087 snd_soc_update_bits(codec, WM8995_AIF2_ADC_RIGHT_VOLUME, 2088 WM8995_AIF2ADC_VU_MASK, WM8995_AIF1ADC2_VU); 2089 snd_soc_update_bits(codec, WM8995_DAC1_RIGHT_VOLUME, 2090 WM8995_DAC1_VU_MASK, WM8995_DAC1_VU); 2091 snd_soc_update_bits(codec, WM8995_DAC2_RIGHT_VOLUME, 2092 WM8995_DAC2_VU_MASK, WM8995_DAC2_VU); 2093 snd_soc_update_bits(codec, WM8995_RIGHT_LINE_INPUT_1_VOLUME, 2094 WM8995_IN1_VU_MASK, WM8995_IN1_VU); 2095 2096 wm8995_update_class_w(codec); 2097 2098 return 0; 2099 2100err_reg_enable: 2101 regulator_bulk_disable(ARRAY_SIZE(wm8995->supplies), wm8995->supplies); 2102err_reg_get: 2103 regulator_bulk_free(ARRAY_SIZE(wm8995->supplies), wm8995->supplies); 2104 return ret; 2105} 2106 2107#define WM8995_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 2108 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 2109 2110static const struct snd_soc_dai_ops wm8995_aif1_dai_ops = { 2111 .set_sysclk = wm8995_set_dai_sysclk, 2112 .set_fmt = wm8995_set_dai_fmt, 2113 .hw_params = wm8995_hw_params, 2114 .digital_mute = wm8995_aif_mute, 2115 .set_pll = wm8995_set_fll, 2116 .set_tristate = wm8995_set_tristate, 2117}; 2118 2119static const struct snd_soc_dai_ops wm8995_aif2_dai_ops = { 2120 .set_sysclk = wm8995_set_dai_sysclk, 2121 .set_fmt = wm8995_set_dai_fmt, 2122 .hw_params = wm8995_hw_params, 2123 .digital_mute = wm8995_aif_mute, 2124 .set_pll = wm8995_set_fll, 2125 .set_tristate = wm8995_set_tristate, 2126}; 2127 2128static const struct snd_soc_dai_ops wm8995_aif3_dai_ops = { 2129 .set_tristate = wm8995_set_tristate, 2130}; 2131 2132static struct snd_soc_dai_driver wm8995_dai[] = { 2133 { 2134 .name = "wm8995-aif1", 2135 .playback = { 2136 .stream_name = "AIF1 Playback", 2137 .channels_min = 2, 2138 .channels_max = 2, 2139 .rates = SNDRV_PCM_RATE_8000_96000, 2140 .formats = WM8995_FORMATS 2141 }, 2142 .capture = { 2143 .stream_name = "AIF1 Capture", 2144 .channels_min = 2, 2145 .channels_max = 2, 2146 .rates = SNDRV_PCM_RATE_8000_48000, 2147 .formats = WM8995_FORMATS 2148 }, 2149 .ops = &wm8995_aif1_dai_ops 2150 }, 2151 { 2152 .name = "wm8995-aif2", 2153 .playback = { 2154 .stream_name = "AIF2 Playback", 2155 .channels_min = 2, 2156 .channels_max = 2, 2157 .rates = SNDRV_PCM_RATE_8000_96000, 2158 .formats = WM8995_FORMATS 2159 }, 2160 .capture = { 2161 .stream_name = "AIF2 Capture", 2162 .channels_min = 2, 2163 .channels_max = 2, 2164 .rates = SNDRV_PCM_RATE_8000_48000, 2165 .formats = WM8995_FORMATS 2166 }, 2167 .ops = &wm8995_aif2_dai_ops 2168 }, 2169 { 2170 .name = "wm8995-aif3", 2171 .playback = { 2172 .stream_name = "AIF3 Playback", 2173 .channels_min = 2, 2174 .channels_max = 2, 2175 .rates = SNDRV_PCM_RATE_8000_96000, 2176 .formats = WM8995_FORMATS 2177 }, 2178 .capture = { 2179 .stream_name = "AIF3 Capture", 2180 .channels_min = 2, 2181 .channels_max = 2, 2182 .rates = SNDRV_PCM_RATE_8000_48000, 2183 .formats = WM8995_FORMATS 2184 }, 2185 .ops = &wm8995_aif3_dai_ops 2186 } 2187}; 2188 2189static const struct snd_soc_codec_driver soc_codec_dev_wm8995 = { 2190 .probe = wm8995_probe, 2191 .remove = wm8995_remove, 2192 .set_bias_level = wm8995_set_bias_level, 2193 .idle_bias_off = true, 2194 2195 .controls = wm8995_snd_controls, 2196 .num_controls = ARRAY_SIZE(wm8995_snd_controls), 2197 .dapm_widgets = wm8995_dapm_widgets, 2198 .num_dapm_widgets = ARRAY_SIZE(wm8995_dapm_widgets), 2199 .dapm_routes = wm8995_intercon, 2200 .num_dapm_routes = ARRAY_SIZE(wm8995_intercon), 2201}; 2202 2203static const struct regmap_config wm8995_regmap = { 2204 .reg_bits = 16, 2205 .val_bits = 16, 2206 2207 .max_register = WM8995_MAX_REGISTER, 2208 .reg_defaults = wm8995_reg_defaults, 2209 .num_reg_defaults = ARRAY_SIZE(wm8995_reg_defaults), 2210 .volatile_reg = wm8995_volatile, 2211 .readable_reg = wm8995_readable, 2212 .cache_type = REGCACHE_RBTREE, 2213}; 2214 2215#if defined(CONFIG_SPI_MASTER) 2216static int wm8995_spi_probe(struct spi_device *spi) 2217{ 2218 struct wm8995_priv *wm8995; 2219 int ret; 2220 2221 wm8995 = devm_kzalloc(&spi->dev, sizeof(*wm8995), GFP_KERNEL); 2222 if (!wm8995) 2223 return -ENOMEM; 2224 2225 spi_set_drvdata(spi, wm8995); 2226 2227 wm8995->regmap = devm_regmap_init_spi(spi, &wm8995_regmap); 2228 if (IS_ERR(wm8995->regmap)) { 2229 ret = PTR_ERR(wm8995->regmap); 2230 dev_err(&spi->dev, "Failed to register regmap: %d\n", ret); 2231 return ret; 2232 } 2233 2234 ret = snd_soc_register_codec(&spi->dev, 2235 &soc_codec_dev_wm8995, wm8995_dai, 2236 ARRAY_SIZE(wm8995_dai)); 2237 return ret; 2238} 2239 2240static int wm8995_spi_remove(struct spi_device *spi) 2241{ 2242 snd_soc_unregister_codec(&spi->dev); 2243 return 0; 2244} 2245 2246static struct spi_driver wm8995_spi_driver = { 2247 .driver = { 2248 .name = "wm8995", 2249 .owner = THIS_MODULE, 2250 }, 2251 .probe = wm8995_spi_probe, 2252 .remove = wm8995_spi_remove 2253}; 2254#endif 2255 2256#if IS_ENABLED(CONFIG_I2C) 2257static int wm8995_i2c_probe(struct i2c_client *i2c, 2258 const struct i2c_device_id *id) 2259{ 2260 struct wm8995_priv *wm8995; 2261 int ret; 2262 2263 wm8995 = devm_kzalloc(&i2c->dev, sizeof(*wm8995), GFP_KERNEL); 2264 if (!wm8995) 2265 return -ENOMEM; 2266 2267 i2c_set_clientdata(i2c, wm8995); 2268 2269 wm8995->regmap = devm_regmap_init_i2c(i2c, &wm8995_regmap); 2270 if (IS_ERR(wm8995->regmap)) { 2271 ret = PTR_ERR(wm8995->regmap); 2272 dev_err(&i2c->dev, "Failed to register regmap: %d\n", ret); 2273 return ret; 2274 } 2275 2276 ret = snd_soc_register_codec(&i2c->dev, 2277 &soc_codec_dev_wm8995, wm8995_dai, 2278 ARRAY_SIZE(wm8995_dai)); 2279 if (ret < 0) 2280 dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret); 2281 2282 return ret; 2283} 2284 2285static int wm8995_i2c_remove(struct i2c_client *client) 2286{ 2287 snd_soc_unregister_codec(&client->dev); 2288 return 0; 2289} 2290 2291static const struct i2c_device_id wm8995_i2c_id[] = { 2292 {"wm8995", 0}, 2293 {} 2294}; 2295 2296MODULE_DEVICE_TABLE(i2c, wm8995_i2c_id); 2297 2298static struct i2c_driver wm8995_i2c_driver = { 2299 .driver = { 2300 .name = "wm8995", 2301 .owner = THIS_MODULE, 2302 }, 2303 .probe = wm8995_i2c_probe, 2304 .remove = wm8995_i2c_remove, 2305 .id_table = wm8995_i2c_id 2306}; 2307#endif 2308 2309static int __init wm8995_modinit(void) 2310{ 2311 int ret = 0; 2312 2313#if IS_ENABLED(CONFIG_I2C) 2314 ret = i2c_add_driver(&wm8995_i2c_driver); 2315 if (ret) { 2316 printk(KERN_ERR "Failed to register wm8995 I2C driver: %d\n", 2317 ret); 2318 } 2319#endif 2320#if defined(CONFIG_SPI_MASTER) 2321 ret = spi_register_driver(&wm8995_spi_driver); 2322 if (ret) { 2323 printk(KERN_ERR "Failed to register wm8995 SPI driver: %d\n", 2324 ret); 2325 } 2326#endif 2327 return ret; 2328} 2329 2330module_init(wm8995_modinit); 2331 2332static void __exit wm8995_exit(void) 2333{ 2334#if IS_ENABLED(CONFIG_I2C) 2335 i2c_del_driver(&wm8995_i2c_driver); 2336#endif 2337#if defined(CONFIG_SPI_MASTER) 2338 spi_unregister_driver(&wm8995_spi_driver); 2339#endif 2340} 2341 2342module_exit(wm8995_exit); 2343 2344MODULE_DESCRIPTION("ASoC WM8995 driver"); 2345MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>"); 2346MODULE_LICENSE("GPL"); 2347