PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 22843 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 15446 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 16777 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 16649 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 5671 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x00000000
PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 5618 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0
PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 6406 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0
PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 6940 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0