PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 22837 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 15440 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 16771 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 16643 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 5675 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x00000000
PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 5614 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0
PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 6402 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0
PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 6936 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0