PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 22840 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 15443 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 16774 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 16646 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 5677 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x00000000
PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 5616 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0
PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 6404 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0
PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 6938 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0