PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 22855 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 15458 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 16789 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 16661 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 5679 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x00000000
PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 5626 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0
PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 6414 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0
PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 6948 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0