PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 22849 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 15452 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 16783 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 16655 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 5683 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x00000000
PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 5622 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0
PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 6410 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0
PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 6944 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0