PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 22852 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 15455 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 16786 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 16658 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 5685 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x00000000
PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 5624 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0
PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 6412 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0
PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 6946 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0