PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 22867 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 15470 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 16801 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 16673 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 5687 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x00000000
PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 5634 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0
PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 6422 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0
PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 6956 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0