PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 22876 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 15479 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 16810 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 16682 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 5701 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x00000000
PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 5640 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0
PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 6428 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0
PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 6962 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0