PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 22882 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 15485 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 16816 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 16688 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 5705 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x00000000
PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 5644 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0
PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 6432 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0
PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 6966 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0