PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 22888 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 15491 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 16822 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 16694 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 5709 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x00000000
PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 5648 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0
PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 6436 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0
PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 6970 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0