PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 22894 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 15497 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 16828 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 16700 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 5713 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x00000000
PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 5652 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0
PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 6440 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0
PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 6974 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0