VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 27003 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT                                                             0x0
VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 28307 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT                                                             0x0
VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 28580 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT                                                             0x0
VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 9899 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h #define VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT                                                             0x0
VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 9562 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_sh_mask.h #define VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT                                                             0x0
VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 9989 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_sh_mask.h #define VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT                                                             0x0