MC_REGISTERS_TABLE_101__data_5_value_3_MASK 3481 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MC_REGISTERS_TABLE_101__data_5_value_3_MASK 0xffffffff
MC_REGISTERS_TABLE_101__data_5_value_3_MASK 3479 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MC_REGISTERS_TABLE_101__data_5_value_3_MASK 0xffffffff