MC_REGISTERS_TABLE_102__data_5_value_4__SHIFT 3484 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MC_REGISTERS_TABLE_102__data_5_value_4__SHIFT 0x0
MC_REGISTERS_TABLE_102__data_5_value_4__SHIFT 3482 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MC_REGISTERS_TABLE_102__data_5_value_4__SHIFT 0x0