MC_REGISTERS_TABLE_108__data_5_value_10__SHIFT 3496 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MC_REGISTERS_TABLE_108__data_5_value_10__SHIFT 0x0
MC_REGISTERS_TABLE_108__data_5_value_10__SHIFT 3494 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MC_REGISTERS_TABLE_108__data_5_value_10__SHIFT 0x0