MC_REGISTERS_TABLE_110__data_5_value_12_MASK 3499 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MC_REGISTERS_TABLE_110__data_5_value_12_MASK 0xffffffff
MC_REGISTERS_TABLE_110__data_5_value_12_MASK 3497 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MC_REGISTERS_TABLE_110__data_5_value_12_MASK 0xffffffff