MC_REGISTERS_TABLE_11__address_9_s1__SHIFT 3288 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MC_REGISTERS_TABLE_11__address_9_s1__SHIFT 0x0
MC_REGISTERS_TABLE_11__address_9_s1__SHIFT 3286 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MC_REGISTERS_TABLE_11__address_9_s1__SHIFT 0x0
MC_REGISTERS_TABLE_11__address_9_s1__SHIFT 1308 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define MC_REGISTERS_TABLE_11__address_9_s1__SHIFT 0x0
MC_REGISTERS_TABLE_11__address_9_s1__SHIFT 3512 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define MC_REGISTERS_TABLE_11__address_9_s1__SHIFT 0x0