MC_REGISTERS_TABLE_14__address_12_s1__SHIFT 3300 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MC_REGISTERS_TABLE_14__address_12_s1__SHIFT 0x0
MC_REGISTERS_TABLE_14__address_12_s1__SHIFT 3298 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MC_REGISTERS_TABLE_14__address_12_s1__SHIFT 0x0
MC_REGISTERS_TABLE_14__address_12_s1__SHIFT 1320 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define MC_REGISTERS_TABLE_14__address_12_s1__SHIFT 0x0
MC_REGISTERS_TABLE_14__address_12_s1__SHIFT 3524 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define MC_REGISTERS_TABLE_14__address_12_s1__SHIFT 0x0