MC_REGISTERS_TABLE_17__address_15_s1__SHIFT 3312 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MC_REGISTERS_TABLE_17__address_15_s1__SHIFT 0x0
MC_REGISTERS_TABLE_17__address_15_s1__SHIFT 3310 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MC_REGISTERS_TABLE_17__address_15_s1__SHIFT 0x0
MC_REGISTERS_TABLE_17__address_15_s1__SHIFT 1332 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define MC_REGISTERS_TABLE_17__address_15_s1__SHIFT 0x0
MC_REGISTERS_TABLE_17__address_15_s1__SHIFT 3536 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define MC_REGISTERS_TABLE_17__address_15_s1__SHIFT 0x0