MC_REGISTERS_TABLE_19__data_0_value_1__SHIFT 3318 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MC_REGISTERS_TABLE_19__data_0_value_1__SHIFT 0x0
MC_REGISTERS_TABLE_19__data_0_value_1__SHIFT 3316 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MC_REGISTERS_TABLE_19__data_0_value_1__SHIFT 0x0
MC_REGISTERS_TABLE_19__data_0_value_1__SHIFT 1338 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define MC_REGISTERS_TABLE_19__data_0_value_1__SHIFT 0x0
MC_REGISTERS_TABLE_19__data_0_value_1__SHIFT 3542 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define MC_REGISTERS_TABLE_19__data_0_value_1__SHIFT 0x0