MC_REGISTERS_TABLE_1__reserved_0__SHIFT 3248 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MC_REGISTERS_TABLE_1__reserved_0__SHIFT 0x10
MC_REGISTERS_TABLE_1__reserved_0__SHIFT 3246 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MC_REGISTERS_TABLE_1__reserved_0__SHIFT 0x10
MC_REGISTERS_TABLE_1__reserved_0__SHIFT 1268 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define MC_REGISTERS_TABLE_1__reserved_0__SHIFT 0x10
MC_REGISTERS_TABLE_1__reserved_0__SHIFT 3472 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define MC_REGISTERS_TABLE_1__reserved_0__SHIFT 0x10