MC_REGISTERS_TABLE_1__reserved_1__SHIFT 3246 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MC_REGISTERS_TABLE_1__reserved_1__SHIFT 0x8
MC_REGISTERS_TABLE_1__reserved_1__SHIFT 3244 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MC_REGISTERS_TABLE_1__reserved_1__SHIFT 0x8
MC_REGISTERS_TABLE_1__reserved_1__SHIFT 1266 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define MC_REGISTERS_TABLE_1__reserved_1__SHIFT 0x8
MC_REGISTERS_TABLE_1__reserved_1__SHIFT 3470 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define MC_REGISTERS_TABLE_1__reserved_1__SHIFT 0x8