MC_REGISTERS_TABLE_21__data_0_value_3__SHIFT 3322 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MC_REGISTERS_TABLE_21__data_0_value_3__SHIFT 0x0
MC_REGISTERS_TABLE_21__data_0_value_3__SHIFT 3320 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MC_REGISTERS_TABLE_21__data_0_value_3__SHIFT 0x0
MC_REGISTERS_TABLE_21__data_0_value_3__SHIFT 1342 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define MC_REGISTERS_TABLE_21__data_0_value_3__SHIFT 0x0
MC_REGISTERS_TABLE_21__data_0_value_3__SHIFT 3546 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define MC_REGISTERS_TABLE_21__data_0_value_3__SHIFT 0x0