MC_REGISTERS_TABLE_2__address_0_s1__SHIFT 3252 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MC_REGISTERS_TABLE_2__address_0_s1__SHIFT 0x0
MC_REGISTERS_TABLE_2__address_0_s1__SHIFT 3250 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MC_REGISTERS_TABLE_2__address_0_s1__SHIFT 0x0
MC_REGISTERS_TABLE_2__address_0_s1__SHIFT 1272 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define MC_REGISTERS_TABLE_2__address_0_s1__SHIFT 0x0
MC_REGISTERS_TABLE_2__address_0_s1__SHIFT 3476 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define MC_REGISTERS_TABLE_2__address_0_s1__SHIFT 0x0