MC_REGISTERS_TABLE_32__data_0_value_14__SHIFT 3344 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define MC_REGISTERS_TABLE_32__data_0_value_14__SHIFT 0x0
MC_REGISTERS_TABLE_32__data_0_value_14__SHIFT 3342 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define MC_REGISTERS_TABLE_32__data_0_value_14__SHIFT 0x0
MC_REGISTERS_TABLE_32__data_0_value_14__SHIFT 1364 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define MC_REGISTERS_TABLE_32__data_0_value_14__SHIFT 0x0
MC_REGISTERS_TABLE_32__data_0_value_14__SHIFT 3568 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define MC_REGISTERS_TABLE_32__data_0_value_14__SHIFT 0x0